1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qapi/qmp/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_SLI] = 0x12C17000, 61 [ASPEED_DEV_SLIIO] = 0x14C1E000, 62 [ASPEED_GIC_DIST] = 0x12200000, 63 [ASPEED_GIC_REDIST] = 0x12280000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_I2C] = 0x14C0F000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_RTC] = 0x12C0F000, 68 }; 69 70 #define AST2700_MAX_IRQ 256 71 72 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 73 static const int aspeed_soc_ast2700_irqmap[] = { 74 [ASPEED_DEV_UART0] = 132, 75 [ASPEED_DEV_UART1] = 132, 76 [ASPEED_DEV_UART2] = 132, 77 [ASPEED_DEV_UART3] = 132, 78 [ASPEED_DEV_UART4] = 8, 79 [ASPEED_DEV_UART5] = 132, 80 [ASPEED_DEV_UART6] = 132, 81 [ASPEED_DEV_UART7] = 132, 82 [ASPEED_DEV_UART8] = 132, 83 [ASPEED_DEV_UART9] = 132, 84 [ASPEED_DEV_UART10] = 132, 85 [ASPEED_DEV_UART11] = 132, 86 [ASPEED_DEV_UART12] = 132, 87 [ASPEED_DEV_FMC] = 131, 88 [ASPEED_DEV_SDMC] = 0, 89 [ASPEED_DEV_SCU] = 12, 90 [ASPEED_DEV_ADC] = 130, 91 [ASPEED_DEV_XDMA] = 5, 92 [ASPEED_DEV_EMMC] = 15, 93 [ASPEED_DEV_GPIO] = 130, 94 [ASPEED_DEV_RTC] = 13, 95 [ASPEED_DEV_TIMER1] = 16, 96 [ASPEED_DEV_TIMER2] = 17, 97 [ASPEED_DEV_TIMER3] = 18, 98 [ASPEED_DEV_TIMER4] = 19, 99 [ASPEED_DEV_TIMER5] = 20, 100 [ASPEED_DEV_TIMER6] = 21, 101 [ASPEED_DEV_TIMER7] = 22, 102 [ASPEED_DEV_TIMER8] = 23, 103 [ASPEED_DEV_WDT] = 131, 104 [ASPEED_DEV_PWM] = 131, 105 [ASPEED_DEV_LPC] = 128, 106 [ASPEED_DEV_IBT] = 128, 107 [ASPEED_DEV_I2C] = 130, 108 [ASPEED_DEV_PECI] = 133, 109 [ASPEED_DEV_ETH1] = 132, 110 [ASPEED_DEV_ETH2] = 132, 111 [ASPEED_DEV_ETH3] = 132, 112 [ASPEED_DEV_HACE] = 4, 113 [ASPEED_DEV_KCS] = 128, 114 [ASPEED_DEV_DP] = 28, 115 [ASPEED_DEV_I3C] = 131, 116 }; 117 118 /* GICINT 128 */ 119 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 120 [ASPEED_DEV_LPC] = 0, 121 [ASPEED_DEV_IBT] = 2, 122 [ASPEED_DEV_KCS] = 4, 123 }; 124 125 /* GICINT 130 */ 126 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 127 [ASPEED_DEV_I2C] = 0, 128 [ASPEED_DEV_ADC] = 16, 129 [ASPEED_DEV_GPIO] = 18, 130 }; 131 132 /* GICINT 131 */ 133 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 134 [ASPEED_DEV_I3C] = 0, 135 [ASPEED_DEV_WDT] = 16, 136 [ASPEED_DEV_FMC] = 25, 137 [ASPEED_DEV_PWM] = 29, 138 }; 139 140 /* GICINT 132 */ 141 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 142 [ASPEED_DEV_ETH1] = 0, 143 [ASPEED_DEV_ETH2] = 1, 144 [ASPEED_DEV_ETH3] = 2, 145 [ASPEED_DEV_UART0] = 7, 146 [ASPEED_DEV_UART1] = 8, 147 [ASPEED_DEV_UART2] = 9, 148 [ASPEED_DEV_UART3] = 10, 149 [ASPEED_DEV_UART5] = 11, 150 [ASPEED_DEV_UART6] = 12, 151 [ASPEED_DEV_UART7] = 13, 152 [ASPEED_DEV_UART8] = 14, 153 [ASPEED_DEV_UART9] = 15, 154 [ASPEED_DEV_UART10] = 16, 155 [ASPEED_DEV_UART11] = 17, 156 [ASPEED_DEV_UART12] = 18, 157 }; 158 159 /* GICINT 133 */ 160 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 161 [ASPEED_DEV_PECI] = 4, 162 }; 163 164 /* GICINT 128 ~ 136 */ 165 struct gic_intc_irq_info { 166 int irq; 167 const int *ptr; 168 }; 169 170 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 171 {128, aspeed_soc_ast2700_gic128_intcmap}, 172 {129, NULL}, 173 {130, aspeed_soc_ast2700_gic130_intcmap}, 174 {131, aspeed_soc_ast2700_gic131_intcmap}, 175 {132, aspeed_soc_ast2700_gic132_intcmap}, 176 {133, aspeed_soc_ast2700_gic133_intcmap}, 177 {134, NULL}, 178 {135, NULL}, 179 {136, NULL}, 180 }; 181 182 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 183 { 184 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 185 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 186 int i; 187 188 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 189 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 190 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 191 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 192 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 193 } 194 } 195 196 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 197 } 198 199 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 200 int index) 201 { 202 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 203 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 204 int i; 205 206 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 207 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 208 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 209 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 210 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); 211 } 212 } 213 214 /* 215 * Invalid orgate index, device irq should be 128 to 136. 216 */ 217 g_assert_not_reached(); 218 } 219 220 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 221 unsigned int size) 222 { 223 qemu_log_mask(LOG_GUEST_ERROR, 224 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 225 __func__, addr); 226 return 0; 227 } 228 229 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 230 unsigned int size) 231 { 232 AspeedSoCState *s = ASPEED_SOC(opaque); 233 ram_addr_t ram_size; 234 MemTxResult result; 235 236 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 237 &error_abort); 238 239 assert(ram_size > 0); 240 241 /* 242 * Emulate ddr capacity hardware behavior. 243 * If writes the data to the address which is beyond the ram size, 244 * it would write the data to the "address % ram_size". 245 */ 246 result = address_space_write(&s->dram_as, addr % ram_size, 247 MEMTXATTRS_UNSPECIFIED, &data, 4); 248 if (result != MEMTX_OK) { 249 qemu_log_mask(LOG_GUEST_ERROR, 250 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 251 ", data :0x%" PRIx64 "\n", 252 __func__, addr % ram_size, data); 253 } 254 } 255 256 static const MemoryRegionOps aspeed_ram_capacity_ops = { 257 .read = aspeed_ram_capacity_read, 258 .write = aspeed_ram_capacity_write, 259 .endianness = DEVICE_LITTLE_ENDIAN, 260 .valid = { 261 .min_access_size = 1, 262 .max_access_size = 8, 263 }, 264 }; 265 266 /* 267 * SDMC should be realized first to get correct RAM size and max size 268 * values 269 */ 270 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 271 { 272 ram_addr_t ram_size, max_ram_size; 273 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 274 AspeedSoCState *s = ASPEED_SOC(dev); 275 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 276 277 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 278 &error_abort); 279 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 280 &error_abort); 281 282 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 283 ram_size); 284 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 285 address_space_init(&s->dram_as, s->dram_mr, "dram"); 286 287 /* 288 * Add a memory region beyond the RAM region to emulate 289 * ddr capacity hardware behavior. 290 */ 291 if (ram_size < max_ram_size) { 292 memory_region_init_io(&a->dram_empty, OBJECT(s), 293 &aspeed_ram_capacity_ops, s, 294 "ram-empty", max_ram_size - ram_size); 295 296 memory_region_add_subregion(s->memory, 297 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 298 &a->dram_empty); 299 } 300 301 memory_region_add_subregion(s->memory, 302 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 303 return true; 304 } 305 306 static void aspeed_soc_ast2700_init(Object *obj) 307 { 308 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 309 AspeedSoCState *s = ASPEED_SOC(obj); 310 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 311 int i; 312 char socname[8]; 313 char typename[64]; 314 315 if (sscanf(sc->name, "%7s", socname) != 1) { 316 g_assert_not_reached(); 317 } 318 319 for (i = 0; i < sc->num_cpus; i++) { 320 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 321 aspeed_soc_cpu_type(sc)); 322 } 323 324 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 325 326 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 327 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 328 sc->silicon_rev); 329 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 330 "hw-strap1"); 331 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 332 "hw-strap2"); 333 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 334 "hw-prot-key"); 335 336 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 337 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 338 sc->silicon_rev); 339 340 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 341 object_initialize_child(obj, "fmc", &s->fmc, typename); 342 343 for (i = 0; i < sc->spis_num; i++) { 344 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 345 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 346 } 347 348 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 349 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 350 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 351 "ram-size"); 352 353 for (i = 0; i < sc->wdts_num; i++) { 354 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 355 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 356 } 357 358 for (i = 0; i < sc->macs_num; i++) { 359 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 360 TYPE_FTGMAC100); 361 362 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 363 } 364 365 for (i = 0; i < sc->uarts_num; i++) { 366 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 367 } 368 369 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 370 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 371 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 372 373 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 374 object_initialize_child(obj, "adc", &s->adc, typename); 375 376 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 377 object_initialize_child(obj, "i2c", &s->i2c, typename); 378 379 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 380 object_initialize_child(obj, "gpio", &s->gpio, typename); 381 382 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 383 } 384 385 /* 386 * ASPEED ast2700 has 0x0 as cluster ID 387 * 388 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 389 */ 390 static uint64_t aspeed_calc_affinity(int cpu) 391 { 392 return (0x0 << ARM_AFF1_SHIFT) | cpu; 393 } 394 395 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 396 { 397 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 398 AspeedSoCState *s = ASPEED_SOC(dev); 399 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 400 SysBusDevice *gicbusdev; 401 DeviceState *gicdev; 402 QList *redist_region_count; 403 int i; 404 405 gicbusdev = SYS_BUS_DEVICE(&a->gic); 406 gicdev = DEVICE(&a->gic); 407 qdev_prop_set_uint32(gicdev, "revision", 3); 408 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 409 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 410 411 redist_region_count = qlist_new(); 412 qlist_append_int(redist_region_count, sc->num_cpus); 413 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 414 415 if (!sysbus_realize(gicbusdev, errp)) { 416 return false; 417 } 418 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 419 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 420 421 for (i = 0; i < sc->num_cpus; i++) { 422 DeviceState *cpudev = DEVICE(&a->cpu[i]); 423 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 424 425 const int timer_irq[] = { 426 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 427 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 428 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 429 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 430 }; 431 int j; 432 433 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 434 qdev_connect_gpio_out(cpudev, j, 435 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 436 } 437 438 qemu_irq irq = qdev_get_gpio_in(gicdev, 439 intidbase + ARCH_GIC_MAINT_IRQ); 440 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 441 0, irq); 442 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 443 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 444 445 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 446 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 447 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 448 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 449 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 450 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 451 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 452 } 453 454 return true; 455 } 456 457 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 458 { 459 int i; 460 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 461 AspeedSoCState *s = ASPEED_SOC(dev); 462 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 463 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 464 g_autofree char *sram_name = NULL; 465 qemu_irq irq; 466 467 /* Default boot region (SPI memory or ROMs) */ 468 memory_region_init(&s->spi_boot_container, OBJECT(s), 469 "aspeed.spi_boot_container", 0x400000000); 470 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 471 &s->spi_boot_container); 472 473 /* CPU */ 474 for (i = 0; i < sc->num_cpus; i++) { 475 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 476 aspeed_calc_affinity(i), &error_abort); 477 478 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 479 &error_abort); 480 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 481 OBJECT(s->memory), &error_abort); 482 483 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 484 return; 485 } 486 } 487 488 /* GIC */ 489 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 490 return; 491 } 492 493 /* INTC */ 494 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 495 return; 496 } 497 498 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 499 sc->memmap[ASPEED_DEV_INTC]); 500 501 /* GICINT orgates -> INTC -> GIC */ 502 for (i = 0; i < ic->num_ints; i++) { 503 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 504 qdev_get_gpio_in(DEVICE(&a->intc), i)); 505 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 506 qdev_get_gpio_in(DEVICE(&a->gic), 507 aspeed_soc_ast2700_gic_intcmap[i].irq)); 508 } 509 510 /* SRAM */ 511 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 512 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 513 errp)) { 514 return; 515 } 516 memory_region_add_subregion(s->memory, 517 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 518 519 /* SCU */ 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 521 return; 522 } 523 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 524 525 /* SCU1 */ 526 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 527 return; 528 } 529 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 530 sc->memmap[ASPEED_DEV_SCUIO]); 531 532 /* UART */ 533 if (!aspeed_soc_uart_realize(s, errp)) { 534 return; 535 } 536 537 /* FMC, The number of CS is set at the board level */ 538 object_property_set_int(OBJECT(&s->fmc), "dram-base", 539 sc->memmap[ASPEED_DEV_SDRAM], 540 &error_abort); 541 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 542 &error_abort); 543 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 544 return; 545 } 546 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 547 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 548 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 549 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 550 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 551 552 /* Set up an alias on the FMC CE0 region (boot default) */ 553 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 554 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 555 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 556 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 557 558 /* SPI */ 559 for (i = 0; i < sc->spis_num; i++) { 560 object_property_set_link(OBJECT(&s->spi[i]), "dram", 561 OBJECT(s->dram_mr), &error_abort); 562 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 563 return; 564 } 565 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 566 sc->memmap[ASPEED_DEV_SPI0 + i]); 567 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 568 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 569 } 570 571 /* 572 * SDMC - SDRAM Memory Controller 573 * The SDMC controller is unlocked at SPL stage. 574 * At present, only supports to emulate booting 575 * start from u-boot stage. Set SDMC controller 576 * unlocked by default. It is a temporarily solution. 577 */ 578 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 579 &error_abort); 580 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 581 return; 582 } 583 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 584 sc->memmap[ASPEED_DEV_SDMC]); 585 586 /* RAM */ 587 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 588 return; 589 } 590 591 /* Net */ 592 for (i = 0; i < sc->macs_num; i++) { 593 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 594 &error_abort); 595 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 596 &error_abort); 597 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 598 return; 599 } 600 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 601 sc->memmap[ASPEED_DEV_ETH1 + i]); 602 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 603 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 604 605 object_property_set_link(OBJECT(&s->mii[i]), "nic", 606 OBJECT(&s->ftgmac100[i]), &error_abort); 607 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 608 return; 609 } 610 611 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 612 sc->memmap[ASPEED_DEV_MII1 + i]); 613 } 614 615 /* Watch dog */ 616 for (i = 0; i < sc->wdts_num; i++) { 617 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 618 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 619 620 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 621 &error_abort); 622 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 623 return; 624 } 625 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 626 } 627 628 /* SLI */ 629 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 630 return; 631 } 632 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 633 634 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 635 return; 636 } 637 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 638 sc->memmap[ASPEED_DEV_SLIIO]); 639 640 /* ADC */ 641 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 642 return; 643 } 644 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 645 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 646 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 647 648 /* I2C */ 649 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 650 &error_abort); 651 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 652 return; 653 } 654 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 655 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 656 /* 657 * The AST2700 I2C controller has one source INTC per bus. 658 * I2C buses interrupt are connected to GICINT130_INTC 659 * from bit 0 to bit 15. 660 * I2C bus 0 is connected to GICINT130_INTC at bit 0. 661 * I2C bus 15 is connected to GICINT130_INTC at bit 15. 662 */ 663 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 664 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 665 } 666 667 /* GPIO */ 668 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 669 return; 670 } 671 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 672 sc->memmap[ASPEED_DEV_GPIO]); 673 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 674 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 675 676 /* RTC */ 677 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 678 return; 679 } 680 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 681 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 682 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 683 684 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 685 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 686 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 687 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 688 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 689 } 690 691 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 692 { 693 static const char * const valid_cpu_types[] = { 694 ARM_CPU_TYPE_NAME("cortex-a35"), 695 NULL 696 }; 697 DeviceClass *dc = DEVICE_CLASS(oc); 698 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 699 700 /* Reason: The Aspeed SoC can only be instantiated from a board */ 701 dc->user_creatable = false; 702 dc->realize = aspeed_soc_ast2700_realize; 703 704 sc->name = "ast2700-a0"; 705 sc->valid_cpu_types = valid_cpu_types; 706 sc->silicon_rev = AST2700_A0_SILICON_REV; 707 sc->sram_size = 0x20000; 708 sc->spis_num = 3; 709 sc->wdts_num = 8; 710 sc->macs_num = 1; 711 sc->uarts_num = 13; 712 sc->num_cpus = 4; 713 sc->uarts_base = ASPEED_DEV_UART0; 714 sc->irqmap = aspeed_soc_ast2700_irqmap; 715 sc->memmap = aspeed_soc_ast2700_memmap; 716 sc->get_irq = aspeed_soc_ast2700_get_irq; 717 } 718 719 static const TypeInfo aspeed_soc_ast27x0_types[] = { 720 { 721 .name = TYPE_ASPEED27X0_SOC, 722 .parent = TYPE_ASPEED_SOC, 723 .instance_size = sizeof(Aspeed27x0SoCState), 724 .abstract = true, 725 }, { 726 .name = "ast2700-a0", 727 .parent = TYPE_ASPEED27X0_SOC, 728 .instance_init = aspeed_soc_ast2700_init, 729 .class_init = aspeed_soc_ast2700_class_init, 730 }, 731 }; 732 733 DEFINE_TYPES(aspeed_soc_ast27x0_types) 734