1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "qemu/module.h" 17 #include "qemu/error-report.h" 18 #include "hw/i2c/aspeed_i2c.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/intc/arm_gicv3.h" 22 #include "qapi/qmp/qlist.h" 23 #include "qemu/log.h" 24 25 static const hwaddr aspeed_soc_ast2700_memmap[] = { 26 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 [ASPEED_DEV_SDMC] = 0x12C00000, 29 [ASPEED_DEV_SCU] = 0x12C02000, 30 [ASPEED_DEV_SCUIO] = 0x14C02000, 31 [ASPEED_DEV_UART0] = 0X14C33000, 32 [ASPEED_DEV_UART1] = 0X14C33100, 33 [ASPEED_DEV_UART2] = 0X14C33200, 34 [ASPEED_DEV_UART3] = 0X14C33300, 35 [ASPEED_DEV_UART4] = 0X12C1A000, 36 [ASPEED_DEV_UART5] = 0X14C33400, 37 [ASPEED_DEV_UART6] = 0X14C33500, 38 [ASPEED_DEV_UART7] = 0X14C33600, 39 [ASPEED_DEV_UART8] = 0X14C33700, 40 [ASPEED_DEV_UART9] = 0X14C33800, 41 [ASPEED_DEV_UART10] = 0X14C33900, 42 [ASPEED_DEV_UART11] = 0X14C33A00, 43 [ASPEED_DEV_UART12] = 0X14C33B00, 44 [ASPEED_DEV_WDT] = 0x14C37000, 45 [ASPEED_DEV_VUART] = 0X14C30000, 46 [ASPEED_DEV_FMC] = 0x14000000, 47 [ASPEED_DEV_SPI0] = 0x14010000, 48 [ASPEED_DEV_SPI1] = 0x14020000, 49 [ASPEED_DEV_SPI2] = 0x14030000, 50 [ASPEED_DEV_SDRAM] = 0x400000000, 51 [ASPEED_DEV_MII1] = 0x14040000, 52 [ASPEED_DEV_MII2] = 0x14040008, 53 [ASPEED_DEV_MII3] = 0x14040010, 54 [ASPEED_DEV_ETH1] = 0x14050000, 55 [ASPEED_DEV_ETH2] = 0x14060000, 56 [ASPEED_DEV_ETH3] = 0x14070000, 57 [ASPEED_DEV_EMMC] = 0x12090000, 58 [ASPEED_DEV_INTC] = 0x12100000, 59 [ASPEED_DEV_SLI] = 0x12C17000, 60 [ASPEED_DEV_SLIIO] = 0x14C1E000, 61 [ASPEED_GIC_DIST] = 0x12200000, 62 [ASPEED_GIC_REDIST] = 0x12280000, 63 [ASPEED_DEV_ADC] = 0x14C00000, 64 }; 65 66 #define AST2700_MAX_IRQ 288 67 68 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 69 static const int aspeed_soc_ast2700_irqmap[] = { 70 [ASPEED_DEV_UART0] = 132, 71 [ASPEED_DEV_UART1] = 132, 72 [ASPEED_DEV_UART2] = 132, 73 [ASPEED_DEV_UART3] = 132, 74 [ASPEED_DEV_UART4] = 8, 75 [ASPEED_DEV_UART5] = 132, 76 [ASPEED_DEV_UART6] = 132, 77 [ASPEED_DEV_UART7] = 132, 78 [ASPEED_DEV_UART8] = 132, 79 [ASPEED_DEV_UART9] = 132, 80 [ASPEED_DEV_UART10] = 132, 81 [ASPEED_DEV_UART11] = 132, 82 [ASPEED_DEV_UART12] = 132, 83 [ASPEED_DEV_FMC] = 131, 84 [ASPEED_DEV_SDMC] = 0, 85 [ASPEED_DEV_SCU] = 12, 86 [ASPEED_DEV_ADC] = 130, 87 [ASPEED_DEV_XDMA] = 5, 88 [ASPEED_DEV_EMMC] = 15, 89 [ASPEED_DEV_GPIO] = 11, 90 [ASPEED_DEV_GPIO_1_8V] = 130, 91 [ASPEED_DEV_RTC] = 13, 92 [ASPEED_DEV_TIMER1] = 16, 93 [ASPEED_DEV_TIMER2] = 17, 94 [ASPEED_DEV_TIMER3] = 18, 95 [ASPEED_DEV_TIMER4] = 19, 96 [ASPEED_DEV_TIMER5] = 20, 97 [ASPEED_DEV_TIMER6] = 21, 98 [ASPEED_DEV_TIMER7] = 22, 99 [ASPEED_DEV_TIMER8] = 23, 100 [ASPEED_DEV_WDT] = 131, 101 [ASPEED_DEV_PWM] = 131, 102 [ASPEED_DEV_LPC] = 128, 103 [ASPEED_DEV_IBT] = 128, 104 [ASPEED_DEV_I2C] = 130, 105 [ASPEED_DEV_PECI] = 133, 106 [ASPEED_DEV_ETH1] = 132, 107 [ASPEED_DEV_ETH2] = 132, 108 [ASPEED_DEV_ETH3] = 132, 109 [ASPEED_DEV_HACE] = 4, 110 [ASPEED_DEV_KCS] = 128, 111 [ASPEED_DEV_DP] = 28, 112 [ASPEED_DEV_I3C] = 131, 113 }; 114 115 /* GICINT 128 */ 116 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 117 [ASPEED_DEV_LPC] = 0, 118 [ASPEED_DEV_IBT] = 2, 119 [ASPEED_DEV_KCS] = 4, 120 }; 121 122 /* GICINT 130 */ 123 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 124 [ASPEED_DEV_I2C] = 0, 125 [ASPEED_DEV_ADC] = 16, 126 [ASPEED_DEV_GPIO_1_8V] = 18, 127 }; 128 129 /* GICINT 131 */ 130 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 131 [ASPEED_DEV_I3C] = 0, 132 [ASPEED_DEV_WDT] = 16, 133 [ASPEED_DEV_FMC] = 25, 134 [ASPEED_DEV_PWM] = 29, 135 }; 136 137 /* GICINT 132 */ 138 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 139 [ASPEED_DEV_ETH1] = 0, 140 [ASPEED_DEV_ETH2] = 1, 141 [ASPEED_DEV_ETH3] = 2, 142 [ASPEED_DEV_UART0] = 7, 143 [ASPEED_DEV_UART1] = 8, 144 [ASPEED_DEV_UART2] = 9, 145 [ASPEED_DEV_UART3] = 10, 146 [ASPEED_DEV_UART5] = 11, 147 [ASPEED_DEV_UART6] = 12, 148 [ASPEED_DEV_UART7] = 13, 149 [ASPEED_DEV_UART8] = 14, 150 [ASPEED_DEV_UART9] = 15, 151 [ASPEED_DEV_UART10] = 16, 152 [ASPEED_DEV_UART11] = 17, 153 [ASPEED_DEV_UART12] = 18, 154 }; 155 156 /* GICINT 133 */ 157 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 158 [ASPEED_DEV_PECI] = 4, 159 }; 160 161 /* GICINT 128 ~ 136 */ 162 struct gic_intc_irq_info { 163 int irq; 164 const int *ptr; 165 }; 166 167 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 168 {128, aspeed_soc_ast2700_gic128_intcmap}, 169 {129, NULL}, 170 {130, aspeed_soc_ast2700_gic130_intcmap}, 171 {131, aspeed_soc_ast2700_gic131_intcmap}, 172 {132, aspeed_soc_ast2700_gic132_intcmap}, 173 {133, aspeed_soc_ast2700_gic133_intcmap}, 174 {134, NULL}, 175 {135, NULL}, 176 {136, NULL}, 177 }; 178 179 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 180 { 181 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 182 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 183 int i; 184 185 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 186 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 187 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 188 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 189 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 190 } 191 } 192 193 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 194 } 195 196 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 197 unsigned int size) 198 { 199 qemu_log_mask(LOG_GUEST_ERROR, 200 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 201 __func__, addr); 202 return 0; 203 } 204 205 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 206 unsigned int size) 207 { 208 AspeedSoCState *s = ASPEED_SOC(opaque); 209 ram_addr_t ram_size; 210 MemTxResult result; 211 212 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 213 &error_abort); 214 215 assert(ram_size > 0); 216 217 /* 218 * Emulate ddr capacity hardware behavior. 219 * If writes the data to the address which is beyond the ram size, 220 * it would write the data to the "address % ram_size". 221 */ 222 result = address_space_write(&s->dram_as, addr % ram_size, 223 MEMTXATTRS_UNSPECIFIED, &data, 4); 224 if (result != MEMTX_OK) { 225 qemu_log_mask(LOG_GUEST_ERROR, 226 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 227 ", data :0x%" PRIx64 "\n", 228 __func__, addr % ram_size, data); 229 } 230 } 231 232 static const MemoryRegionOps aspeed_ram_capacity_ops = { 233 .read = aspeed_ram_capacity_read, 234 .write = aspeed_ram_capacity_write, 235 .endianness = DEVICE_LITTLE_ENDIAN, 236 .valid = { 237 .min_access_size = 1, 238 .max_access_size = 8, 239 }, 240 }; 241 242 /* 243 * SDMC should be realized first to get correct RAM size and max size 244 * values 245 */ 246 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 247 { 248 ram_addr_t ram_size, max_ram_size; 249 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 250 AspeedSoCState *s = ASPEED_SOC(dev); 251 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 252 253 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 254 &error_abort); 255 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 256 &error_abort); 257 258 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 259 ram_size); 260 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 261 address_space_init(&s->dram_as, s->dram_mr, "dram"); 262 263 /* 264 * Add a memory region beyond the RAM region to emulate 265 * ddr capacity hardware behavior. 266 */ 267 if (ram_size < max_ram_size) { 268 memory_region_init_io(&a->dram_empty, OBJECT(s), 269 &aspeed_ram_capacity_ops, s, 270 "ram-empty", max_ram_size - ram_size); 271 272 memory_region_add_subregion(s->memory, 273 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 274 &a->dram_empty); 275 } 276 277 memory_region_add_subregion(s->memory, 278 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 279 return true; 280 } 281 282 static void aspeed_soc_ast2700_init(Object *obj) 283 { 284 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 285 AspeedSoCState *s = ASPEED_SOC(obj); 286 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 287 int i; 288 char socname[8]; 289 char typename[64]; 290 291 if (sscanf(sc->name, "%7s", socname) != 1) { 292 g_assert_not_reached(); 293 } 294 295 for (i = 0; i < sc->num_cpus; i++) { 296 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 297 aspeed_soc_cpu_type(sc)); 298 } 299 300 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 301 302 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 303 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 304 sc->silicon_rev); 305 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 306 "hw-strap1"); 307 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 308 "hw-strap2"); 309 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 310 "hw-prot-key"); 311 312 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 313 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 314 sc->silicon_rev); 315 316 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 317 object_initialize_child(obj, "fmc", &s->fmc, typename); 318 319 for (i = 0; i < sc->spis_num; i++) { 320 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 321 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 322 } 323 324 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 325 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 326 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 327 "ram-size"); 328 329 for (i = 0; i < sc->wdts_num; i++) { 330 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 331 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 332 } 333 334 for (i = 0; i < sc->macs_num; i++) { 335 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 336 TYPE_FTGMAC100); 337 338 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 339 } 340 341 for (i = 0; i < sc->uarts_num; i++) { 342 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 343 } 344 345 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 346 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 347 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 348 349 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 350 object_initialize_child(obj, "adc", &s->adc, typename); 351 } 352 353 /* 354 * ASPEED ast2700 has 0x0 as cluster ID 355 * 356 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 357 */ 358 static uint64_t aspeed_calc_affinity(int cpu) 359 { 360 return (0x0 << ARM_AFF1_SHIFT) | cpu; 361 } 362 363 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 364 { 365 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 366 AspeedSoCState *s = ASPEED_SOC(dev); 367 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 368 SysBusDevice *gicbusdev; 369 DeviceState *gicdev; 370 QList *redist_region_count; 371 int i; 372 373 gicbusdev = SYS_BUS_DEVICE(&a->gic); 374 gicdev = DEVICE(&a->gic); 375 qdev_prop_set_uint32(gicdev, "revision", 3); 376 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 377 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); 378 379 redist_region_count = qlist_new(); 380 qlist_append_int(redist_region_count, sc->num_cpus); 381 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 382 383 if (!sysbus_realize(gicbusdev, errp)) { 384 return false; 385 } 386 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 387 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 388 389 for (i = 0; i < sc->num_cpus; i++) { 390 DeviceState *cpudev = DEVICE(&a->cpu[i]); 391 int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; 392 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 393 394 const int timer_irq[] = { 395 [GTIMER_PHYS] = 14, 396 [GTIMER_VIRT] = 11, 397 [GTIMER_HYP] = 10, 398 [GTIMER_SEC] = 13, 399 }; 400 int j; 401 402 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 403 qdev_connect_gpio_out(cpudev, j, 404 qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); 405 } 406 407 qemu_irq irq = qdev_get_gpio_in(gicdev, 408 ppibase + ARCH_GIC_MAINT_IRQ); 409 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 410 0, irq); 411 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 412 qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); 413 414 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 415 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 416 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 417 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 418 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 419 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 420 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 421 } 422 423 return true; 424 } 425 426 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 427 { 428 int i; 429 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 430 AspeedSoCState *s = ASPEED_SOC(dev); 431 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 432 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 433 g_autofree char *sram_name = NULL; 434 435 /* Default boot region (SPI memory or ROMs) */ 436 memory_region_init(&s->spi_boot_container, OBJECT(s), 437 "aspeed.spi_boot_container", 0x400000000); 438 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 439 &s->spi_boot_container); 440 441 /* CPU */ 442 for (i = 0; i < sc->num_cpus; i++) { 443 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 444 aspeed_calc_affinity(i), &error_abort); 445 446 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 447 &error_abort); 448 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 449 OBJECT(s->memory), &error_abort); 450 451 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 452 return; 453 } 454 } 455 456 /* GIC */ 457 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 458 return; 459 } 460 461 /* INTC */ 462 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 463 return; 464 } 465 466 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 467 sc->memmap[ASPEED_DEV_INTC]); 468 469 /* GICINT orgates -> INTC -> GIC */ 470 for (i = 0; i < ic->num_ints; i++) { 471 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 472 qdev_get_gpio_in(DEVICE(&a->intc), i)); 473 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 474 qdev_get_gpio_in(DEVICE(&a->gic), 475 aspeed_soc_ast2700_gic_intcmap[i].irq)); 476 } 477 478 /* SRAM */ 479 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 480 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 481 errp)) { 482 return; 483 } 484 memory_region_add_subregion(s->memory, 485 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 486 487 /* SCU */ 488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 489 return; 490 } 491 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 492 493 /* SCU1 */ 494 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 495 return; 496 } 497 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 498 sc->memmap[ASPEED_DEV_SCUIO]); 499 500 /* UART */ 501 if (!aspeed_soc_uart_realize(s, errp)) { 502 return; 503 } 504 505 /* FMC, The number of CS is set at the board level */ 506 object_property_set_int(OBJECT(&s->fmc), "dram-base", 507 sc->memmap[ASPEED_DEV_SDRAM], 508 &error_abort); 509 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 510 &error_abort); 511 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 512 return; 513 } 514 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 515 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 516 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 518 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 519 520 /* Set up an alias on the FMC CE0 region (boot default) */ 521 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 522 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 523 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 524 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 525 526 /* SPI */ 527 for (i = 0; i < sc->spis_num; i++) { 528 object_property_set_link(OBJECT(&s->spi[i]), "dram", 529 OBJECT(s->dram_mr), &error_abort); 530 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 531 return; 532 } 533 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 534 sc->memmap[ASPEED_DEV_SPI0 + i]); 535 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 536 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 537 } 538 539 /* 540 * SDMC - SDRAM Memory Controller 541 * The SDMC controller is unlocked at SPL stage. 542 * At present, only supports to emulate booting 543 * start from u-boot stage. Set SDMC controller 544 * unlocked by default. It is a temporarily solution. 545 */ 546 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 547 &error_abort); 548 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 549 return; 550 } 551 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 552 sc->memmap[ASPEED_DEV_SDMC]); 553 554 /* RAM */ 555 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 556 return; 557 } 558 559 /* Net */ 560 for (i = 0; i < sc->macs_num; i++) { 561 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 562 &error_abort); 563 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 564 &error_abort); 565 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 566 return; 567 } 568 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 569 sc->memmap[ASPEED_DEV_ETH1 + i]); 570 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 571 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 572 573 object_property_set_link(OBJECT(&s->mii[i]), "nic", 574 OBJECT(&s->ftgmac100[i]), &error_abort); 575 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 576 return; 577 } 578 579 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 580 sc->memmap[ASPEED_DEV_MII1 + i]); 581 } 582 583 /* Watch dog */ 584 for (i = 0; i < sc->wdts_num; i++) { 585 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 586 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 587 588 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 589 &error_abort); 590 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 591 return; 592 } 593 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 594 } 595 596 /* SLI */ 597 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 598 return; 599 } 600 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 601 602 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 603 return; 604 } 605 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 606 sc->memmap[ASPEED_DEV_SLIIO]); 607 608 /* ADC */ 609 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 610 return; 611 } 612 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 613 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 614 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 615 616 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 617 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 618 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 619 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 620 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 621 } 622 623 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 624 { 625 static const char * const valid_cpu_types[] = { 626 ARM_CPU_TYPE_NAME("cortex-a35"), 627 NULL 628 }; 629 DeviceClass *dc = DEVICE_CLASS(oc); 630 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 631 632 /* Reason: The Aspeed SoC can only be instantiated from a board */ 633 dc->user_creatable = false; 634 dc->realize = aspeed_soc_ast2700_realize; 635 636 sc->name = "ast2700-a0"; 637 sc->valid_cpu_types = valid_cpu_types; 638 sc->silicon_rev = AST2700_A0_SILICON_REV; 639 sc->sram_size = 0x20000; 640 sc->spis_num = 3; 641 sc->wdts_num = 8; 642 sc->macs_num = 1; 643 sc->uarts_num = 13; 644 sc->num_cpus = 4; 645 sc->uarts_base = ASPEED_DEV_UART0; 646 sc->irqmap = aspeed_soc_ast2700_irqmap; 647 sc->memmap = aspeed_soc_ast2700_memmap; 648 sc->get_irq = aspeed_soc_ast2700_get_irq; 649 } 650 651 static const TypeInfo aspeed_soc_ast27x0_types[] = { 652 { 653 .name = TYPE_ASPEED27X0_SOC, 654 .parent = TYPE_ASPEED_SOC, 655 .instance_size = sizeof(Aspeed27x0SoCState), 656 .abstract = true, 657 }, { 658 .name = "ast2700-a0", 659 .parent = TYPE_ASPEED27X0_SOC, 660 .instance_init = aspeed_soc_ast2700_init, 661 .class_init = aspeed_soc_ast2700_class_init, 662 }, 663 }; 664 665 DEFINE_TYPES(aspeed_soc_ast27x0_types) 666