1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "qemu/module.h" 17 #include "qemu/error-report.h" 18 #include "hw/i2c/aspeed_i2c.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/intc/arm_gicv3.h" 22 #include "qapi/qmp/qlist.h" 23 #include "qemu/log.h" 24 25 static const hwaddr aspeed_soc_ast2700_memmap[] = { 26 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 [ASPEED_DEV_SDMC] = 0x12C00000, 29 [ASPEED_DEV_SCU] = 0x12C02000, 30 [ASPEED_DEV_SCUIO] = 0x14C02000, 31 [ASPEED_DEV_UART0] = 0X14C33000, 32 [ASPEED_DEV_UART1] = 0X14C33100, 33 [ASPEED_DEV_UART2] = 0X14C33200, 34 [ASPEED_DEV_UART3] = 0X14C33300, 35 [ASPEED_DEV_UART4] = 0X12C1A000, 36 [ASPEED_DEV_UART5] = 0X14C33400, 37 [ASPEED_DEV_UART6] = 0X14C33500, 38 [ASPEED_DEV_UART7] = 0X14C33600, 39 [ASPEED_DEV_UART8] = 0X14C33700, 40 [ASPEED_DEV_UART9] = 0X14C33800, 41 [ASPEED_DEV_UART10] = 0X14C33900, 42 [ASPEED_DEV_UART11] = 0X14C33A00, 43 [ASPEED_DEV_UART12] = 0X14C33B00, 44 [ASPEED_DEV_WDT] = 0x14C37000, 45 [ASPEED_DEV_VUART] = 0X14C30000, 46 [ASPEED_DEV_FMC] = 0x14000000, 47 [ASPEED_DEV_SPI0] = 0x14010000, 48 [ASPEED_DEV_SPI1] = 0x14020000, 49 [ASPEED_DEV_SPI2] = 0x14030000, 50 [ASPEED_DEV_SDRAM] = 0x400000000, 51 [ASPEED_DEV_MII1] = 0x14040000, 52 [ASPEED_DEV_MII2] = 0x14040008, 53 [ASPEED_DEV_MII3] = 0x14040010, 54 [ASPEED_DEV_ETH1] = 0x14050000, 55 [ASPEED_DEV_ETH2] = 0x14060000, 56 [ASPEED_DEV_ETH3] = 0x14070000, 57 [ASPEED_DEV_EMMC] = 0x12090000, 58 [ASPEED_DEV_INTC] = 0x12100000, 59 [ASPEED_DEV_SLI] = 0x12C17000, 60 [ASPEED_DEV_SLIIO] = 0x14C1E000, 61 [ASPEED_GIC_DIST] = 0x12200000, 62 [ASPEED_GIC_REDIST] = 0x12280000, 63 [ASPEED_DEV_ADC] = 0x14C00000, 64 [ASPEED_DEV_I2C] = 0x14C0F000, 65 [ASPEED_DEV_GPIO] = 0x14C0B000, 66 }; 67 68 #define AST2700_MAX_IRQ 288 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2700_irqmap[] = { 72 [ASPEED_DEV_UART0] = 132, 73 [ASPEED_DEV_UART1] = 132, 74 [ASPEED_DEV_UART2] = 132, 75 [ASPEED_DEV_UART3] = 132, 76 [ASPEED_DEV_UART4] = 8, 77 [ASPEED_DEV_UART5] = 132, 78 [ASPEED_DEV_UART6] = 132, 79 [ASPEED_DEV_UART7] = 132, 80 [ASPEED_DEV_UART8] = 132, 81 [ASPEED_DEV_UART9] = 132, 82 [ASPEED_DEV_UART10] = 132, 83 [ASPEED_DEV_UART11] = 132, 84 [ASPEED_DEV_UART12] = 132, 85 [ASPEED_DEV_FMC] = 131, 86 [ASPEED_DEV_SDMC] = 0, 87 [ASPEED_DEV_SCU] = 12, 88 [ASPEED_DEV_ADC] = 130, 89 [ASPEED_DEV_XDMA] = 5, 90 [ASPEED_DEV_EMMC] = 15, 91 [ASPEED_DEV_GPIO] = 130, 92 [ASPEED_DEV_RTC] = 13, 93 [ASPEED_DEV_TIMER1] = 16, 94 [ASPEED_DEV_TIMER2] = 17, 95 [ASPEED_DEV_TIMER3] = 18, 96 [ASPEED_DEV_TIMER4] = 19, 97 [ASPEED_DEV_TIMER5] = 20, 98 [ASPEED_DEV_TIMER6] = 21, 99 [ASPEED_DEV_TIMER7] = 22, 100 [ASPEED_DEV_TIMER8] = 23, 101 [ASPEED_DEV_WDT] = 131, 102 [ASPEED_DEV_PWM] = 131, 103 [ASPEED_DEV_LPC] = 128, 104 [ASPEED_DEV_IBT] = 128, 105 [ASPEED_DEV_I2C] = 130, 106 [ASPEED_DEV_PECI] = 133, 107 [ASPEED_DEV_ETH1] = 132, 108 [ASPEED_DEV_ETH2] = 132, 109 [ASPEED_DEV_ETH3] = 132, 110 [ASPEED_DEV_HACE] = 4, 111 [ASPEED_DEV_KCS] = 128, 112 [ASPEED_DEV_DP] = 28, 113 [ASPEED_DEV_I3C] = 131, 114 }; 115 116 /* GICINT 128 */ 117 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 118 [ASPEED_DEV_LPC] = 0, 119 [ASPEED_DEV_IBT] = 2, 120 [ASPEED_DEV_KCS] = 4, 121 }; 122 123 /* GICINT 130 */ 124 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 125 [ASPEED_DEV_I2C] = 0, 126 [ASPEED_DEV_ADC] = 16, 127 [ASPEED_DEV_GPIO] = 18, 128 }; 129 130 /* GICINT 131 */ 131 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 132 [ASPEED_DEV_I3C] = 0, 133 [ASPEED_DEV_WDT] = 16, 134 [ASPEED_DEV_FMC] = 25, 135 [ASPEED_DEV_PWM] = 29, 136 }; 137 138 /* GICINT 132 */ 139 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 140 [ASPEED_DEV_ETH1] = 0, 141 [ASPEED_DEV_ETH2] = 1, 142 [ASPEED_DEV_ETH3] = 2, 143 [ASPEED_DEV_UART0] = 7, 144 [ASPEED_DEV_UART1] = 8, 145 [ASPEED_DEV_UART2] = 9, 146 [ASPEED_DEV_UART3] = 10, 147 [ASPEED_DEV_UART5] = 11, 148 [ASPEED_DEV_UART6] = 12, 149 [ASPEED_DEV_UART7] = 13, 150 [ASPEED_DEV_UART8] = 14, 151 [ASPEED_DEV_UART9] = 15, 152 [ASPEED_DEV_UART10] = 16, 153 [ASPEED_DEV_UART11] = 17, 154 [ASPEED_DEV_UART12] = 18, 155 }; 156 157 /* GICINT 133 */ 158 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 159 [ASPEED_DEV_PECI] = 4, 160 }; 161 162 /* GICINT 128 ~ 136 */ 163 struct gic_intc_irq_info { 164 int irq; 165 const int *ptr; 166 }; 167 168 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 169 {128, aspeed_soc_ast2700_gic128_intcmap}, 170 {129, NULL}, 171 {130, aspeed_soc_ast2700_gic130_intcmap}, 172 {131, aspeed_soc_ast2700_gic131_intcmap}, 173 {132, aspeed_soc_ast2700_gic132_intcmap}, 174 {133, aspeed_soc_ast2700_gic133_intcmap}, 175 {134, NULL}, 176 {135, NULL}, 177 {136, NULL}, 178 }; 179 180 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 181 { 182 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 183 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 184 int i; 185 186 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 187 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 188 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 189 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 190 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 191 } 192 } 193 194 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 195 } 196 197 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 198 int index) 199 { 200 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 201 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 202 int i; 203 204 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 205 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 206 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 207 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 208 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); 209 } 210 } 211 212 /* 213 * Invalid orgate index, device irq should be 128 to 136. 214 */ 215 g_assert_not_reached(); 216 } 217 218 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 219 unsigned int size) 220 { 221 qemu_log_mask(LOG_GUEST_ERROR, 222 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 223 __func__, addr); 224 return 0; 225 } 226 227 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 228 unsigned int size) 229 { 230 AspeedSoCState *s = ASPEED_SOC(opaque); 231 ram_addr_t ram_size; 232 MemTxResult result; 233 234 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 235 &error_abort); 236 237 assert(ram_size > 0); 238 239 /* 240 * Emulate ddr capacity hardware behavior. 241 * If writes the data to the address which is beyond the ram size, 242 * it would write the data to the "address % ram_size". 243 */ 244 result = address_space_write(&s->dram_as, addr % ram_size, 245 MEMTXATTRS_UNSPECIFIED, &data, 4); 246 if (result != MEMTX_OK) { 247 qemu_log_mask(LOG_GUEST_ERROR, 248 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 249 ", data :0x%" PRIx64 "\n", 250 __func__, addr % ram_size, data); 251 } 252 } 253 254 static const MemoryRegionOps aspeed_ram_capacity_ops = { 255 .read = aspeed_ram_capacity_read, 256 .write = aspeed_ram_capacity_write, 257 .endianness = DEVICE_LITTLE_ENDIAN, 258 .valid = { 259 .min_access_size = 1, 260 .max_access_size = 8, 261 }, 262 }; 263 264 /* 265 * SDMC should be realized first to get correct RAM size and max size 266 * values 267 */ 268 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 269 { 270 ram_addr_t ram_size, max_ram_size; 271 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 272 AspeedSoCState *s = ASPEED_SOC(dev); 273 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 274 275 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 276 &error_abort); 277 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 278 &error_abort); 279 280 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 281 ram_size); 282 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 283 address_space_init(&s->dram_as, s->dram_mr, "dram"); 284 285 /* 286 * Add a memory region beyond the RAM region to emulate 287 * ddr capacity hardware behavior. 288 */ 289 if (ram_size < max_ram_size) { 290 memory_region_init_io(&a->dram_empty, OBJECT(s), 291 &aspeed_ram_capacity_ops, s, 292 "ram-empty", max_ram_size - ram_size); 293 294 memory_region_add_subregion(s->memory, 295 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 296 &a->dram_empty); 297 } 298 299 memory_region_add_subregion(s->memory, 300 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 301 return true; 302 } 303 304 static void aspeed_soc_ast2700_init(Object *obj) 305 { 306 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 307 AspeedSoCState *s = ASPEED_SOC(obj); 308 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 309 int i; 310 char socname[8]; 311 char typename[64]; 312 313 if (sscanf(sc->name, "%7s", socname) != 1) { 314 g_assert_not_reached(); 315 } 316 317 for (i = 0; i < sc->num_cpus; i++) { 318 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 319 aspeed_soc_cpu_type(sc)); 320 } 321 322 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 323 324 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 325 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 326 sc->silicon_rev); 327 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 328 "hw-strap1"); 329 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 330 "hw-strap2"); 331 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 332 "hw-prot-key"); 333 334 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 335 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 336 sc->silicon_rev); 337 338 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 339 object_initialize_child(obj, "fmc", &s->fmc, typename); 340 341 for (i = 0; i < sc->spis_num; i++) { 342 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 343 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 344 } 345 346 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 347 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 348 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 349 "ram-size"); 350 351 for (i = 0; i < sc->wdts_num; i++) { 352 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 353 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 354 } 355 356 for (i = 0; i < sc->macs_num; i++) { 357 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 358 TYPE_FTGMAC100); 359 360 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 361 } 362 363 for (i = 0; i < sc->uarts_num; i++) { 364 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 365 } 366 367 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 368 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 369 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 370 371 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 372 object_initialize_child(obj, "adc", &s->adc, typename); 373 374 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 375 object_initialize_child(obj, "i2c", &s->i2c, typename); 376 377 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 378 object_initialize_child(obj, "gpio", &s->gpio, typename); 379 } 380 381 /* 382 * ASPEED ast2700 has 0x0 as cluster ID 383 * 384 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 385 */ 386 static uint64_t aspeed_calc_affinity(int cpu) 387 { 388 return (0x0 << ARM_AFF1_SHIFT) | cpu; 389 } 390 391 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 392 { 393 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 394 AspeedSoCState *s = ASPEED_SOC(dev); 395 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 396 SysBusDevice *gicbusdev; 397 DeviceState *gicdev; 398 QList *redist_region_count; 399 int i; 400 401 gicbusdev = SYS_BUS_DEVICE(&a->gic); 402 gicdev = DEVICE(&a->gic); 403 qdev_prop_set_uint32(gicdev, "revision", 3); 404 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 405 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); 406 407 redist_region_count = qlist_new(); 408 qlist_append_int(redist_region_count, sc->num_cpus); 409 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 410 411 if (!sysbus_realize(gicbusdev, errp)) { 412 return false; 413 } 414 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 415 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 416 417 for (i = 0; i < sc->num_cpus; i++) { 418 DeviceState *cpudev = DEVICE(&a->cpu[i]); 419 int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; 420 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 421 422 const int timer_irq[] = { 423 [GTIMER_PHYS] = 14, 424 [GTIMER_VIRT] = 11, 425 [GTIMER_HYP] = 10, 426 [GTIMER_SEC] = 13, 427 }; 428 int j; 429 430 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 431 qdev_connect_gpio_out(cpudev, j, 432 qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); 433 } 434 435 qemu_irq irq = qdev_get_gpio_in(gicdev, 436 ppibase + ARCH_GIC_MAINT_IRQ); 437 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 438 0, irq); 439 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 440 qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); 441 442 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 443 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 444 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 445 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 446 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 447 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 448 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 449 } 450 451 return true; 452 } 453 454 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 455 { 456 int i; 457 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 458 AspeedSoCState *s = ASPEED_SOC(dev); 459 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 460 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 461 g_autofree char *sram_name = NULL; 462 qemu_irq irq; 463 464 /* Default boot region (SPI memory or ROMs) */ 465 memory_region_init(&s->spi_boot_container, OBJECT(s), 466 "aspeed.spi_boot_container", 0x400000000); 467 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 468 &s->spi_boot_container); 469 470 /* CPU */ 471 for (i = 0; i < sc->num_cpus; i++) { 472 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 473 aspeed_calc_affinity(i), &error_abort); 474 475 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 476 &error_abort); 477 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 478 OBJECT(s->memory), &error_abort); 479 480 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 481 return; 482 } 483 } 484 485 /* GIC */ 486 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 487 return; 488 } 489 490 /* INTC */ 491 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 492 return; 493 } 494 495 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 496 sc->memmap[ASPEED_DEV_INTC]); 497 498 /* GICINT orgates -> INTC -> GIC */ 499 for (i = 0; i < ic->num_ints; i++) { 500 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 501 qdev_get_gpio_in(DEVICE(&a->intc), i)); 502 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 503 qdev_get_gpio_in(DEVICE(&a->gic), 504 aspeed_soc_ast2700_gic_intcmap[i].irq)); 505 } 506 507 /* SRAM */ 508 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 509 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 510 errp)) { 511 return; 512 } 513 memory_region_add_subregion(s->memory, 514 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 515 516 /* SCU */ 517 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 518 return; 519 } 520 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 521 522 /* SCU1 */ 523 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 524 return; 525 } 526 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 527 sc->memmap[ASPEED_DEV_SCUIO]); 528 529 /* UART */ 530 if (!aspeed_soc_uart_realize(s, errp)) { 531 return; 532 } 533 534 /* FMC, The number of CS is set at the board level */ 535 object_property_set_int(OBJECT(&s->fmc), "dram-base", 536 sc->memmap[ASPEED_DEV_SDRAM], 537 &error_abort); 538 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 539 &error_abort); 540 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 541 return; 542 } 543 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 545 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 547 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 548 549 /* Set up an alias on the FMC CE0 region (boot default) */ 550 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 551 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 552 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 553 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 554 555 /* SPI */ 556 for (i = 0; i < sc->spis_num; i++) { 557 object_property_set_link(OBJECT(&s->spi[i]), "dram", 558 OBJECT(s->dram_mr), &error_abort); 559 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 560 return; 561 } 562 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 563 sc->memmap[ASPEED_DEV_SPI0 + i]); 564 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 565 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 566 } 567 568 /* 569 * SDMC - SDRAM Memory Controller 570 * The SDMC controller is unlocked at SPL stage. 571 * At present, only supports to emulate booting 572 * start from u-boot stage. Set SDMC controller 573 * unlocked by default. It is a temporarily solution. 574 */ 575 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 576 &error_abort); 577 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 578 return; 579 } 580 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 581 sc->memmap[ASPEED_DEV_SDMC]); 582 583 /* RAM */ 584 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 585 return; 586 } 587 588 /* Net */ 589 for (i = 0; i < sc->macs_num; i++) { 590 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 591 &error_abort); 592 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 593 &error_abort); 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 595 return; 596 } 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 598 sc->memmap[ASPEED_DEV_ETH1 + i]); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 600 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 601 602 object_property_set_link(OBJECT(&s->mii[i]), "nic", 603 OBJECT(&s->ftgmac100[i]), &error_abort); 604 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 605 return; 606 } 607 608 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 609 sc->memmap[ASPEED_DEV_MII1 + i]); 610 } 611 612 /* Watch dog */ 613 for (i = 0; i < sc->wdts_num; i++) { 614 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 615 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 616 617 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 618 &error_abort); 619 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 620 return; 621 } 622 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 623 } 624 625 /* SLI */ 626 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 627 return; 628 } 629 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 630 631 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 632 return; 633 } 634 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 635 sc->memmap[ASPEED_DEV_SLIIO]); 636 637 /* ADC */ 638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 639 return; 640 } 641 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 643 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 644 645 /* I2C */ 646 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 647 &error_abort); 648 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 649 return; 650 } 651 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 652 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 653 /* 654 * The AST2700 I2C controller has one source INTC per bus. 655 * I2C buses interrupt are connected to GICINT130_INTC 656 * from bit 0 to bit 15. 657 * I2C bus 0 is connected to GICINT130_INTC at bit 0. 658 * I2C bus 15 is connected to GICINT130_INTC at bit 15. 659 */ 660 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 661 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 662 } 663 664 /* GPIO */ 665 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 666 return; 667 } 668 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 669 sc->memmap[ASPEED_DEV_GPIO]); 670 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 671 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 672 673 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 674 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 675 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 676 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 677 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 678 } 679 680 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 681 { 682 static const char * const valid_cpu_types[] = { 683 ARM_CPU_TYPE_NAME("cortex-a35"), 684 NULL 685 }; 686 DeviceClass *dc = DEVICE_CLASS(oc); 687 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 688 689 /* Reason: The Aspeed SoC can only be instantiated from a board */ 690 dc->user_creatable = false; 691 dc->realize = aspeed_soc_ast2700_realize; 692 693 sc->name = "ast2700-a0"; 694 sc->valid_cpu_types = valid_cpu_types; 695 sc->silicon_rev = AST2700_A0_SILICON_REV; 696 sc->sram_size = 0x20000; 697 sc->spis_num = 3; 698 sc->wdts_num = 8; 699 sc->macs_num = 1; 700 sc->uarts_num = 13; 701 sc->num_cpus = 4; 702 sc->uarts_base = ASPEED_DEV_UART0; 703 sc->irqmap = aspeed_soc_ast2700_irqmap; 704 sc->memmap = aspeed_soc_ast2700_memmap; 705 sc->get_irq = aspeed_soc_ast2700_get_irq; 706 } 707 708 static const TypeInfo aspeed_soc_ast27x0_types[] = { 709 { 710 .name = TYPE_ASPEED27X0_SOC, 711 .parent = TYPE_ASPEED_SOC, 712 .instance_size = sizeof(Aspeed27x0SoCState), 713 .abstract = true, 714 }, { 715 .name = "ast2700-a0", 716 .parent = TYPE_ASPEED27X0_SOC, 717 .instance_init = aspeed_soc_ast2700_init, 718 .class_init = aspeed_soc_ast2700_class_init, 719 }, 720 }; 721 722 DEFINE_TYPES(aspeed_soc_ast27x0_types) 723