1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 26 static const hwaddr aspeed_soc_ast2700_memmap[] = { 27 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 28 [ASPEED_DEV_SRAM] = 0x10000000, 29 [ASPEED_DEV_SDMC] = 0x12C00000, 30 [ASPEED_DEV_SCU] = 0x12C02000, 31 [ASPEED_DEV_SCUIO] = 0x14C02000, 32 [ASPEED_DEV_UART0] = 0X14C33000, 33 [ASPEED_DEV_UART1] = 0X14C33100, 34 [ASPEED_DEV_UART2] = 0X14C33200, 35 [ASPEED_DEV_UART3] = 0X14C33300, 36 [ASPEED_DEV_UART4] = 0X12C1A000, 37 [ASPEED_DEV_UART5] = 0X14C33400, 38 [ASPEED_DEV_UART6] = 0X14C33500, 39 [ASPEED_DEV_UART7] = 0X14C33600, 40 [ASPEED_DEV_UART8] = 0X14C33700, 41 [ASPEED_DEV_UART9] = 0X14C33800, 42 [ASPEED_DEV_UART10] = 0X14C33900, 43 [ASPEED_DEV_UART11] = 0X14C33A00, 44 [ASPEED_DEV_UART12] = 0X14C33B00, 45 [ASPEED_DEV_WDT] = 0x14C37000, 46 [ASPEED_DEV_VUART] = 0X14C30000, 47 [ASPEED_DEV_FMC] = 0x14000000, 48 [ASPEED_DEV_SPI0] = 0x14010000, 49 [ASPEED_DEV_SPI1] = 0x14020000, 50 [ASPEED_DEV_SPI2] = 0x14030000, 51 [ASPEED_DEV_SDRAM] = 0x400000000, 52 [ASPEED_DEV_MII1] = 0x14040000, 53 [ASPEED_DEV_MII2] = 0x14040008, 54 [ASPEED_DEV_MII3] = 0x14040010, 55 [ASPEED_DEV_ETH1] = 0x14050000, 56 [ASPEED_DEV_ETH2] = 0x14060000, 57 [ASPEED_DEV_ETH3] = 0x14070000, 58 [ASPEED_DEV_EMMC] = 0x12090000, 59 [ASPEED_DEV_INTC] = 0x12100000, 60 [ASPEED_DEV_SLI] = 0x12C17000, 61 [ASPEED_DEV_SLIIO] = 0x14C1E000, 62 [ASPEED_GIC_DIST] = 0x12200000, 63 [ASPEED_GIC_REDIST] = 0x12280000, 64 [ASPEED_DEV_ADC] = 0x14C00000, 65 [ASPEED_DEV_I2C] = 0x14C0F000, 66 [ASPEED_DEV_GPIO] = 0x14C0B000, 67 [ASPEED_DEV_RTC] = 0x12C0F000, 68 [ASPEED_DEV_SDHCI] = 0x14080000, 69 [ASPEED_DEV_TIMER1] = 0x12C10000, 70 [ASPEED_DEV_HACE] = 0x12070000, 71 }; 72 73 #define AST2700_MAX_IRQ 256 74 75 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 76 static const int aspeed_soc_ast2700_irqmap[] = { 77 [ASPEED_DEV_UART0] = 132, 78 [ASPEED_DEV_UART1] = 132, 79 [ASPEED_DEV_UART2] = 132, 80 [ASPEED_DEV_UART3] = 132, 81 [ASPEED_DEV_UART4] = 8, 82 [ASPEED_DEV_UART5] = 132, 83 [ASPEED_DEV_UART6] = 132, 84 [ASPEED_DEV_UART7] = 132, 85 [ASPEED_DEV_UART8] = 132, 86 [ASPEED_DEV_UART9] = 132, 87 [ASPEED_DEV_UART10] = 132, 88 [ASPEED_DEV_UART11] = 132, 89 [ASPEED_DEV_UART12] = 132, 90 [ASPEED_DEV_FMC] = 131, 91 [ASPEED_DEV_SDMC] = 0, 92 [ASPEED_DEV_SCU] = 12, 93 [ASPEED_DEV_ADC] = 130, 94 [ASPEED_DEV_XDMA] = 5, 95 [ASPEED_DEV_EMMC] = 15, 96 [ASPEED_DEV_GPIO] = 130, 97 [ASPEED_DEV_RTC] = 13, 98 [ASPEED_DEV_TIMER1] = 16, 99 [ASPEED_DEV_TIMER2] = 17, 100 [ASPEED_DEV_TIMER3] = 18, 101 [ASPEED_DEV_TIMER4] = 19, 102 [ASPEED_DEV_TIMER5] = 20, 103 [ASPEED_DEV_TIMER6] = 21, 104 [ASPEED_DEV_TIMER7] = 22, 105 [ASPEED_DEV_TIMER8] = 23, 106 [ASPEED_DEV_WDT] = 131, 107 [ASPEED_DEV_PWM] = 131, 108 [ASPEED_DEV_LPC] = 128, 109 [ASPEED_DEV_IBT] = 128, 110 [ASPEED_DEV_I2C] = 130, 111 [ASPEED_DEV_PECI] = 133, 112 [ASPEED_DEV_ETH1] = 132, 113 [ASPEED_DEV_ETH2] = 132, 114 [ASPEED_DEV_ETH3] = 132, 115 [ASPEED_DEV_HACE] = 4, 116 [ASPEED_DEV_KCS] = 128, 117 [ASPEED_DEV_DP] = 28, 118 [ASPEED_DEV_I3C] = 131, 119 [ASPEED_DEV_SDHCI] = 133, 120 }; 121 122 /* GICINT 128 */ 123 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 124 [ASPEED_DEV_LPC] = 0, 125 [ASPEED_DEV_IBT] = 2, 126 [ASPEED_DEV_KCS] = 4, 127 }; 128 129 /* GICINT 130 */ 130 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 131 [ASPEED_DEV_I2C] = 0, 132 [ASPEED_DEV_ADC] = 16, 133 [ASPEED_DEV_GPIO] = 18, 134 }; 135 136 /* GICINT 131 */ 137 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 138 [ASPEED_DEV_I3C] = 0, 139 [ASPEED_DEV_WDT] = 16, 140 [ASPEED_DEV_FMC] = 25, 141 [ASPEED_DEV_PWM] = 29, 142 }; 143 144 /* GICINT 132 */ 145 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 146 [ASPEED_DEV_ETH1] = 0, 147 [ASPEED_DEV_ETH2] = 1, 148 [ASPEED_DEV_ETH3] = 2, 149 [ASPEED_DEV_UART0] = 7, 150 [ASPEED_DEV_UART1] = 8, 151 [ASPEED_DEV_UART2] = 9, 152 [ASPEED_DEV_UART3] = 10, 153 [ASPEED_DEV_UART5] = 11, 154 [ASPEED_DEV_UART6] = 12, 155 [ASPEED_DEV_UART7] = 13, 156 [ASPEED_DEV_UART8] = 14, 157 [ASPEED_DEV_UART9] = 15, 158 [ASPEED_DEV_UART10] = 16, 159 [ASPEED_DEV_UART11] = 17, 160 [ASPEED_DEV_UART12] = 18, 161 }; 162 163 /* GICINT 133 */ 164 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 165 [ASPEED_DEV_SDHCI] = 1, 166 [ASPEED_DEV_PECI] = 4, 167 }; 168 169 /* GICINT 128 ~ 136 */ 170 struct gic_intc_irq_info { 171 int irq; 172 const int *ptr; 173 }; 174 175 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 176 {128, aspeed_soc_ast2700_gic128_intcmap}, 177 {129, NULL}, 178 {130, aspeed_soc_ast2700_gic130_intcmap}, 179 {131, aspeed_soc_ast2700_gic131_intcmap}, 180 {132, aspeed_soc_ast2700_gic132_intcmap}, 181 {133, aspeed_soc_ast2700_gic133_intcmap}, 182 {134, NULL}, 183 {135, NULL}, 184 {136, NULL}, 185 }; 186 187 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 188 { 189 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 190 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 191 int i; 192 193 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 194 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 195 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 196 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 197 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 198 } 199 } 200 201 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 202 } 203 204 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 205 int index) 206 { 207 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 208 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 209 int i; 210 211 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 212 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 213 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 214 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 215 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index); 216 } 217 } 218 219 /* 220 * Invalid orgate index, device irq should be 128 to 136. 221 */ 222 g_assert_not_reached(); 223 } 224 225 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 226 unsigned int size) 227 { 228 qemu_log_mask(LOG_GUEST_ERROR, 229 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 230 __func__, addr); 231 return 0; 232 } 233 234 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 235 unsigned int size) 236 { 237 AspeedSoCState *s = ASPEED_SOC(opaque); 238 ram_addr_t ram_size; 239 MemTxResult result; 240 241 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 242 &error_abort); 243 244 assert(ram_size > 0); 245 246 /* 247 * Emulate ddr capacity hardware behavior. 248 * If writes the data to the address which is beyond the ram size, 249 * it would write the data to the "address % ram_size". 250 */ 251 result = address_space_write(&s->dram_as, addr % ram_size, 252 MEMTXATTRS_UNSPECIFIED, &data, 4); 253 if (result != MEMTX_OK) { 254 qemu_log_mask(LOG_GUEST_ERROR, 255 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 256 ", data :0x%" PRIx64 "\n", 257 __func__, addr % ram_size, data); 258 } 259 } 260 261 static const MemoryRegionOps aspeed_ram_capacity_ops = { 262 .read = aspeed_ram_capacity_read, 263 .write = aspeed_ram_capacity_write, 264 .endianness = DEVICE_LITTLE_ENDIAN, 265 .valid = { 266 .min_access_size = 1, 267 .max_access_size = 8, 268 }, 269 }; 270 271 /* 272 * SDMC should be realized first to get correct RAM size and max size 273 * values 274 */ 275 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 276 { 277 ram_addr_t ram_size, max_ram_size; 278 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 279 AspeedSoCState *s = ASPEED_SOC(dev); 280 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 281 282 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 283 &error_abort); 284 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 285 &error_abort); 286 287 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 288 ram_size); 289 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 290 address_space_init(&s->dram_as, s->dram_mr, "dram"); 291 292 /* 293 * Add a memory region beyond the RAM region to emulate 294 * ddr capacity hardware behavior. 295 */ 296 if (ram_size < max_ram_size) { 297 memory_region_init_io(&a->dram_empty, OBJECT(s), 298 &aspeed_ram_capacity_ops, s, 299 "ram-empty", max_ram_size - ram_size); 300 301 memory_region_add_subregion(s->memory, 302 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 303 &a->dram_empty); 304 } 305 306 memory_region_add_subregion(s->memory, 307 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 308 return true; 309 } 310 311 static void aspeed_soc_ast2700_init(Object *obj) 312 { 313 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 314 AspeedSoCState *s = ASPEED_SOC(obj); 315 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 316 int i; 317 char socname[8]; 318 char typename[64]; 319 320 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 321 g_assert_not_reached(); 322 } 323 324 for (i = 0; i < sc->num_cpus; i++) { 325 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 326 aspeed_soc_cpu_type(sc)); 327 } 328 329 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 330 331 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 332 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 333 sc->silicon_rev); 334 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 335 "hw-strap1"); 336 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 337 "hw-strap2"); 338 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 339 "hw-prot-key"); 340 341 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 342 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 343 sc->silicon_rev); 344 345 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 346 object_initialize_child(obj, "fmc", &s->fmc, typename); 347 348 for (i = 0; i < sc->spis_num; i++) { 349 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 350 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 351 } 352 353 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 354 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 355 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 356 "ram-size"); 357 358 for (i = 0; i < sc->wdts_num; i++) { 359 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 360 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 361 } 362 363 for (i = 0; i < sc->macs_num; i++) { 364 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 365 TYPE_FTGMAC100); 366 367 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 368 } 369 370 for (i = 0; i < sc->uarts_num; i++) { 371 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 372 } 373 374 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 375 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 376 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 377 378 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 379 object_initialize_child(obj, "adc", &s->adc, typename); 380 381 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 382 object_initialize_child(obj, "i2c", &s->i2c, typename); 383 384 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 385 object_initialize_child(obj, "gpio", &s->gpio, typename); 386 387 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 388 389 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 390 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 391 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 392 393 /* Init sd card slot class here so that they're under the correct parent */ 394 object_initialize_child(obj, "sd-controller.sdhci", 395 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 396 397 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 398 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 399 400 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 401 TYPE_SYSBUS_SDHCI); 402 403 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 404 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 405 406 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 407 object_initialize_child(obj, "hace", &s->hace, typename); 408 } 409 410 /* 411 * ASPEED ast2700 has 0x0 as cluster ID 412 * 413 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 414 */ 415 static uint64_t aspeed_calc_affinity(int cpu) 416 { 417 return (0x0 << ARM_AFF1_SHIFT) | cpu; 418 } 419 420 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 421 { 422 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 423 AspeedSoCState *s = ASPEED_SOC(dev); 424 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 425 SysBusDevice *gicbusdev; 426 DeviceState *gicdev; 427 QList *redist_region_count; 428 int i; 429 430 gicbusdev = SYS_BUS_DEVICE(&a->gic); 431 gicdev = DEVICE(&a->gic); 432 qdev_prop_set_uint32(gicdev, "revision", 3); 433 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 434 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 435 436 redist_region_count = qlist_new(); 437 qlist_append_int(redist_region_count, sc->num_cpus); 438 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 439 440 if (!sysbus_realize(gicbusdev, errp)) { 441 return false; 442 } 443 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 444 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 445 446 for (i = 0; i < sc->num_cpus; i++) { 447 DeviceState *cpudev = DEVICE(&a->cpu[i]); 448 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 449 450 const int timer_irq[] = { 451 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 452 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 453 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 454 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 455 }; 456 int j; 457 458 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 459 qdev_connect_gpio_out(cpudev, j, 460 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 461 } 462 463 qemu_irq irq = qdev_get_gpio_in(gicdev, 464 intidbase + ARCH_GIC_MAINT_IRQ); 465 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 466 0, irq); 467 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 468 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 469 470 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 471 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 472 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 473 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 474 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 475 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 476 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 477 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 478 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 479 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 480 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 481 } 482 483 return true; 484 } 485 486 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 487 { 488 int i; 489 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 490 AspeedSoCState *s = ASPEED_SOC(dev); 491 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 492 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 493 g_autofree char *sram_name = NULL; 494 qemu_irq irq; 495 496 /* Default boot region (SPI memory or ROMs) */ 497 memory_region_init(&s->spi_boot_container, OBJECT(s), 498 "aspeed.spi_boot_container", 0x400000000); 499 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 500 &s->spi_boot_container); 501 502 /* CPU */ 503 for (i = 0; i < sc->num_cpus; i++) { 504 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 505 aspeed_calc_affinity(i), &error_abort); 506 507 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 508 &error_abort); 509 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 510 OBJECT(s->memory), &error_abort); 511 512 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 513 return; 514 } 515 } 516 517 /* GIC */ 518 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 519 return; 520 } 521 522 /* INTC */ 523 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 524 return; 525 } 526 527 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 528 sc->memmap[ASPEED_DEV_INTC]); 529 530 /* GICINT orgates -> INTC -> GIC */ 531 for (i = 0; i < ic->num_ints; i++) { 532 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 533 qdev_get_gpio_in(DEVICE(&a->intc), i)); 534 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 535 qdev_get_gpio_in(DEVICE(&a->gic), 536 aspeed_soc_ast2700_gic_intcmap[i].irq)); 537 } 538 539 /* SRAM */ 540 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 541 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 542 errp)) { 543 return; 544 } 545 memory_region_add_subregion(s->memory, 546 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 547 548 /* SCU */ 549 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 550 return; 551 } 552 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 553 554 /* SCU1 */ 555 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 556 return; 557 } 558 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 559 sc->memmap[ASPEED_DEV_SCUIO]); 560 561 /* UART */ 562 if (!aspeed_soc_uart_realize(s, errp)) { 563 return; 564 } 565 566 /* FMC, The number of CS is set at the board level */ 567 object_property_set_int(OBJECT(&s->fmc), "dram-base", 568 sc->memmap[ASPEED_DEV_SDRAM], 569 &error_abort); 570 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 571 &error_abort); 572 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 573 return; 574 } 575 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 576 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 577 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 578 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 579 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 580 581 /* Set up an alias on the FMC CE0 region (boot default) */ 582 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 583 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 584 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 585 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 586 587 /* SPI */ 588 for (i = 0; i < sc->spis_num; i++) { 589 object_property_set_link(OBJECT(&s->spi[i]), "dram", 590 OBJECT(s->dram_mr), &error_abort); 591 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 592 return; 593 } 594 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 595 sc->memmap[ASPEED_DEV_SPI0 + i]); 596 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 597 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 598 } 599 600 /* 601 * SDMC - SDRAM Memory Controller 602 * The SDMC controller is unlocked at SPL stage. 603 * At present, only supports to emulate booting 604 * start from u-boot stage. Set SDMC controller 605 * unlocked by default. It is a temporarily solution. 606 */ 607 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 608 &error_abort); 609 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 610 return; 611 } 612 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 613 sc->memmap[ASPEED_DEV_SDMC]); 614 615 /* RAM */ 616 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 617 return; 618 } 619 620 /* Net */ 621 for (i = 0; i < sc->macs_num; i++) { 622 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 623 &error_abort); 624 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 625 &error_abort); 626 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 627 return; 628 } 629 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 630 sc->memmap[ASPEED_DEV_ETH1 + i]); 631 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 632 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 633 634 object_property_set_link(OBJECT(&s->mii[i]), "nic", 635 OBJECT(&s->ftgmac100[i]), &error_abort); 636 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 637 return; 638 } 639 640 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 641 sc->memmap[ASPEED_DEV_MII1 + i]); 642 } 643 644 /* Watch dog */ 645 for (i = 0; i < sc->wdts_num; i++) { 646 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 647 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 648 649 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 650 &error_abort); 651 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 652 return; 653 } 654 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 655 } 656 657 /* SLI */ 658 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 659 return; 660 } 661 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 662 663 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 664 return; 665 } 666 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 667 sc->memmap[ASPEED_DEV_SLIIO]); 668 669 /* ADC */ 670 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 671 return; 672 } 673 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 674 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 675 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 676 677 /* I2C */ 678 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 679 &error_abort); 680 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 681 return; 682 } 683 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 684 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 685 /* 686 * The AST2700 I2C controller has one source INTC per bus. 687 * I2C buses interrupt are connected to GICINT130_INTC 688 * from bit 0 to bit 15. 689 * I2C bus 0 is connected to GICINT130_INTC at bit 0. 690 * I2C bus 15 is connected to GICINT130_INTC at bit 15. 691 */ 692 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 693 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 694 } 695 696 /* GPIO */ 697 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 698 return; 699 } 700 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 701 sc->memmap[ASPEED_DEV_GPIO]); 702 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 703 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 704 705 /* RTC */ 706 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 707 return; 708 } 709 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 710 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 711 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 712 713 /* SDHCI */ 714 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 715 return; 716 } 717 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 718 sc->memmap[ASPEED_DEV_SDHCI]); 719 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 720 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 721 722 /* eMMC */ 723 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 724 return; 725 } 726 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 727 sc->memmap[ASPEED_DEV_EMMC]); 728 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 729 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 730 731 /* Timer */ 732 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 733 &error_abort); 734 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 735 return; 736 } 737 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 738 sc->memmap[ASPEED_DEV_TIMER1]); 739 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 740 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 741 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 742 } 743 744 /* HACE */ 745 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 746 &error_abort); 747 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 748 return; 749 } 750 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 751 sc->memmap[ASPEED_DEV_HACE]); 752 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 753 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 754 755 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 756 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 757 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 758 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 759 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 760 } 761 762 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 763 { 764 static const char * const valid_cpu_types[] = { 765 ARM_CPU_TYPE_NAME("cortex-a35"), 766 NULL 767 }; 768 DeviceClass *dc = DEVICE_CLASS(oc); 769 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 770 771 /* Reason: The Aspeed SoC can only be instantiated from a board */ 772 dc->user_creatable = false; 773 dc->realize = aspeed_soc_ast2700_realize; 774 775 sc->valid_cpu_types = valid_cpu_types; 776 sc->silicon_rev = AST2700_A0_SILICON_REV; 777 sc->sram_size = 0x20000; 778 sc->spis_num = 3; 779 sc->wdts_num = 8; 780 sc->macs_num = 1; 781 sc->uarts_num = 13; 782 sc->num_cpus = 4; 783 sc->uarts_base = ASPEED_DEV_UART0; 784 sc->irqmap = aspeed_soc_ast2700_irqmap; 785 sc->memmap = aspeed_soc_ast2700_memmap; 786 sc->get_irq = aspeed_soc_ast2700_get_irq; 787 } 788 789 static const TypeInfo aspeed_soc_ast27x0_types[] = { 790 { 791 .name = TYPE_ASPEED27X0_SOC, 792 .parent = TYPE_ASPEED_SOC, 793 .instance_size = sizeof(Aspeed27x0SoCState), 794 .abstract = true, 795 }, { 796 .name = "ast2700-a0", 797 .parent = TYPE_ASPEED27X0_SOC, 798 .instance_init = aspeed_soc_ast2700_init, 799 .class_init = aspeed_soc_ast2700_class_init, 800 }, 801 }; 802 803 DEFINE_TYPES(aspeed_soc_ast27x0_types) 804