1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "qemu/module.h" 17 #include "qemu/error-report.h" 18 #include "hw/i2c/aspeed_i2c.h" 19 #include "net/net.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/intc/arm_gicv3.h" 22 #include "qapi/qmp/qlist.h" 23 #include "qemu/log.h" 24 25 static const hwaddr aspeed_soc_ast2700_memmap[] = { 26 [ASPEED_DEV_SPI_BOOT] = 0x400000000, 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 [ASPEED_DEV_SDMC] = 0x12C00000, 29 [ASPEED_DEV_SCU] = 0x12C02000, 30 [ASPEED_DEV_SCUIO] = 0x14C02000, 31 [ASPEED_DEV_UART0] = 0X14C33000, 32 [ASPEED_DEV_UART1] = 0X14C33100, 33 [ASPEED_DEV_UART2] = 0X14C33200, 34 [ASPEED_DEV_UART3] = 0X14C33300, 35 [ASPEED_DEV_UART4] = 0X12C1A000, 36 [ASPEED_DEV_UART5] = 0X14C33400, 37 [ASPEED_DEV_UART6] = 0X14C33500, 38 [ASPEED_DEV_UART7] = 0X14C33600, 39 [ASPEED_DEV_UART8] = 0X14C33700, 40 [ASPEED_DEV_UART9] = 0X14C33800, 41 [ASPEED_DEV_UART10] = 0X14C33900, 42 [ASPEED_DEV_UART11] = 0X14C33A00, 43 [ASPEED_DEV_UART12] = 0X14C33B00, 44 [ASPEED_DEV_WDT] = 0x14C37000, 45 [ASPEED_DEV_VUART] = 0X14C30000, 46 [ASPEED_DEV_FMC] = 0x14000000, 47 [ASPEED_DEV_SPI0] = 0x14010000, 48 [ASPEED_DEV_SPI1] = 0x14020000, 49 [ASPEED_DEV_SPI2] = 0x14030000, 50 [ASPEED_DEV_SDRAM] = 0x400000000, 51 [ASPEED_DEV_MII1] = 0x14040000, 52 [ASPEED_DEV_MII2] = 0x14040008, 53 [ASPEED_DEV_MII3] = 0x14040010, 54 [ASPEED_DEV_ETH1] = 0x14050000, 55 [ASPEED_DEV_ETH2] = 0x14060000, 56 [ASPEED_DEV_ETH3] = 0x14070000, 57 [ASPEED_DEV_EMMC] = 0x12090000, 58 [ASPEED_DEV_INTC] = 0x12100000, 59 [ASPEED_DEV_SLI] = 0x12C17000, 60 [ASPEED_DEV_SLIIO] = 0x14C1E000, 61 [ASPEED_GIC_DIST] = 0x12200000, 62 [ASPEED_GIC_REDIST] = 0x12280000, 63 }; 64 65 #define AST2700_MAX_IRQ 288 66 67 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 68 static const int aspeed_soc_ast2700_irqmap[] = { 69 [ASPEED_DEV_UART0] = 132, 70 [ASPEED_DEV_UART1] = 132, 71 [ASPEED_DEV_UART2] = 132, 72 [ASPEED_DEV_UART3] = 132, 73 [ASPEED_DEV_UART4] = 8, 74 [ASPEED_DEV_UART5] = 132, 75 [ASPEED_DEV_UART6] = 132, 76 [ASPEED_DEV_UART7] = 132, 77 [ASPEED_DEV_UART8] = 132, 78 [ASPEED_DEV_UART9] = 132, 79 [ASPEED_DEV_UART10] = 132, 80 [ASPEED_DEV_UART11] = 132, 81 [ASPEED_DEV_UART12] = 132, 82 [ASPEED_DEV_FMC] = 131, 83 [ASPEED_DEV_SDMC] = 0, 84 [ASPEED_DEV_SCU] = 12, 85 [ASPEED_DEV_ADC] = 130, 86 [ASPEED_DEV_XDMA] = 5, 87 [ASPEED_DEV_EMMC] = 15, 88 [ASPEED_DEV_GPIO] = 11, 89 [ASPEED_DEV_GPIO_1_8V] = 130, 90 [ASPEED_DEV_RTC] = 13, 91 [ASPEED_DEV_TIMER1] = 16, 92 [ASPEED_DEV_TIMER2] = 17, 93 [ASPEED_DEV_TIMER3] = 18, 94 [ASPEED_DEV_TIMER4] = 19, 95 [ASPEED_DEV_TIMER5] = 20, 96 [ASPEED_DEV_TIMER6] = 21, 97 [ASPEED_DEV_TIMER7] = 22, 98 [ASPEED_DEV_TIMER8] = 23, 99 [ASPEED_DEV_WDT] = 131, 100 [ASPEED_DEV_PWM] = 131, 101 [ASPEED_DEV_LPC] = 128, 102 [ASPEED_DEV_IBT] = 128, 103 [ASPEED_DEV_I2C] = 130, 104 [ASPEED_DEV_PECI] = 133, 105 [ASPEED_DEV_ETH1] = 132, 106 [ASPEED_DEV_ETH2] = 132, 107 [ASPEED_DEV_ETH3] = 132, 108 [ASPEED_DEV_HACE] = 4, 109 [ASPEED_DEV_KCS] = 128, 110 [ASPEED_DEV_DP] = 28, 111 [ASPEED_DEV_I3C] = 131, 112 }; 113 114 /* GICINT 128 */ 115 static const int aspeed_soc_ast2700_gic128_intcmap[] = { 116 [ASPEED_DEV_LPC] = 0, 117 [ASPEED_DEV_IBT] = 2, 118 [ASPEED_DEV_KCS] = 4, 119 }; 120 121 /* GICINT 130 */ 122 static const int aspeed_soc_ast2700_gic130_intcmap[] = { 123 [ASPEED_DEV_I2C] = 0, 124 [ASPEED_DEV_ADC] = 16, 125 [ASPEED_DEV_GPIO_1_8V] = 18, 126 }; 127 128 /* GICINT 131 */ 129 static const int aspeed_soc_ast2700_gic131_intcmap[] = { 130 [ASPEED_DEV_I3C] = 0, 131 [ASPEED_DEV_WDT] = 16, 132 [ASPEED_DEV_FMC] = 25, 133 [ASPEED_DEV_PWM] = 29, 134 }; 135 136 /* GICINT 132 */ 137 static const int aspeed_soc_ast2700_gic132_intcmap[] = { 138 [ASPEED_DEV_ETH1] = 0, 139 [ASPEED_DEV_ETH2] = 1, 140 [ASPEED_DEV_ETH3] = 2, 141 [ASPEED_DEV_UART0] = 7, 142 [ASPEED_DEV_UART1] = 8, 143 [ASPEED_DEV_UART2] = 9, 144 [ASPEED_DEV_UART3] = 10, 145 [ASPEED_DEV_UART5] = 11, 146 [ASPEED_DEV_UART6] = 12, 147 [ASPEED_DEV_UART7] = 13, 148 [ASPEED_DEV_UART8] = 14, 149 [ASPEED_DEV_UART9] = 15, 150 [ASPEED_DEV_UART10] = 16, 151 [ASPEED_DEV_UART11] = 17, 152 [ASPEED_DEV_UART12] = 18, 153 }; 154 155 /* GICINT 133 */ 156 static const int aspeed_soc_ast2700_gic133_intcmap[] = { 157 [ASPEED_DEV_PECI] = 4, 158 }; 159 160 /* GICINT 128 ~ 136 */ 161 struct gic_intc_irq_info { 162 int irq; 163 const int *ptr; 164 }; 165 166 static const struct gic_intc_irq_info aspeed_soc_ast2700_gic_intcmap[] = { 167 {128, aspeed_soc_ast2700_gic128_intcmap}, 168 {129, NULL}, 169 {130, aspeed_soc_ast2700_gic130_intcmap}, 170 {131, aspeed_soc_ast2700_gic131_intcmap}, 171 {132, aspeed_soc_ast2700_gic132_intcmap}, 172 {133, aspeed_soc_ast2700_gic133_intcmap}, 173 {134, NULL}, 174 {135, NULL}, 175 {136, NULL}, 176 }; 177 178 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 179 { 180 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 181 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 182 int i; 183 184 for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) { 185 if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) { 186 assert(aspeed_soc_ast2700_gic_intcmap[i].ptr); 187 return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), 188 aspeed_soc_ast2700_gic_intcmap[i].ptr[dev]); 189 } 190 } 191 192 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 193 } 194 195 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 196 unsigned int size) 197 { 198 qemu_log_mask(LOG_GUEST_ERROR, 199 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 200 __func__, addr); 201 return 0; 202 } 203 204 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 205 unsigned int size) 206 { 207 AspeedSoCState *s = ASPEED_SOC(opaque); 208 ram_addr_t ram_size; 209 MemTxResult result; 210 211 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 212 &error_abort); 213 214 assert(ram_size > 0); 215 216 /* 217 * Emulate ddr capacity hardware behavior. 218 * If writes the data to the address which is beyond the ram size, 219 * it would write the data to the "address % ram_size". 220 */ 221 result = address_space_write(&s->dram_as, addr % ram_size, 222 MEMTXATTRS_UNSPECIFIED, &data, 4); 223 if (result != MEMTX_OK) { 224 qemu_log_mask(LOG_GUEST_ERROR, 225 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 226 ", data :0x%" PRIx64 "\n", 227 __func__, addr % ram_size, data); 228 } 229 } 230 231 static const MemoryRegionOps aspeed_ram_capacity_ops = { 232 .read = aspeed_ram_capacity_read, 233 .write = aspeed_ram_capacity_write, 234 .endianness = DEVICE_LITTLE_ENDIAN, 235 .valid = { 236 .min_access_size = 1, 237 .max_access_size = 8, 238 }, 239 }; 240 241 /* 242 * SDMC should be realized first to get correct RAM size and max size 243 * values 244 */ 245 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 246 { 247 ram_addr_t ram_size, max_ram_size; 248 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 249 AspeedSoCState *s = ASPEED_SOC(dev); 250 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 251 252 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 253 &error_abort); 254 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 255 &error_abort); 256 257 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 258 ram_size); 259 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 260 address_space_init(&s->dram_as, s->dram_mr, "dram"); 261 262 /* 263 * Add a memory region beyond the RAM region to emulate 264 * ddr capacity hardware behavior. 265 */ 266 if (ram_size < max_ram_size) { 267 memory_region_init_io(&a->dram_empty, OBJECT(s), 268 &aspeed_ram_capacity_ops, s, 269 "ram-empty", max_ram_size - ram_size); 270 271 memory_region_add_subregion(s->memory, 272 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 273 &a->dram_empty); 274 } 275 276 memory_region_add_subregion(s->memory, 277 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 278 return true; 279 } 280 281 static void aspeed_soc_ast2700_init(Object *obj) 282 { 283 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 284 AspeedSoCState *s = ASPEED_SOC(obj); 285 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 286 int i; 287 char socname[8]; 288 char typename[64]; 289 290 if (sscanf(sc->name, "%7s", socname) != 1) { 291 g_assert_not_reached(); 292 } 293 294 for (i = 0; i < sc->num_cpus; i++) { 295 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 296 aspeed_soc_cpu_type(sc)); 297 } 298 299 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 300 301 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 302 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 303 sc->silicon_rev); 304 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 305 "hw-strap1"); 306 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 307 "hw-strap2"); 308 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 309 "hw-prot-key"); 310 311 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 312 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 313 sc->silicon_rev); 314 315 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 316 object_initialize_child(obj, "fmc", &s->fmc, typename); 317 318 for (i = 0; i < sc->spis_num; i++) { 319 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 320 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 321 } 322 323 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 324 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 325 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 326 "ram-size"); 327 328 for (i = 0; i < sc->wdts_num; i++) { 329 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 330 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 331 } 332 333 for (i = 0; i < sc->macs_num; i++) { 334 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 335 TYPE_FTGMAC100); 336 337 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 338 } 339 340 for (i = 0; i < sc->uarts_num; i++) { 341 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 342 } 343 344 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 345 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 346 object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); 347 } 348 349 /* 350 * ASPEED ast2700 has 0x0 as cluster ID 351 * 352 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 353 */ 354 static uint64_t aspeed_calc_affinity(int cpu) 355 { 356 return (0x0 << ARM_AFF1_SHIFT) | cpu; 357 } 358 359 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 360 { 361 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 362 AspeedSoCState *s = ASPEED_SOC(dev); 363 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 364 SysBusDevice *gicbusdev; 365 DeviceState *gicdev; 366 QList *redist_region_count; 367 int i; 368 369 gicbusdev = SYS_BUS_DEVICE(&a->gic); 370 gicdev = DEVICE(&a->gic); 371 qdev_prop_set_uint32(gicdev, "revision", 3); 372 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 373 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ); 374 375 redist_region_count = qlist_new(); 376 qlist_append_int(redist_region_count, sc->num_cpus); 377 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 378 379 if (!sysbus_realize(gicbusdev, errp)) { 380 return false; 381 } 382 sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]); 383 sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]); 384 385 for (i = 0; i < sc->num_cpus; i++) { 386 DeviceState *cpudev = DEVICE(&a->cpu[i]); 387 int NUM_IRQS = 256, ARCH_GIC_MAINT_IRQ = 9, VIRTUAL_PMU_IRQ = 7; 388 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; 389 390 const int timer_irq[] = { 391 [GTIMER_PHYS] = 14, 392 [GTIMER_VIRT] = 11, 393 [GTIMER_HYP] = 10, 394 [GTIMER_SEC] = 13, 395 }; 396 int j; 397 398 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 399 qdev_connect_gpio_out(cpudev, j, 400 qdev_get_gpio_in(gicdev, ppibase + timer_irq[j])); 401 } 402 403 qemu_irq irq = qdev_get_gpio_in(gicdev, 404 ppibase + ARCH_GIC_MAINT_IRQ); 405 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 406 0, irq); 407 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 408 qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); 409 410 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 411 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 412 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 413 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 414 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 415 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 416 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 417 } 418 419 return true; 420 } 421 422 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 423 { 424 int i; 425 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 426 AspeedSoCState *s = ASPEED_SOC(dev); 427 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 428 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc); 429 g_autofree char *sram_name = NULL; 430 431 /* Default boot region (SPI memory or ROMs) */ 432 memory_region_init(&s->spi_boot_container, OBJECT(s), 433 "aspeed.spi_boot_container", 0x400000000); 434 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 435 &s->spi_boot_container); 436 437 /* CPU */ 438 for (i = 0; i < sc->num_cpus; i++) { 439 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 440 aspeed_calc_affinity(i), &error_abort); 441 442 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 443 &error_abort); 444 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 445 OBJECT(s->memory), &error_abort); 446 447 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 448 return; 449 } 450 } 451 452 /* GIC */ 453 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 454 return; 455 } 456 457 /* INTC */ 458 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { 459 return; 460 } 461 462 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, 463 sc->memmap[ASPEED_DEV_INTC]); 464 465 /* GICINT orgates -> INTC -> GIC */ 466 for (i = 0; i < ic->num_ints; i++) { 467 qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, 468 qdev_get_gpio_in(DEVICE(&a->intc), i)); 469 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, 470 qdev_get_gpio_in(DEVICE(&a->gic), 471 aspeed_soc_ast2700_gic_intcmap[i].irq)); 472 } 473 474 /* SRAM */ 475 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 476 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 477 errp)) { 478 return; 479 } 480 memory_region_add_subregion(s->memory, 481 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 482 483 /* SCU */ 484 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 485 return; 486 } 487 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 488 489 /* SCU1 */ 490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 491 return; 492 } 493 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 494 sc->memmap[ASPEED_DEV_SCUIO]); 495 496 /* UART */ 497 if (!aspeed_soc_uart_realize(s, errp)) { 498 return; 499 } 500 501 /* FMC, The number of CS is set at the board level */ 502 object_property_set_int(OBJECT(&s->fmc), "dram-base", 503 sc->memmap[ASPEED_DEV_SDRAM], 504 &error_abort); 505 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 506 &error_abort); 507 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 508 return; 509 } 510 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 511 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 512 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 514 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 515 516 /* Set up an alias on the FMC CE0 region (boot default) */ 517 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 518 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 519 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 520 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 521 522 /* SPI */ 523 for (i = 0; i < sc->spis_num; i++) { 524 object_property_set_link(OBJECT(&s->spi[i]), "dram", 525 OBJECT(s->dram_mr), &error_abort); 526 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 527 return; 528 } 529 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 530 sc->memmap[ASPEED_DEV_SPI0 + i]); 531 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 532 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 533 } 534 535 /* 536 * SDMC - SDRAM Memory Controller 537 * The SDMC controller is unlocked at SPL stage. 538 * At present, only supports to emulate booting 539 * start from u-boot stage. Set SDMC controller 540 * unlocked by default. It is a temporarily solution. 541 */ 542 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 543 &error_abort); 544 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 545 return; 546 } 547 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 548 sc->memmap[ASPEED_DEV_SDMC]); 549 550 /* RAM */ 551 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 552 return; 553 } 554 555 /* Net */ 556 for (i = 0; i < sc->macs_num; i++) { 557 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 558 &error_abort); 559 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 560 &error_abort); 561 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 562 return; 563 } 564 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 565 sc->memmap[ASPEED_DEV_ETH1 + i]); 566 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 567 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 568 569 object_property_set_link(OBJECT(&s->mii[i]), "nic", 570 OBJECT(&s->ftgmac100[i]), &error_abort); 571 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 572 return; 573 } 574 575 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 576 sc->memmap[ASPEED_DEV_MII1 + i]); 577 } 578 579 /* Watch dog */ 580 for (i = 0; i < sc->wdts_num; i++) { 581 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 582 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 583 584 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 585 &error_abort); 586 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 587 return; 588 } 589 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 590 } 591 592 /* SLI */ 593 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 594 return; 595 } 596 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 597 598 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 599 return; 600 } 601 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 602 sc->memmap[ASPEED_DEV_SLIIO]); 603 604 create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); 605 create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); 606 create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); 607 create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000); 608 create_unimplemented_device("ast2700.io", 0x0, 0x4000000); 609 } 610 611 static void aspeed_soc_ast2700_class_init(ObjectClass *oc, void *data) 612 { 613 static const char * const valid_cpu_types[] = { 614 ARM_CPU_TYPE_NAME("cortex-a35"), 615 NULL 616 }; 617 DeviceClass *dc = DEVICE_CLASS(oc); 618 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 619 620 /* Reason: The Aspeed SoC can only be instantiated from a board */ 621 dc->user_creatable = false; 622 dc->realize = aspeed_soc_ast2700_realize; 623 624 sc->name = "ast2700-a0"; 625 sc->valid_cpu_types = valid_cpu_types; 626 sc->silicon_rev = AST2700_A0_SILICON_REV; 627 sc->sram_size = 0x20000; 628 sc->spis_num = 3; 629 sc->wdts_num = 8; 630 sc->macs_num = 1; 631 sc->uarts_num = 13; 632 sc->num_cpus = 4; 633 sc->uarts_base = ASPEED_DEV_UART0; 634 sc->irqmap = aspeed_soc_ast2700_irqmap; 635 sc->memmap = aspeed_soc_ast2700_memmap; 636 sc->get_irq = aspeed_soc_ast2700_get_irq; 637 } 638 639 static const TypeInfo aspeed_soc_ast27x0_types[] = { 640 { 641 .name = TYPE_ASPEED27X0_SOC, 642 .parent = TYPE_ASPEED_SOC, 643 .instance_size = sizeof(Aspeed27x0SoCState), 644 .abstract = true, 645 }, { 646 .name = "ast2700-a0", 647 .parent = TYPE_ASPEED27X0_SOC, 648 .instance_init = aspeed_soc_ast2700_init, 649 .class_init = aspeed_soc_ast2700_class_init, 650 }, 651 }; 652 653 DEFINE_TYPES(aspeed_soc_ast27x0_types) 654