1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 #include "hw/qdev-clock.h" 26 #include "hw/boards.h" 27 28 #define AST2700_SOC_IO_SIZE 0x00FE0000 29 #define AST2700_SOC_IOMEM_SIZE 0x01000000 30 #define AST2700_SOC_DPMCU_SIZE 0x00040000 31 #define AST2700_SOC_LTPI_SIZE 0x01000000 32 33 static const hwaddr aspeed_soc_ast2700_memmap[] = { 34 [ASPEED_DEV_VBOOTROM] = 0x00000000, 35 [ASPEED_DEV_IOMEM] = 0x00020000, 36 [ASPEED_DEV_SRAM] = 0x10000000, 37 [ASPEED_DEV_DPMCU] = 0x11000000, 38 [ASPEED_DEV_IOMEM0] = 0x12000000, 39 [ASPEED_DEV_EHCI1] = 0x12061000, 40 [ASPEED_DEV_EHCI2] = 0x12063000, 41 [ASPEED_DEV_HACE] = 0x12070000, 42 [ASPEED_DEV_EMMC] = 0x12090000, 43 [ASPEED_DEV_INTC] = 0x12100000, 44 [ASPEED_GIC_DIST] = 0x12200000, 45 [ASPEED_GIC_REDIST] = 0x12280000, 46 [ASPEED_DEV_SDMC] = 0x12C00000, 47 [ASPEED_DEV_SCU] = 0x12C02000, 48 [ASPEED_DEV_RTC] = 0x12C0F000, 49 [ASPEED_DEV_TIMER1] = 0x12C10000, 50 [ASPEED_DEV_SLI] = 0x12C17000, 51 [ASPEED_DEV_UART4] = 0x12C1A000, 52 [ASPEED_DEV_IOMEM1] = 0x14000000, 53 [ASPEED_DEV_FMC] = 0x14000000, 54 [ASPEED_DEV_SPI0] = 0x14010000, 55 [ASPEED_DEV_SPI1] = 0x14020000, 56 [ASPEED_DEV_SPI2] = 0x14030000, 57 [ASPEED_DEV_MII1] = 0x14040000, 58 [ASPEED_DEV_MII2] = 0x14040008, 59 [ASPEED_DEV_MII3] = 0x14040010, 60 [ASPEED_DEV_ETH1] = 0x14050000, 61 [ASPEED_DEV_ETH2] = 0x14060000, 62 [ASPEED_DEV_ETH3] = 0x14070000, 63 [ASPEED_DEV_SDHCI] = 0x14080000, 64 [ASPEED_DEV_EHCI3] = 0x14121000, 65 [ASPEED_DEV_EHCI4] = 0x14123000, 66 [ASPEED_DEV_ADC] = 0x14C00000, 67 [ASPEED_DEV_SCUIO] = 0x14C02000, 68 [ASPEED_DEV_GPIO] = 0x14C0B000, 69 [ASPEED_DEV_I2C] = 0x14C0F000, 70 [ASPEED_DEV_INTCIO] = 0x14C18000, 71 [ASPEED_DEV_SLIIO] = 0x14C1E000, 72 [ASPEED_DEV_VUART] = 0x14C30000, 73 [ASPEED_DEV_UART0] = 0x14C33000, 74 [ASPEED_DEV_UART1] = 0x14C33100, 75 [ASPEED_DEV_UART2] = 0x14C33200, 76 [ASPEED_DEV_UART3] = 0x14C33300, 77 [ASPEED_DEV_UART5] = 0x14C33400, 78 [ASPEED_DEV_UART6] = 0x14C33500, 79 [ASPEED_DEV_UART7] = 0x14C33600, 80 [ASPEED_DEV_UART8] = 0x14C33700, 81 [ASPEED_DEV_UART9] = 0x14C33800, 82 [ASPEED_DEV_UART10] = 0x14C33900, 83 [ASPEED_DEV_UART11] = 0x14C33A00, 84 [ASPEED_DEV_UART12] = 0x14C33B00, 85 [ASPEED_DEV_WDT] = 0x14C37000, 86 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 87 [ASPEED_DEV_LTPI] = 0x300000000, 88 [ASPEED_DEV_SDRAM] = 0x400000000, 89 }; 90 91 #define AST2700_MAX_IRQ 256 92 93 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 94 static const int aspeed_soc_ast2700a0_irqmap[] = { 95 [ASPEED_DEV_SDMC] = 0, 96 [ASPEED_DEV_HACE] = 4, 97 [ASPEED_DEV_XDMA] = 5, 98 [ASPEED_DEV_UART4] = 8, 99 [ASPEED_DEV_SCU] = 12, 100 [ASPEED_DEV_RTC] = 13, 101 [ASPEED_DEV_EMMC] = 15, 102 [ASPEED_DEV_TIMER1] = 16, 103 [ASPEED_DEV_TIMER2] = 17, 104 [ASPEED_DEV_TIMER3] = 18, 105 [ASPEED_DEV_TIMER4] = 19, 106 [ASPEED_DEV_TIMER5] = 20, 107 [ASPEED_DEV_TIMER6] = 21, 108 [ASPEED_DEV_TIMER7] = 22, 109 [ASPEED_DEV_TIMER8] = 23, 110 [ASPEED_DEV_DP] = 28, 111 [ASPEED_DEV_EHCI1] = 33, 112 [ASPEED_DEV_EHCI2] = 37, 113 [ASPEED_DEV_LPC] = 128, 114 [ASPEED_DEV_IBT] = 128, 115 [ASPEED_DEV_KCS] = 128, 116 [ASPEED_DEV_ADC] = 130, 117 [ASPEED_DEV_GPIO] = 130, 118 [ASPEED_DEV_I2C] = 130, 119 [ASPEED_DEV_FMC] = 131, 120 [ASPEED_DEV_WDT] = 131, 121 [ASPEED_DEV_PWM] = 131, 122 [ASPEED_DEV_I3C] = 131, 123 [ASPEED_DEV_UART0] = 132, 124 [ASPEED_DEV_UART1] = 132, 125 [ASPEED_DEV_UART2] = 132, 126 [ASPEED_DEV_UART3] = 132, 127 [ASPEED_DEV_UART5] = 132, 128 [ASPEED_DEV_UART6] = 132, 129 [ASPEED_DEV_UART7] = 132, 130 [ASPEED_DEV_UART8] = 132, 131 [ASPEED_DEV_UART9] = 132, 132 [ASPEED_DEV_UART10] = 132, 133 [ASPEED_DEV_UART11] = 132, 134 [ASPEED_DEV_UART12] = 132, 135 [ASPEED_DEV_ETH1] = 132, 136 [ASPEED_DEV_ETH2] = 132, 137 [ASPEED_DEV_ETH3] = 132, 138 [ASPEED_DEV_PECI] = 133, 139 [ASPEED_DEV_SDHCI] = 133, 140 }; 141 142 static const int aspeed_soc_ast2700a1_irqmap[] = { 143 [ASPEED_DEV_SDMC] = 0, 144 [ASPEED_DEV_HACE] = 4, 145 [ASPEED_DEV_XDMA] = 5, 146 [ASPEED_DEV_UART4] = 8, 147 [ASPEED_DEV_SCU] = 12, 148 [ASPEED_DEV_RTC] = 13, 149 [ASPEED_DEV_EMMC] = 15, 150 [ASPEED_DEV_TIMER1] = 16, 151 [ASPEED_DEV_TIMER2] = 17, 152 [ASPEED_DEV_TIMER3] = 18, 153 [ASPEED_DEV_TIMER4] = 19, 154 [ASPEED_DEV_TIMER5] = 20, 155 [ASPEED_DEV_TIMER6] = 21, 156 [ASPEED_DEV_TIMER7] = 22, 157 [ASPEED_DEV_TIMER8] = 23, 158 [ASPEED_DEV_DP] = 28, 159 [ASPEED_DEV_EHCI1] = 33, 160 [ASPEED_DEV_EHCI2] = 37, 161 [ASPEED_DEV_LPC] = 192, 162 [ASPEED_DEV_IBT] = 192, 163 [ASPEED_DEV_KCS] = 192, 164 [ASPEED_DEV_I2C] = 194, 165 [ASPEED_DEV_ADC] = 194, 166 [ASPEED_DEV_GPIO] = 194, 167 [ASPEED_DEV_FMC] = 195, 168 [ASPEED_DEV_WDT] = 195, 169 [ASPEED_DEV_PWM] = 195, 170 [ASPEED_DEV_I3C] = 195, 171 [ASPEED_DEV_UART0] = 196, 172 [ASPEED_DEV_UART1] = 196, 173 [ASPEED_DEV_UART2] = 196, 174 [ASPEED_DEV_UART3] = 196, 175 [ASPEED_DEV_UART5] = 196, 176 [ASPEED_DEV_UART6] = 196, 177 [ASPEED_DEV_UART7] = 196, 178 [ASPEED_DEV_UART8] = 196, 179 [ASPEED_DEV_UART9] = 196, 180 [ASPEED_DEV_UART10] = 196, 181 [ASPEED_DEV_UART11] = 196, 182 [ASPEED_DEV_UART12] = 196, 183 [ASPEED_DEV_ETH1] = 196, 184 [ASPEED_DEV_ETH2] = 196, 185 [ASPEED_DEV_ETH3] = 196, 186 [ASPEED_DEV_PECI] = 197, 187 [ASPEED_DEV_SDHCI] = 197, 188 }; 189 190 /* GICINT 128 */ 191 /* GICINT 192 */ 192 static const int ast2700_gic128_gic192_intcmap[] = { 193 [ASPEED_DEV_LPC] = 0, 194 [ASPEED_DEV_IBT] = 2, 195 [ASPEED_DEV_KCS] = 4, 196 }; 197 198 /* GICINT 129 */ 199 /* GICINT 193 */ 200 201 /* GICINT 130 */ 202 /* GICINT 194 */ 203 static const int ast2700_gic130_gic194_intcmap[] = { 204 [ASPEED_DEV_I2C] = 0, 205 [ASPEED_DEV_ADC] = 16, 206 [ASPEED_DEV_GPIO] = 18, 207 }; 208 209 /* GICINT 131 */ 210 /* GICINT 195 */ 211 static const int ast2700_gic131_gic195_intcmap[] = { 212 [ASPEED_DEV_I3C] = 0, 213 [ASPEED_DEV_WDT] = 16, 214 [ASPEED_DEV_FMC] = 25, 215 [ASPEED_DEV_PWM] = 29, 216 }; 217 218 /* GICINT 132 */ 219 /* GICINT 196 */ 220 static const int ast2700_gic132_gic196_intcmap[] = { 221 [ASPEED_DEV_ETH1] = 0, 222 [ASPEED_DEV_ETH2] = 1, 223 [ASPEED_DEV_ETH3] = 2, 224 [ASPEED_DEV_UART0] = 7, 225 [ASPEED_DEV_UART1] = 8, 226 [ASPEED_DEV_UART2] = 9, 227 [ASPEED_DEV_UART3] = 10, 228 [ASPEED_DEV_UART5] = 11, 229 [ASPEED_DEV_UART6] = 12, 230 [ASPEED_DEV_UART7] = 13, 231 [ASPEED_DEV_UART8] = 14, 232 [ASPEED_DEV_UART9] = 15, 233 [ASPEED_DEV_UART10] = 16, 234 [ASPEED_DEV_UART11] = 17, 235 [ASPEED_DEV_UART12] = 18, 236 [ASPEED_DEV_EHCI3] = 28, 237 [ASPEED_DEV_EHCI4] = 29, 238 }; 239 240 /* GICINT 133 */ 241 /* GICINT 197 */ 242 static const int ast2700_gic133_gic197_intcmap[] = { 243 [ASPEED_DEV_SDHCI] = 1, 244 [ASPEED_DEV_PECI] = 4, 245 }; 246 247 /* GICINT 128 ~ 136 */ 248 /* GICINT 192 ~ 201 */ 249 struct gic_intc_irq_info { 250 int irq; 251 int intc_idx; 252 int orgate_idx; 253 const int *ptr; 254 }; 255 256 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 257 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 258 {193, 1, 1, NULL}, 259 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 260 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 261 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 262 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 263 {198, 1, 6, NULL}, 264 {199, 1, 7, NULL}, 265 {200, 1, 8, NULL}, 266 {201, 1, 9, NULL}, 267 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 268 {129, 0, 2, NULL}, 269 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 270 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 271 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 272 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 273 {134, 0, 7, NULL}, 274 {135, 0, 8, NULL}, 275 {136, 0, 9, NULL}, 276 }; 277 278 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 279 { 280 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 281 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 282 int or_idx; 283 int idx; 284 int i; 285 286 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 287 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 288 assert(ast2700_gic_intcmap[i].ptr); 289 or_idx = ast2700_gic_intcmap[i].orgate_idx; 290 idx = ast2700_gic_intcmap[i].intc_idx; 291 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 292 ast2700_gic_intcmap[i].ptr[dev]); 293 } 294 } 295 296 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 297 } 298 299 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 300 int index) 301 { 302 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 303 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 304 int or_idx; 305 int idx; 306 int i; 307 308 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 309 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 310 assert(ast2700_gic_intcmap[i].ptr); 311 or_idx = ast2700_gic_intcmap[i].orgate_idx; 312 idx = ast2700_gic_intcmap[i].intc_idx; 313 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 314 ast2700_gic_intcmap[i].ptr[dev] + index); 315 } 316 } 317 318 /* 319 * Invalid OR gate index, device IRQ should be between 128 to 136 320 * and 192 to 201. 321 */ 322 g_assert_not_reached(); 323 } 324 325 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 326 unsigned int size) 327 { 328 qemu_log_mask(LOG_GUEST_ERROR, 329 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 330 __func__, addr); 331 return 0; 332 } 333 334 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 335 unsigned int size) 336 { 337 AspeedSoCState *s = ASPEED_SOC(opaque); 338 ram_addr_t ram_size; 339 MemTxResult result; 340 341 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 342 &error_abort); 343 344 assert(ram_size > 0); 345 346 /* 347 * Emulate ddr capacity hardware behavior. 348 * If writes the data to the address which is beyond the ram size, 349 * it would write the data to the "address % ram_size". 350 */ 351 address_space_stl_le(&s->dram_as, addr % ram_size, data, 352 MEMTXATTRS_UNSPECIFIED, &result); 353 354 if (result != MEMTX_OK) { 355 qemu_log_mask(LOG_GUEST_ERROR, 356 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 357 ", data :0x%" PRIx64 "\n", 358 __func__, addr % ram_size, data); 359 } 360 } 361 362 static const MemoryRegionOps aspeed_ram_capacity_ops = { 363 .read = aspeed_ram_capacity_read, 364 .write = aspeed_ram_capacity_write, 365 .endianness = DEVICE_LITTLE_ENDIAN, 366 .impl.min_access_size = 4, 367 .valid = { 368 .min_access_size = 4, 369 .max_access_size = 4, 370 }, 371 }; 372 373 /* 374 * SDMC should be realized first to get correct RAM size and max size 375 * values 376 */ 377 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 378 { 379 ram_addr_t ram_size, max_ram_size; 380 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 381 AspeedSoCState *s = ASPEED_SOC(dev); 382 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 383 384 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 385 &error_abort); 386 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 387 &error_abort); 388 389 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 390 ram_size); 391 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 392 address_space_init(&s->dram_as, s->dram_mr, "dram"); 393 394 /* 395 * Add a memory region beyond the RAM region to emulate 396 * ddr capacity hardware behavior. 397 */ 398 if (ram_size < max_ram_size) { 399 memory_region_init_io(&a->dram_empty, OBJECT(s), 400 &aspeed_ram_capacity_ops, s, 401 "ram-empty", max_ram_size - ram_size); 402 403 memory_region_add_subregion(s->memory, 404 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 405 &a->dram_empty); 406 } 407 408 memory_region_add_subregion(s->memory, 409 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 410 return true; 411 } 412 413 static void aspeed_soc_ast2700_init(Object *obj) 414 { 415 MachineState *ms = MACHINE(qdev_get_machine()); 416 MachineClass *mc = MACHINE_GET_CLASS(ms); 417 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 418 AspeedSoCState *s = ASPEED_SOC(obj); 419 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 420 int i; 421 char socname[8]; 422 char typename[64]; 423 424 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 425 g_assert_not_reached(); 426 } 427 428 for (i = 0; i < sc->num_cpus; i++) { 429 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 430 aspeed_soc_cpu_type(sc)); 431 } 432 433 /* Coprocessors */ 434 if (mc->default_cpus > sc->num_cpus) { 435 object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC); 436 object_initialize_child(obj, "tsp", &a->tsp, TYPE_ASPEED27X0TSP_SOC); 437 } 438 439 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 440 441 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 442 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 443 sc->silicon_rev); 444 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 445 "hw-strap1"); 446 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 447 "hw-prot-key"); 448 449 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 450 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 451 sc->silicon_rev); 452 /* 453 * There is one hw-strap1 register in the SCU (CPU DIE) and another 454 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 455 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 456 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 457 * sets the value in the SCUIO hw-strap1 register. 458 */ 459 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 460 "hw-strap1"); 461 462 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 463 object_initialize_child(obj, "fmc", &s->fmc, typename); 464 465 for (i = 0; i < sc->spis_num; i++) { 466 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 467 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 468 } 469 470 for (i = 0; i < sc->ehcis_num; i++) { 471 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 472 TYPE_PLATFORM_EHCI); 473 } 474 475 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 476 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 477 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 478 "ram-size"); 479 480 for (i = 0; i < sc->wdts_num; i++) { 481 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 482 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 483 } 484 485 for (i = 0; i < sc->macs_num; i++) { 486 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 487 TYPE_FTGMAC100); 488 489 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 490 } 491 492 for (i = 0; i < sc->uarts_num; i++) { 493 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 494 } 495 496 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 497 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 498 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 499 object_initialize_child(obj, "intcio", &a->intc[1], 500 TYPE_ASPEED_2700_INTCIO); 501 502 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 503 object_initialize_child(obj, "adc", &s->adc, typename); 504 505 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 506 object_initialize_child(obj, "i2c", &s->i2c, typename); 507 508 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 509 object_initialize_child(obj, "gpio", &s->gpio, typename); 510 511 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 512 513 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 514 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 515 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 516 517 /* Init sd card slot class here so that they're under the correct parent */ 518 object_initialize_child(obj, "sd-controller.sdhci", 519 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 520 521 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 522 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 523 524 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 525 TYPE_SYSBUS_SDHCI); 526 527 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 528 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 529 530 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 531 object_initialize_child(obj, "hace", &s->hace, typename); 532 object_initialize_child(obj, "dpmcu", &s->dpmcu, 533 TYPE_UNIMPLEMENTED_DEVICE); 534 object_initialize_child(obj, "ltpi", &s->ltpi, 535 TYPE_UNIMPLEMENTED_DEVICE); 536 object_initialize_child(obj, "iomem", &s->iomem, 537 TYPE_UNIMPLEMENTED_DEVICE); 538 object_initialize_child(obj, "iomem0", &s->iomem0, 539 TYPE_UNIMPLEMENTED_DEVICE); 540 object_initialize_child(obj, "iomem1", &s->iomem1, 541 TYPE_UNIMPLEMENTED_DEVICE); 542 } 543 544 /* 545 * ASPEED ast2700 has 0x0 as cluster ID 546 * 547 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 548 */ 549 static uint64_t aspeed_calc_affinity(int cpu) 550 { 551 return (0x0 << ARM_AFF1_SHIFT) | cpu; 552 } 553 554 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 555 { 556 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 557 AspeedSoCState *s = ASPEED_SOC(dev); 558 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 559 SysBusDevice *gicbusdev; 560 DeviceState *gicdev; 561 QList *redist_region_count; 562 int i; 563 564 gicbusdev = SYS_BUS_DEVICE(&a->gic); 565 gicdev = DEVICE(&a->gic); 566 qdev_prop_set_uint32(gicdev, "revision", 3); 567 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 568 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 569 570 redist_region_count = qlist_new(); 571 qlist_append_int(redist_region_count, sc->num_cpus); 572 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 573 574 if (!sysbus_realize(gicbusdev, errp)) { 575 return false; 576 } 577 578 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0, 579 sc->memmap[ASPEED_GIC_DIST]); 580 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1, 581 sc->memmap[ASPEED_GIC_REDIST]); 582 583 for (i = 0; i < sc->num_cpus; i++) { 584 DeviceState *cpudev = DEVICE(&a->cpu[i]); 585 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 586 587 const int timer_irq[] = { 588 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 589 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 590 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 591 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 592 }; 593 int j; 594 595 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 596 qdev_connect_gpio_out(cpudev, j, 597 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 598 } 599 600 qemu_irq irq = qdev_get_gpio_in(gicdev, 601 intidbase + ARCH_GIC_MAINT_IRQ); 602 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 603 0, irq); 604 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 605 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 606 607 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 608 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 609 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 610 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 611 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 612 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 613 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 614 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 615 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 616 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 617 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 618 } 619 620 return true; 621 } 622 623 static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp) 624 { 625 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 626 AspeedSoCState *s = ASPEED_SOC(dev); 627 MemoryRegion *mr; 628 Clock *sysclk; 629 630 sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); 631 clock_set_hz(sysclk, 200000000ULL); 632 qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk); 633 634 memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory", 635 UINT64_MAX); 636 if (!object_property_set_link(OBJECT(&a->ssp), "memory", 637 OBJECT(&a->ssp.memory), &error_abort)) { 638 return false; 639 } 640 641 mr = &s->sram; 642 memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias", 643 mr, 0, memory_region_size(mr)); 644 645 mr = &s->scu.iomem; 646 memory_region_init_alias(&a->ssp.scu_mr_alias, OBJECT(s), "ssp.scu.alias", 647 mr, 0, memory_region_size(mr)); 648 if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { 649 return false; 650 } 651 652 return true; 653 } 654 655 static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp) 656 { 657 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 658 AspeedSoCState *s = ASPEED_SOC(dev); 659 MemoryRegion *mr; 660 Clock *sysclk; 661 662 sysclk = clock_new(OBJECT(s), "TSP_SYSCLK"); 663 clock_set_hz(sysclk, 200000000ULL); 664 qdev_connect_clock_in(DEVICE(&a->tsp), "sysclk", sysclk); 665 666 memory_region_init(&a->tsp.memory, OBJECT(&a->tsp), "tsp-memory", 667 UINT64_MAX); 668 if (!object_property_set_link(OBJECT(&a->tsp), "memory", 669 OBJECT(&a->tsp.memory), &error_abort)) { 670 return false; 671 } 672 673 mr = &s->sram; 674 memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.alias", 675 mr, 0, memory_region_size(mr)); 676 677 mr = &s->scu.iomem; 678 memory_region_init_alias(&a->tsp.scu_mr_alias, OBJECT(s), "tsp.scu.alias", 679 mr, 0, memory_region_size(mr)); 680 if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) { 681 return false; 682 } 683 684 return true; 685 } 686 687 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 688 { 689 int i; 690 MachineState *ms = MACHINE(qdev_get_machine()); 691 MachineClass *mc = MACHINE_GET_CLASS(ms); 692 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 693 AspeedSoCState *s = ASPEED_SOC(dev); 694 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 695 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 696 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 697 g_autofree char *name = NULL; 698 qemu_irq irq; 699 700 /* Default boot region (SPI memory or ROMs) */ 701 memory_region_init(&s->spi_boot_container, OBJECT(s), 702 "aspeed.spi_boot_container", 0x400000000); 703 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 704 &s->spi_boot_container); 705 706 /* CPU */ 707 for (i = 0; i < sc->num_cpus; i++) { 708 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 709 aspeed_calc_affinity(i), &error_abort); 710 711 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 712 &error_abort); 713 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 714 OBJECT(s->memory), &error_abort); 715 716 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 717 return; 718 } 719 } 720 721 /* GIC */ 722 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 723 return; 724 } 725 726 /* INTC */ 727 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 728 return; 729 } 730 731 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 732 sc->memmap[ASPEED_DEV_INTC]); 733 734 /* INTCIO */ 735 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 736 return; 737 } 738 739 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 740 sc->memmap[ASPEED_DEV_INTCIO]); 741 742 /* irq sources -> orgates -> INTC */ 743 for (i = 0; i < ic->num_inpins; i++) { 744 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 745 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 746 } 747 748 /* INTC -> GIC192 - GIC201 */ 749 /* INTC -> GIC128 - GIC136 */ 750 for (i = 0; i < ic->num_outpins; i++) { 751 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 752 qdev_get_gpio_in(DEVICE(&a->gic), 753 ast2700_gic_intcmap[i].irq)); 754 } 755 756 /* irq source -> orgates -> INTCIO */ 757 for (i = 0; i < icio->num_inpins; i++) { 758 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 759 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 760 } 761 762 /* INTCIO -> INTC */ 763 for (i = 0; i < icio->num_outpins; i++) { 764 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 765 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 766 } 767 768 /* SRAM */ 769 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 770 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 771 errp)) { 772 return; 773 } 774 memory_region_add_subregion(s->memory, 775 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 776 777 /* VBOOTROM */ 778 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom", 779 0x20000, errp)) { 780 return; 781 } 782 memory_region_add_subregion(s->memory, 783 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); 784 785 /* SCU */ 786 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 787 return; 788 } 789 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 790 791 /* SCU1 */ 792 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 793 return; 794 } 795 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 796 sc->memmap[ASPEED_DEV_SCUIO]); 797 798 /* 799 * Coprocessors must be realized after the SRAM and SCU regions. 800 * 801 * The SRAM is used as shared memory between the main CPU (PSP) and the 802 * coprocessors. Coprocessors access this shared SRAM region through a 803 * MemoryRegion alias mapped to a different physical address. 804 * 805 * Similarly, the SCU is a single hardware block shared across all 806 * processors. Coprocessors access it via a MemoryRegion alias that maps 807 * to a different address than the one used by the main CPU. 808 * 809 * Therefore, both the SRAM and SCU must be fully initialized before the 810 * coprocessors can create aliases pointing to them. 811 * 812 * To ensure correctness, the device realization order is explicitly 813 * managed: 814 * coprocessors are initialized only after SRAM and SCU are ready. 815 */ 816 if (mc->default_cpus > sc->num_cpus) { 817 if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { 818 return; 819 } 820 if (!aspeed_soc_ast2700_tsp_realize(dev, errp)) { 821 return; 822 } 823 } 824 825 /* UART */ 826 if (!aspeed_soc_uart_realize(s, errp)) { 827 return; 828 } 829 830 /* FMC, The number of CS is set at the board level */ 831 object_property_set_int(OBJECT(&s->fmc), "dram-base", 832 sc->memmap[ASPEED_DEV_SDRAM], 833 &error_abort); 834 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 835 &error_abort); 836 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 837 return; 838 } 839 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 840 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 841 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 842 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 843 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 844 845 /* Set up an alias on the FMC CE0 region (boot default) */ 846 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 847 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 848 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 849 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 850 851 /* SPI */ 852 for (i = 0; i < sc->spis_num; i++) { 853 object_property_set_link(OBJECT(&s->spi[i]), "dram", 854 OBJECT(s->dram_mr), &error_abort); 855 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 856 return; 857 } 858 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 859 sc->memmap[ASPEED_DEV_SPI0 + i]); 860 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 861 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 862 } 863 864 /* EHCI */ 865 for (i = 0; i < sc->ehcis_num; i++) { 866 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 867 return; 868 } 869 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 870 sc->memmap[ASPEED_DEV_EHCI1 + i]); 871 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 872 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 873 } 874 875 /* 876 * SDMC - SDRAM Memory Controller 877 * The SDMC controller is unlocked at SPL stage. 878 * At present, only supports to emulate booting 879 * start from u-boot stage. Set SDMC controller 880 * unlocked by default. It is a temporarily solution. 881 */ 882 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 883 &error_abort); 884 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 885 return; 886 } 887 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 888 sc->memmap[ASPEED_DEV_SDMC]); 889 890 /* RAM */ 891 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 892 return; 893 } 894 895 /* Net */ 896 for (i = 0; i < sc->macs_num; i++) { 897 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 898 &error_abort); 899 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 900 &error_abort); 901 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 902 return; 903 } 904 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 905 sc->memmap[ASPEED_DEV_ETH1 + i]); 906 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 907 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 908 909 object_property_set_link(OBJECT(&s->mii[i]), "nic", 910 OBJECT(&s->ftgmac100[i]), &error_abort); 911 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 912 return; 913 } 914 915 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 916 sc->memmap[ASPEED_DEV_MII1 + i]); 917 } 918 919 /* Watch dog */ 920 for (i = 0; i < sc->wdts_num; i++) { 921 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 922 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 923 924 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 925 &error_abort); 926 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 927 return; 928 } 929 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 930 } 931 932 /* SLI */ 933 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 934 return; 935 } 936 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 937 938 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 939 return; 940 } 941 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 942 sc->memmap[ASPEED_DEV_SLIIO]); 943 944 /* ADC */ 945 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 946 return; 947 } 948 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 949 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 950 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 951 952 /* I2C */ 953 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 954 &error_abort); 955 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 956 return; 957 } 958 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 959 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 960 /* 961 * The AST2700 I2C controller has one source INTC per bus. 962 * 963 * For AST2700 A0: 964 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 965 * 15, and the OR gate output pin is connected to the input pin of 966 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 967 * the GIC. 968 * 969 * For AST2700 A1: 970 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 971 * 15, and the OR gate output pin is connected to the input pin of 972 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 973 * to the INTC (CPU Die) input pin, and its output pin is connected 974 * to the GIC. 975 * 976 * I2C bus 0 is connected to the OR gate at bit 0. 977 * I2C bus 15 is connected to the OR gate at bit 15. 978 */ 979 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 980 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 981 } 982 983 /* GPIO */ 984 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 985 return; 986 } 987 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 988 sc->memmap[ASPEED_DEV_GPIO]); 989 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 990 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 991 992 /* RTC */ 993 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 994 return; 995 } 996 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 997 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 998 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 999 1000 /* SDHCI */ 1001 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 1002 return; 1003 } 1004 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 1005 sc->memmap[ASPEED_DEV_SDHCI]); 1006 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 1007 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 1008 1009 /* eMMC */ 1010 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 1011 return; 1012 } 1013 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 1014 sc->memmap[ASPEED_DEV_EMMC]); 1015 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 1016 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 1017 1018 /* Timer */ 1019 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 1020 &error_abort); 1021 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 1022 return; 1023 } 1024 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 1025 sc->memmap[ASPEED_DEV_TIMER1]); 1026 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 1027 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 1028 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 1029 } 1030 1031 /* HACE */ 1032 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 1033 &error_abort); 1034 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 1035 return; 1036 } 1037 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 1038 sc->memmap[ASPEED_DEV_HACE]); 1039 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 1040 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 1041 1042 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), 1043 "aspeed.dpmcu", 1044 sc->memmap[ASPEED_DEV_DPMCU], 1045 AST2700_SOC_DPMCU_SIZE); 1046 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), 1047 "aspeed.ltpi", 1048 sc->memmap[ASPEED_DEV_LTPI], 1049 AST2700_SOC_LTPI_SIZE); 1050 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), 1051 "aspeed.io", 1052 sc->memmap[ASPEED_DEV_IOMEM], 1053 AST2700_SOC_IO_SIZE); 1054 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0), 1055 "aspeed.iomem0", 1056 sc->memmap[ASPEED_DEV_IOMEM0], 1057 AST2700_SOC_IOMEM_SIZE); 1058 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1), 1059 "aspeed.iomem1", 1060 sc->memmap[ASPEED_DEV_IOMEM1], 1061 AST2700_SOC_IOMEM_SIZE); 1062 } 1063 1064 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 1065 { 1066 static const char * const valid_cpu_types[] = { 1067 ARM_CPU_TYPE_NAME("cortex-a35"), 1068 NULL 1069 }; 1070 DeviceClass *dc = DEVICE_CLASS(oc); 1071 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1072 1073 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1074 dc->user_creatable = false; 1075 dc->realize = aspeed_soc_ast2700_realize; 1076 1077 sc->valid_cpu_types = valid_cpu_types; 1078 sc->silicon_rev = AST2700_A0_SILICON_REV; 1079 sc->sram_size = 0x20000; 1080 sc->spis_num = 3; 1081 sc->ehcis_num = 2; 1082 sc->wdts_num = 8; 1083 sc->macs_num = 1; 1084 sc->uarts_num = 13; 1085 sc->num_cpus = 4; 1086 sc->uarts_base = ASPEED_DEV_UART0; 1087 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 1088 sc->memmap = aspeed_soc_ast2700_memmap; 1089 sc->get_irq = aspeed_soc_ast2700_get_irq; 1090 } 1091 1092 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 1093 { 1094 static const char * const valid_cpu_types[] = { 1095 ARM_CPU_TYPE_NAME("cortex-a35"), 1096 NULL 1097 }; 1098 DeviceClass *dc = DEVICE_CLASS(oc); 1099 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1100 1101 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1102 dc->user_creatable = false; 1103 dc->realize = aspeed_soc_ast2700_realize; 1104 1105 sc->valid_cpu_types = valid_cpu_types; 1106 sc->silicon_rev = AST2700_A1_SILICON_REV; 1107 sc->sram_size = 0x20000; 1108 sc->spis_num = 3; 1109 sc->ehcis_num = 4; 1110 sc->wdts_num = 8; 1111 sc->macs_num = 3; 1112 sc->uarts_num = 13; 1113 sc->num_cpus = 4; 1114 sc->uarts_base = ASPEED_DEV_UART0; 1115 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 1116 sc->memmap = aspeed_soc_ast2700_memmap; 1117 sc->get_irq = aspeed_soc_ast2700_get_irq; 1118 } 1119 1120 static const TypeInfo aspeed_soc_ast27x0_types[] = { 1121 { 1122 .name = TYPE_ASPEED27X0_SOC, 1123 .parent = TYPE_ASPEED_SOC, 1124 .instance_size = sizeof(Aspeed27x0SoCState), 1125 .abstract = true, 1126 }, { 1127 .name = "ast2700-a0", 1128 .parent = TYPE_ASPEED27X0_SOC, 1129 .instance_init = aspeed_soc_ast2700_init, 1130 .class_init = aspeed_soc_ast2700a0_class_init, 1131 }, 1132 { 1133 .name = "ast2700-a1", 1134 .parent = TYPE_ASPEED27X0_SOC, 1135 .instance_init = aspeed_soc_ast2700_init, 1136 .class_init = aspeed_soc_ast2700a1_class_init, 1137 }, 1138 }; 1139 1140 DEFINE_TYPES(aspeed_soc_ast27x0_types) 1141