1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 #include "hw/qdev-clock.h" 26 #include "hw/boards.h" 27 28 #define AST2700_SOC_IO_SIZE 0x00FE0000 29 #define AST2700_SOC_IOMEM_SIZE 0x01000000 30 #define AST2700_SOC_DPMCU_SIZE 0x00040000 31 #define AST2700_SOC_LTPI_SIZE 0x01000000 32 33 static const hwaddr aspeed_soc_ast2700_memmap[] = { 34 [ASPEED_DEV_VBOOTROM] = 0x00000000, 35 [ASPEED_DEV_IOMEM] = 0x00020000, 36 [ASPEED_DEV_SRAM] = 0x10000000, 37 [ASPEED_DEV_DPMCU] = 0x11000000, 38 [ASPEED_DEV_IOMEM0] = 0x12000000, 39 [ASPEED_DEV_EHCI1] = 0x12061000, 40 [ASPEED_DEV_EHCI2] = 0x12063000, 41 [ASPEED_DEV_HACE] = 0x12070000, 42 [ASPEED_DEV_EMMC] = 0x12090000, 43 [ASPEED_DEV_INTC] = 0x12100000, 44 [ASPEED_GIC_DIST] = 0x12200000, 45 [ASPEED_GIC_REDIST] = 0x12280000, 46 [ASPEED_DEV_SDMC] = 0x12C00000, 47 [ASPEED_DEV_SCU] = 0x12C02000, 48 [ASPEED_DEV_RTC] = 0x12C0F000, 49 [ASPEED_DEV_TIMER1] = 0x12C10000, 50 [ASPEED_DEV_SLI] = 0x12C17000, 51 [ASPEED_DEV_UART4] = 0x12C1A000, 52 [ASPEED_DEV_IOMEM1] = 0x14000000, 53 [ASPEED_DEV_FMC] = 0x14000000, 54 [ASPEED_DEV_SPI0] = 0x14010000, 55 [ASPEED_DEV_SPI1] = 0x14020000, 56 [ASPEED_DEV_SPI2] = 0x14030000, 57 [ASPEED_DEV_MII1] = 0x14040000, 58 [ASPEED_DEV_MII2] = 0x14040008, 59 [ASPEED_DEV_MII3] = 0x14040010, 60 [ASPEED_DEV_ETH1] = 0x14050000, 61 [ASPEED_DEV_ETH2] = 0x14060000, 62 [ASPEED_DEV_ETH3] = 0x14070000, 63 [ASPEED_DEV_SDHCI] = 0x14080000, 64 [ASPEED_DEV_EHCI3] = 0x14121000, 65 [ASPEED_DEV_EHCI4] = 0x14123000, 66 [ASPEED_DEV_ADC] = 0x14C00000, 67 [ASPEED_DEV_SCUIO] = 0x14C02000, 68 [ASPEED_DEV_GPIO] = 0x14C0B000, 69 [ASPEED_DEV_I2C] = 0x14C0F000, 70 [ASPEED_DEV_INTCIO] = 0x14C18000, 71 [ASPEED_DEV_SLIIO] = 0x14C1E000, 72 [ASPEED_DEV_VUART] = 0x14C30000, 73 [ASPEED_DEV_UART0] = 0x14C33000, 74 [ASPEED_DEV_UART1] = 0x14C33100, 75 [ASPEED_DEV_UART2] = 0x14C33200, 76 [ASPEED_DEV_UART3] = 0x14C33300, 77 [ASPEED_DEV_UART5] = 0x14C33400, 78 [ASPEED_DEV_UART6] = 0x14C33500, 79 [ASPEED_DEV_UART7] = 0x14C33600, 80 [ASPEED_DEV_UART8] = 0x14C33700, 81 [ASPEED_DEV_UART9] = 0x14C33800, 82 [ASPEED_DEV_UART10] = 0x14C33900, 83 [ASPEED_DEV_UART11] = 0x14C33A00, 84 [ASPEED_DEV_UART12] = 0x14C33B00, 85 [ASPEED_DEV_WDT] = 0x14C37000, 86 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 87 [ASPEED_DEV_LTPI] = 0x300000000, 88 [ASPEED_DEV_SDRAM] = 0x400000000, 89 }; 90 91 #define AST2700_MAX_IRQ 256 92 93 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 94 static const int aspeed_soc_ast2700a0_irqmap[] = { 95 [ASPEED_DEV_SDMC] = 0, 96 [ASPEED_DEV_HACE] = 4, 97 [ASPEED_DEV_XDMA] = 5, 98 [ASPEED_DEV_UART4] = 8, 99 [ASPEED_DEV_SCU] = 12, 100 [ASPEED_DEV_RTC] = 13, 101 [ASPEED_DEV_EMMC] = 15, 102 [ASPEED_DEV_TIMER1] = 16, 103 [ASPEED_DEV_TIMER2] = 17, 104 [ASPEED_DEV_TIMER3] = 18, 105 [ASPEED_DEV_TIMER4] = 19, 106 [ASPEED_DEV_TIMER5] = 20, 107 [ASPEED_DEV_TIMER6] = 21, 108 [ASPEED_DEV_TIMER7] = 22, 109 [ASPEED_DEV_TIMER8] = 23, 110 [ASPEED_DEV_DP] = 28, 111 [ASPEED_DEV_EHCI1] = 33, 112 [ASPEED_DEV_EHCI2] = 37, 113 [ASPEED_DEV_LPC] = 128, 114 [ASPEED_DEV_IBT] = 128, 115 [ASPEED_DEV_KCS] = 128, 116 [ASPEED_DEV_ADC] = 130, 117 [ASPEED_DEV_GPIO] = 130, 118 [ASPEED_DEV_I2C] = 130, 119 [ASPEED_DEV_FMC] = 131, 120 [ASPEED_DEV_WDT] = 131, 121 [ASPEED_DEV_PWM] = 131, 122 [ASPEED_DEV_I3C] = 131, 123 [ASPEED_DEV_UART0] = 132, 124 [ASPEED_DEV_UART1] = 132, 125 [ASPEED_DEV_UART2] = 132, 126 [ASPEED_DEV_UART3] = 132, 127 [ASPEED_DEV_UART5] = 132, 128 [ASPEED_DEV_UART6] = 132, 129 [ASPEED_DEV_UART7] = 132, 130 [ASPEED_DEV_UART8] = 132, 131 [ASPEED_DEV_UART9] = 132, 132 [ASPEED_DEV_UART10] = 132, 133 [ASPEED_DEV_UART11] = 132, 134 [ASPEED_DEV_UART12] = 132, 135 [ASPEED_DEV_ETH1] = 132, 136 [ASPEED_DEV_ETH2] = 132, 137 [ASPEED_DEV_ETH3] = 132, 138 [ASPEED_DEV_PECI] = 133, 139 [ASPEED_DEV_SDHCI] = 133, 140 }; 141 142 static const int aspeed_soc_ast2700a1_irqmap[] = { 143 [ASPEED_DEV_SDMC] = 0, 144 [ASPEED_DEV_HACE] = 4, 145 [ASPEED_DEV_XDMA] = 5, 146 [ASPEED_DEV_UART4] = 8, 147 [ASPEED_DEV_SCU] = 12, 148 [ASPEED_DEV_RTC] = 13, 149 [ASPEED_DEV_EMMC] = 15, 150 [ASPEED_DEV_TIMER1] = 16, 151 [ASPEED_DEV_TIMER2] = 17, 152 [ASPEED_DEV_TIMER3] = 18, 153 [ASPEED_DEV_TIMER4] = 19, 154 [ASPEED_DEV_TIMER5] = 20, 155 [ASPEED_DEV_TIMER6] = 21, 156 [ASPEED_DEV_TIMER7] = 22, 157 [ASPEED_DEV_TIMER8] = 23, 158 [ASPEED_DEV_DP] = 28, 159 [ASPEED_DEV_EHCI1] = 33, 160 [ASPEED_DEV_EHCI2] = 37, 161 [ASPEED_DEV_LPC] = 192, 162 [ASPEED_DEV_IBT] = 192, 163 [ASPEED_DEV_KCS] = 192, 164 [ASPEED_DEV_I2C] = 194, 165 [ASPEED_DEV_ADC] = 194, 166 [ASPEED_DEV_GPIO] = 194, 167 [ASPEED_DEV_FMC] = 195, 168 [ASPEED_DEV_WDT] = 195, 169 [ASPEED_DEV_PWM] = 195, 170 [ASPEED_DEV_I3C] = 195, 171 [ASPEED_DEV_UART0] = 196, 172 [ASPEED_DEV_UART1] = 196, 173 [ASPEED_DEV_UART2] = 196, 174 [ASPEED_DEV_UART3] = 196, 175 [ASPEED_DEV_UART5] = 196, 176 [ASPEED_DEV_UART6] = 196, 177 [ASPEED_DEV_UART7] = 196, 178 [ASPEED_DEV_UART8] = 196, 179 [ASPEED_DEV_UART9] = 196, 180 [ASPEED_DEV_UART10] = 196, 181 [ASPEED_DEV_UART11] = 196, 182 [ASPEED_DEV_UART12] = 196, 183 [ASPEED_DEV_ETH1] = 196, 184 [ASPEED_DEV_ETH2] = 196, 185 [ASPEED_DEV_ETH3] = 196, 186 [ASPEED_DEV_PECI] = 197, 187 [ASPEED_DEV_SDHCI] = 197, 188 }; 189 190 /* GICINT 128 */ 191 /* GICINT 192 */ 192 static const int ast2700_gic128_gic192_intcmap[] = { 193 [ASPEED_DEV_LPC] = 0, 194 [ASPEED_DEV_IBT] = 2, 195 [ASPEED_DEV_KCS] = 4, 196 }; 197 198 /* GICINT 129 */ 199 /* GICINT 193 */ 200 201 /* GICINT 130 */ 202 /* GICINT 194 */ 203 static const int ast2700_gic130_gic194_intcmap[] = { 204 [ASPEED_DEV_I2C] = 0, 205 [ASPEED_DEV_ADC] = 16, 206 [ASPEED_DEV_GPIO] = 18, 207 }; 208 209 /* GICINT 131 */ 210 /* GICINT 195 */ 211 static const int ast2700_gic131_gic195_intcmap[] = { 212 [ASPEED_DEV_I3C] = 0, 213 [ASPEED_DEV_WDT] = 16, 214 [ASPEED_DEV_FMC] = 25, 215 [ASPEED_DEV_PWM] = 29, 216 }; 217 218 /* GICINT 132 */ 219 /* GICINT 196 */ 220 static const int ast2700_gic132_gic196_intcmap[] = { 221 [ASPEED_DEV_ETH1] = 0, 222 [ASPEED_DEV_ETH2] = 1, 223 [ASPEED_DEV_ETH3] = 2, 224 [ASPEED_DEV_UART0] = 7, 225 [ASPEED_DEV_UART1] = 8, 226 [ASPEED_DEV_UART2] = 9, 227 [ASPEED_DEV_UART3] = 10, 228 [ASPEED_DEV_UART5] = 11, 229 [ASPEED_DEV_UART6] = 12, 230 [ASPEED_DEV_UART7] = 13, 231 [ASPEED_DEV_UART8] = 14, 232 [ASPEED_DEV_UART9] = 15, 233 [ASPEED_DEV_UART10] = 16, 234 [ASPEED_DEV_UART11] = 17, 235 [ASPEED_DEV_UART12] = 18, 236 [ASPEED_DEV_EHCI3] = 28, 237 [ASPEED_DEV_EHCI4] = 29, 238 }; 239 240 /* GICINT 133 */ 241 /* GICINT 197 */ 242 static const int ast2700_gic133_gic197_intcmap[] = { 243 [ASPEED_DEV_SDHCI] = 1, 244 [ASPEED_DEV_PECI] = 4, 245 }; 246 247 /* GICINT 128 ~ 136 */ 248 /* GICINT 192 ~ 201 */ 249 struct gic_intc_irq_info { 250 int irq; 251 int intc_idx; 252 int orgate_idx; 253 const int *ptr; 254 }; 255 256 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 257 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 258 {193, 1, 1, NULL}, 259 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 260 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 261 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 262 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 263 {198, 1, 6, NULL}, 264 {199, 1, 7, NULL}, 265 {200, 1, 8, NULL}, 266 {201, 1, 9, NULL}, 267 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 268 {129, 0, 2, NULL}, 269 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 270 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 271 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 272 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 273 {134, 0, 7, NULL}, 274 {135, 0, 8, NULL}, 275 {136, 0, 9, NULL}, 276 }; 277 278 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 279 { 280 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 281 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 282 int or_idx; 283 int idx; 284 int i; 285 286 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 287 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 288 assert(ast2700_gic_intcmap[i].ptr); 289 or_idx = ast2700_gic_intcmap[i].orgate_idx; 290 idx = ast2700_gic_intcmap[i].intc_idx; 291 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 292 ast2700_gic_intcmap[i].ptr[dev]); 293 } 294 } 295 296 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 297 } 298 299 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 300 int index) 301 { 302 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 303 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 304 int or_idx; 305 int idx; 306 int i; 307 308 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 309 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 310 assert(ast2700_gic_intcmap[i].ptr); 311 or_idx = ast2700_gic_intcmap[i].orgate_idx; 312 idx = ast2700_gic_intcmap[i].intc_idx; 313 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 314 ast2700_gic_intcmap[i].ptr[dev] + index); 315 } 316 } 317 318 /* 319 * Invalid OR gate index, device IRQ should be between 128 to 136 320 * and 192 to 201. 321 */ 322 g_assert_not_reached(); 323 } 324 325 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 326 unsigned int size) 327 { 328 qemu_log_mask(LOG_GUEST_ERROR, 329 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 330 __func__, addr); 331 return 0; 332 } 333 334 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 335 unsigned int size) 336 { 337 AspeedSoCState *s = ASPEED_SOC(opaque); 338 ram_addr_t ram_size; 339 MemTxResult result; 340 341 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 342 &error_abort); 343 344 assert(ram_size > 0); 345 346 /* 347 * Emulate ddr capacity hardware behavior. 348 * If writes the data to the address which is beyond the ram size, 349 * it would write the data to the "address % ram_size". 350 */ 351 address_space_stl_le(&s->dram_as, addr % ram_size, data, 352 MEMTXATTRS_UNSPECIFIED, &result); 353 354 if (result != MEMTX_OK) { 355 qemu_log_mask(LOG_GUEST_ERROR, 356 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 357 ", data :0x%" PRIx64 "\n", 358 __func__, addr % ram_size, data); 359 } 360 } 361 362 static const MemoryRegionOps aspeed_ram_capacity_ops = { 363 .read = aspeed_ram_capacity_read, 364 .write = aspeed_ram_capacity_write, 365 .endianness = DEVICE_LITTLE_ENDIAN, 366 .impl.min_access_size = 4, 367 .valid = { 368 .min_access_size = 4, 369 .max_access_size = 4, 370 }, 371 }; 372 373 /* 374 * SDMC should be realized first to get correct RAM size and max size 375 * values 376 */ 377 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 378 { 379 ram_addr_t ram_size, max_ram_size; 380 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 381 AspeedSoCState *s = ASPEED_SOC(dev); 382 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 383 384 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 385 &error_abort); 386 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 387 &error_abort); 388 389 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 390 ram_size); 391 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 392 address_space_init(&s->dram_as, s->dram_mr, "dram"); 393 394 /* 395 * Add a memory region beyond the RAM region to emulate 396 * ddr capacity hardware behavior. 397 */ 398 if (ram_size < max_ram_size) { 399 memory_region_init_io(&a->dram_empty, OBJECT(s), 400 &aspeed_ram_capacity_ops, s, 401 "ram-empty", max_ram_size - ram_size); 402 403 memory_region_add_subregion(s->memory, 404 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 405 &a->dram_empty); 406 } 407 408 memory_region_add_subregion(s->memory, 409 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 410 return true; 411 } 412 413 static void aspeed_soc_ast2700_init(Object *obj) 414 { 415 MachineState *ms = MACHINE(qdev_get_machine()); 416 MachineClass *mc = MACHINE_GET_CLASS(ms); 417 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 418 AspeedSoCState *s = ASPEED_SOC(obj); 419 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 420 int i; 421 char socname[8]; 422 char typename[64]; 423 424 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 425 g_assert_not_reached(); 426 } 427 428 for (i = 0; i < sc->num_cpus; i++) { 429 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 430 aspeed_soc_cpu_type(sc)); 431 } 432 433 /* Coprocessors */ 434 if (mc->default_cpus > sc->num_cpus) { 435 object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC); 436 } 437 438 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 439 440 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 441 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 442 sc->silicon_rev); 443 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 444 "hw-strap1"); 445 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 446 "hw-prot-key"); 447 448 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 449 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 450 sc->silicon_rev); 451 /* 452 * There is one hw-strap1 register in the SCU (CPU DIE) and another 453 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 454 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 455 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 456 * sets the value in the SCUIO hw-strap1 register. 457 */ 458 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 459 "hw-strap1"); 460 461 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 462 object_initialize_child(obj, "fmc", &s->fmc, typename); 463 464 for (i = 0; i < sc->spis_num; i++) { 465 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 466 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 467 } 468 469 for (i = 0; i < sc->ehcis_num; i++) { 470 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 471 TYPE_PLATFORM_EHCI); 472 } 473 474 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 475 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 476 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 477 "ram-size"); 478 479 for (i = 0; i < sc->wdts_num; i++) { 480 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 481 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 482 } 483 484 for (i = 0; i < sc->macs_num; i++) { 485 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 486 TYPE_FTGMAC100); 487 488 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 489 } 490 491 for (i = 0; i < sc->uarts_num; i++) { 492 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 493 } 494 495 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 496 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 497 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 498 object_initialize_child(obj, "intcio", &a->intc[1], 499 TYPE_ASPEED_2700_INTCIO); 500 501 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 502 object_initialize_child(obj, "adc", &s->adc, typename); 503 504 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 505 object_initialize_child(obj, "i2c", &s->i2c, typename); 506 507 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 508 object_initialize_child(obj, "gpio", &s->gpio, typename); 509 510 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 511 512 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 513 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 514 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 515 516 /* Init sd card slot class here so that they're under the correct parent */ 517 object_initialize_child(obj, "sd-controller.sdhci", 518 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 519 520 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 521 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 522 523 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 524 TYPE_SYSBUS_SDHCI); 525 526 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 527 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 528 529 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 530 object_initialize_child(obj, "hace", &s->hace, typename); 531 object_initialize_child(obj, "dpmcu", &s->dpmcu, 532 TYPE_UNIMPLEMENTED_DEVICE); 533 object_initialize_child(obj, "ltpi", &s->ltpi, 534 TYPE_UNIMPLEMENTED_DEVICE); 535 object_initialize_child(obj, "iomem", &s->iomem, 536 TYPE_UNIMPLEMENTED_DEVICE); 537 object_initialize_child(obj, "iomem0", &s->iomem0, 538 TYPE_UNIMPLEMENTED_DEVICE); 539 object_initialize_child(obj, "iomem1", &s->iomem1, 540 TYPE_UNIMPLEMENTED_DEVICE); 541 } 542 543 /* 544 * ASPEED ast2700 has 0x0 as cluster ID 545 * 546 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 547 */ 548 static uint64_t aspeed_calc_affinity(int cpu) 549 { 550 return (0x0 << ARM_AFF1_SHIFT) | cpu; 551 } 552 553 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 554 { 555 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 556 AspeedSoCState *s = ASPEED_SOC(dev); 557 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 558 SysBusDevice *gicbusdev; 559 DeviceState *gicdev; 560 QList *redist_region_count; 561 int i; 562 563 gicbusdev = SYS_BUS_DEVICE(&a->gic); 564 gicdev = DEVICE(&a->gic); 565 qdev_prop_set_uint32(gicdev, "revision", 3); 566 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 567 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 568 569 redist_region_count = qlist_new(); 570 qlist_append_int(redist_region_count, sc->num_cpus); 571 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 572 573 if (!sysbus_realize(gicbusdev, errp)) { 574 return false; 575 } 576 577 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0, 578 sc->memmap[ASPEED_GIC_DIST]); 579 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1, 580 sc->memmap[ASPEED_GIC_REDIST]); 581 582 for (i = 0; i < sc->num_cpus; i++) { 583 DeviceState *cpudev = DEVICE(&a->cpu[i]); 584 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 585 586 const int timer_irq[] = { 587 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 588 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 589 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 590 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 591 }; 592 int j; 593 594 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 595 qdev_connect_gpio_out(cpudev, j, 596 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 597 } 598 599 qemu_irq irq = qdev_get_gpio_in(gicdev, 600 intidbase + ARCH_GIC_MAINT_IRQ); 601 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 602 0, irq); 603 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 604 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 605 606 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 607 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 608 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 609 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 610 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 611 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 612 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 613 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 614 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 615 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 616 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 617 } 618 619 return true; 620 } 621 622 static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp) 623 { 624 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 625 AspeedSoCState *s = ASPEED_SOC(dev); 626 Clock *sysclk; 627 628 sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); 629 clock_set_hz(sysclk, 200000000ULL); 630 qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk); 631 632 memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory", 633 UINT64_MAX); 634 if (!object_property_set_link(OBJECT(&a->ssp), "memory", 635 OBJECT(&a->ssp.memory), &error_abort)) { 636 return false; 637 } 638 639 if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { 640 return false; 641 } 642 643 return true; 644 } 645 646 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 647 { 648 int i; 649 MachineState *ms = MACHINE(qdev_get_machine()); 650 MachineClass *mc = MACHINE_GET_CLASS(ms); 651 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 652 AspeedSoCState *s = ASPEED_SOC(dev); 653 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 654 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 655 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 656 g_autofree char *name = NULL; 657 qemu_irq irq; 658 659 /* Default boot region (SPI memory or ROMs) */ 660 memory_region_init(&s->spi_boot_container, OBJECT(s), 661 "aspeed.spi_boot_container", 0x400000000); 662 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 663 &s->spi_boot_container); 664 665 /* CPU */ 666 for (i = 0; i < sc->num_cpus; i++) { 667 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 668 aspeed_calc_affinity(i), &error_abort); 669 670 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 671 &error_abort); 672 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 673 OBJECT(s->memory), &error_abort); 674 675 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 676 return; 677 } 678 } 679 680 /* GIC */ 681 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 682 return; 683 } 684 685 /* INTC */ 686 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 687 return; 688 } 689 690 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 691 sc->memmap[ASPEED_DEV_INTC]); 692 693 /* INTCIO */ 694 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 695 return; 696 } 697 698 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 699 sc->memmap[ASPEED_DEV_INTCIO]); 700 701 /* irq sources -> orgates -> INTC */ 702 for (i = 0; i < ic->num_inpins; i++) { 703 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 704 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 705 } 706 707 /* INTC -> GIC192 - GIC201 */ 708 /* INTC -> GIC128 - GIC136 */ 709 for (i = 0; i < ic->num_outpins; i++) { 710 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 711 qdev_get_gpio_in(DEVICE(&a->gic), 712 ast2700_gic_intcmap[i].irq)); 713 } 714 715 /* irq source -> orgates -> INTCIO */ 716 for (i = 0; i < icio->num_inpins; i++) { 717 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 718 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 719 } 720 721 /* INTCIO -> INTC */ 722 for (i = 0; i < icio->num_outpins; i++) { 723 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 724 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 725 } 726 727 /* SRAM */ 728 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 729 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 730 errp)) { 731 return; 732 } 733 memory_region_add_subregion(s->memory, 734 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 735 736 /* VBOOTROM */ 737 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom", 738 0x20000, errp)) { 739 return; 740 } 741 memory_region_add_subregion(s->memory, 742 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); 743 744 /* SCU */ 745 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 746 return; 747 } 748 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 749 750 /* SCU1 */ 751 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 752 return; 753 } 754 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 755 sc->memmap[ASPEED_DEV_SCUIO]); 756 757 /* Coprocessors */ 758 if (mc->default_cpus > sc->num_cpus) { 759 if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { 760 return; 761 } 762 } 763 764 /* UART */ 765 if (!aspeed_soc_uart_realize(s, errp)) { 766 return; 767 } 768 769 /* FMC, The number of CS is set at the board level */ 770 object_property_set_int(OBJECT(&s->fmc), "dram-base", 771 sc->memmap[ASPEED_DEV_SDRAM], 772 &error_abort); 773 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 774 &error_abort); 775 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 776 return; 777 } 778 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 779 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 780 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 781 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 782 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 783 784 /* Set up an alias on the FMC CE0 region (boot default) */ 785 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 786 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 787 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 788 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 789 790 /* SPI */ 791 for (i = 0; i < sc->spis_num; i++) { 792 object_property_set_link(OBJECT(&s->spi[i]), "dram", 793 OBJECT(s->dram_mr), &error_abort); 794 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 795 return; 796 } 797 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 798 sc->memmap[ASPEED_DEV_SPI0 + i]); 799 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 800 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 801 } 802 803 /* EHCI */ 804 for (i = 0; i < sc->ehcis_num; i++) { 805 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 806 return; 807 } 808 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 809 sc->memmap[ASPEED_DEV_EHCI1 + i]); 810 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 811 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 812 } 813 814 /* 815 * SDMC - SDRAM Memory Controller 816 * The SDMC controller is unlocked at SPL stage. 817 * At present, only supports to emulate booting 818 * start from u-boot stage. Set SDMC controller 819 * unlocked by default. It is a temporarily solution. 820 */ 821 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 822 &error_abort); 823 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 824 return; 825 } 826 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 827 sc->memmap[ASPEED_DEV_SDMC]); 828 829 /* RAM */ 830 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 831 return; 832 } 833 834 /* Net */ 835 for (i = 0; i < sc->macs_num; i++) { 836 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 837 &error_abort); 838 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 839 &error_abort); 840 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 841 return; 842 } 843 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 844 sc->memmap[ASPEED_DEV_ETH1 + i]); 845 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 846 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 847 848 object_property_set_link(OBJECT(&s->mii[i]), "nic", 849 OBJECT(&s->ftgmac100[i]), &error_abort); 850 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 851 return; 852 } 853 854 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 855 sc->memmap[ASPEED_DEV_MII1 + i]); 856 } 857 858 /* Watch dog */ 859 for (i = 0; i < sc->wdts_num; i++) { 860 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 861 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 862 863 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 864 &error_abort); 865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 866 return; 867 } 868 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 869 } 870 871 /* SLI */ 872 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 873 return; 874 } 875 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 876 877 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 878 return; 879 } 880 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 881 sc->memmap[ASPEED_DEV_SLIIO]); 882 883 /* ADC */ 884 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 885 return; 886 } 887 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 888 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 889 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 890 891 /* I2C */ 892 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 893 &error_abort); 894 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 895 return; 896 } 897 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 898 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 899 /* 900 * The AST2700 I2C controller has one source INTC per bus. 901 * 902 * For AST2700 A0: 903 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 904 * 15, and the OR gate output pin is connected to the input pin of 905 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 906 * the GIC. 907 * 908 * For AST2700 A1: 909 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 910 * 15, and the OR gate output pin is connected to the input pin of 911 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 912 * to the INTC (CPU Die) input pin, and its output pin is connected 913 * to the GIC. 914 * 915 * I2C bus 0 is connected to the OR gate at bit 0. 916 * I2C bus 15 is connected to the OR gate at bit 15. 917 */ 918 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 919 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 920 } 921 922 /* GPIO */ 923 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 924 return; 925 } 926 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 927 sc->memmap[ASPEED_DEV_GPIO]); 928 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 929 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 930 931 /* RTC */ 932 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 933 return; 934 } 935 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 936 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 937 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 938 939 /* SDHCI */ 940 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 941 return; 942 } 943 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 944 sc->memmap[ASPEED_DEV_SDHCI]); 945 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 946 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 947 948 /* eMMC */ 949 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 950 return; 951 } 952 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 953 sc->memmap[ASPEED_DEV_EMMC]); 954 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 955 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 956 957 /* Timer */ 958 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 959 &error_abort); 960 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 961 return; 962 } 963 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 964 sc->memmap[ASPEED_DEV_TIMER1]); 965 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 966 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 967 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 968 } 969 970 /* HACE */ 971 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 972 &error_abort); 973 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 974 return; 975 } 976 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 977 sc->memmap[ASPEED_DEV_HACE]); 978 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 979 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 980 981 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), 982 "aspeed.dpmcu", 983 sc->memmap[ASPEED_DEV_DPMCU], 984 AST2700_SOC_DPMCU_SIZE); 985 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), 986 "aspeed.ltpi", 987 sc->memmap[ASPEED_DEV_LTPI], 988 AST2700_SOC_LTPI_SIZE); 989 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), 990 "aspeed.io", 991 sc->memmap[ASPEED_DEV_IOMEM], 992 AST2700_SOC_IO_SIZE); 993 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0), 994 "aspeed.iomem0", 995 sc->memmap[ASPEED_DEV_IOMEM0], 996 AST2700_SOC_IOMEM_SIZE); 997 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1), 998 "aspeed.iomem1", 999 sc->memmap[ASPEED_DEV_IOMEM1], 1000 AST2700_SOC_IOMEM_SIZE); 1001 } 1002 1003 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 1004 { 1005 static const char * const valid_cpu_types[] = { 1006 ARM_CPU_TYPE_NAME("cortex-a35"), 1007 NULL 1008 }; 1009 DeviceClass *dc = DEVICE_CLASS(oc); 1010 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1011 1012 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1013 dc->user_creatable = false; 1014 dc->realize = aspeed_soc_ast2700_realize; 1015 1016 sc->valid_cpu_types = valid_cpu_types; 1017 sc->silicon_rev = AST2700_A0_SILICON_REV; 1018 sc->sram_size = 0x20000; 1019 sc->spis_num = 3; 1020 sc->ehcis_num = 2; 1021 sc->wdts_num = 8; 1022 sc->macs_num = 1; 1023 sc->uarts_num = 13; 1024 sc->num_cpus = 4; 1025 sc->uarts_base = ASPEED_DEV_UART0; 1026 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 1027 sc->memmap = aspeed_soc_ast2700_memmap; 1028 sc->get_irq = aspeed_soc_ast2700_get_irq; 1029 } 1030 1031 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 1032 { 1033 static const char * const valid_cpu_types[] = { 1034 ARM_CPU_TYPE_NAME("cortex-a35"), 1035 NULL 1036 }; 1037 DeviceClass *dc = DEVICE_CLASS(oc); 1038 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1039 1040 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1041 dc->user_creatable = false; 1042 dc->realize = aspeed_soc_ast2700_realize; 1043 1044 sc->valid_cpu_types = valid_cpu_types; 1045 sc->silicon_rev = AST2700_A1_SILICON_REV; 1046 sc->sram_size = 0x20000; 1047 sc->spis_num = 3; 1048 sc->ehcis_num = 4; 1049 sc->wdts_num = 8; 1050 sc->macs_num = 3; 1051 sc->uarts_num = 13; 1052 sc->num_cpus = 4; 1053 sc->uarts_base = ASPEED_DEV_UART0; 1054 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 1055 sc->memmap = aspeed_soc_ast2700_memmap; 1056 sc->get_irq = aspeed_soc_ast2700_get_irq; 1057 } 1058 1059 static const TypeInfo aspeed_soc_ast27x0_types[] = { 1060 { 1061 .name = TYPE_ASPEED27X0_SOC, 1062 .parent = TYPE_ASPEED_SOC, 1063 .instance_size = sizeof(Aspeed27x0SoCState), 1064 .abstract = true, 1065 }, { 1066 .name = "ast2700-a0", 1067 .parent = TYPE_ASPEED27X0_SOC, 1068 .instance_init = aspeed_soc_ast2700_init, 1069 .class_init = aspeed_soc_ast2700a0_class_init, 1070 }, 1071 { 1072 .name = "ast2700-a1", 1073 .parent = TYPE_ASPEED27X0_SOC, 1074 .instance_init = aspeed_soc_ast2700_init, 1075 .class_init = aspeed_soc_ast2700a1_class_init, 1076 }, 1077 }; 1078 1079 DEFINE_TYPES(aspeed_soc_ast27x0_types) 1080