1 /* 2 * ASPEED SoC 27x0 family 3 * 4 * Copyright (C) 2024 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for AST27x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/arm/bsa.h" 17 #include "qemu/module.h" 18 #include "qemu/error-report.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "net/net.h" 21 #include "system/system.h" 22 #include "hw/intc/arm_gicv3.h" 23 #include "qobject/qlist.h" 24 #include "qemu/log.h" 25 #include "hw/qdev-clock.h" 26 #include "hw/boards.h" 27 28 #define AST2700_SOC_IO_SIZE 0x00FE0000 29 #define AST2700_SOC_IOMEM_SIZE 0x01000000 30 #define AST2700_SOC_DPMCU_SIZE 0x00040000 31 #define AST2700_SOC_LTPI_SIZE 0x01000000 32 33 static const hwaddr aspeed_soc_ast2700_memmap[] = { 34 [ASPEED_DEV_VBOOTROM] = 0x00000000, 35 [ASPEED_DEV_IOMEM] = 0x00020000, 36 [ASPEED_DEV_SRAM] = 0x10000000, 37 [ASPEED_DEV_DPMCU] = 0x11000000, 38 [ASPEED_DEV_IOMEM0] = 0x12000000, 39 [ASPEED_DEV_EHCI1] = 0x12061000, 40 [ASPEED_DEV_EHCI2] = 0x12063000, 41 [ASPEED_DEV_HACE] = 0x12070000, 42 [ASPEED_DEV_EMMC] = 0x12090000, 43 [ASPEED_DEV_PCIE0] = 0x120E0000, 44 [ASPEED_DEV_PCIE1] = 0x120F0000, 45 [ASPEED_DEV_INTC] = 0x12100000, 46 [ASPEED_GIC_DIST] = 0x12200000, 47 [ASPEED_GIC_REDIST] = 0x12280000, 48 [ASPEED_DEV_SDMC] = 0x12C00000, 49 [ASPEED_DEV_SCU] = 0x12C02000, 50 [ASPEED_DEV_RTC] = 0x12C0F000, 51 [ASPEED_DEV_TIMER1] = 0x12C10000, 52 [ASPEED_DEV_PCIE_PHY0] = 0x12C15000, 53 [ASPEED_DEV_PCIE_PHY1] = 0x12C15800, 54 [ASPEED_DEV_SLI] = 0x12C17000, 55 [ASPEED_DEV_UART4] = 0x12C1A000, 56 [ASPEED_DEV_IOMEM1] = 0x14000000, 57 [ASPEED_DEV_FMC] = 0x14000000, 58 [ASPEED_DEV_SPI0] = 0x14010000, 59 [ASPEED_DEV_SPI1] = 0x14020000, 60 [ASPEED_DEV_SPI2] = 0x14030000, 61 [ASPEED_DEV_MII1] = 0x14040000, 62 [ASPEED_DEV_MII2] = 0x14040008, 63 [ASPEED_DEV_MII3] = 0x14040010, 64 [ASPEED_DEV_ETH1] = 0x14050000, 65 [ASPEED_DEV_ETH2] = 0x14060000, 66 [ASPEED_DEV_ETH3] = 0x14070000, 67 [ASPEED_DEV_SDHCI] = 0x14080000, 68 [ASPEED_DEV_PCIE2] = 0x140D0000, 69 [ASPEED_DEV_EHCI3] = 0x14121000, 70 [ASPEED_DEV_EHCI4] = 0x14123000, 71 [ASPEED_DEV_ADC] = 0x14C00000, 72 [ASPEED_DEV_SCUIO] = 0x14C02000, 73 [ASPEED_DEV_GPIO] = 0x14C0B000, 74 [ASPEED_DEV_I2C] = 0x14C0F000, 75 [ASPEED_DEV_INTCIO] = 0x14C18000, 76 [ASPEED_DEV_PCIE_PHY2] = 0x14C1C000, 77 [ASPEED_DEV_SLIIO] = 0x14C1E000, 78 [ASPEED_DEV_VUART] = 0x14C30000, 79 [ASPEED_DEV_UART0] = 0x14C33000, 80 [ASPEED_DEV_UART1] = 0x14C33100, 81 [ASPEED_DEV_UART2] = 0x14C33200, 82 [ASPEED_DEV_UART3] = 0x14C33300, 83 [ASPEED_DEV_UART5] = 0x14C33400, 84 [ASPEED_DEV_UART6] = 0x14C33500, 85 [ASPEED_DEV_UART7] = 0x14C33600, 86 [ASPEED_DEV_UART8] = 0x14C33700, 87 [ASPEED_DEV_UART9] = 0x14C33800, 88 [ASPEED_DEV_UART10] = 0x14C33900, 89 [ASPEED_DEV_UART11] = 0x14C33A00, 90 [ASPEED_DEV_UART12] = 0x14C33B00, 91 [ASPEED_DEV_WDT] = 0x14C37000, 92 [ASPEED_DEV_PCIE_MMIO0] = 0x60000000, 93 [ASPEED_DEV_PCIE_MMIO1] = 0x80000000, 94 [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000, 95 [ASPEED_DEV_SPI_BOOT] = 0x100000000, 96 [ASPEED_DEV_LTPI] = 0x300000000, 97 [ASPEED_DEV_SDRAM] = 0x400000000, 98 }; 99 100 #define AST2700_MAX_IRQ 256 101 102 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 103 static const int aspeed_soc_ast2700a0_irqmap[] = { 104 [ASPEED_DEV_SDMC] = 0, 105 [ASPEED_DEV_HACE] = 4, 106 [ASPEED_DEV_XDMA] = 5, 107 [ASPEED_DEV_UART4] = 8, 108 [ASPEED_DEV_SCU] = 12, 109 [ASPEED_DEV_RTC] = 13, 110 [ASPEED_DEV_EMMC] = 15, 111 [ASPEED_DEV_TIMER1] = 16, 112 [ASPEED_DEV_TIMER2] = 17, 113 [ASPEED_DEV_TIMER3] = 18, 114 [ASPEED_DEV_TIMER4] = 19, 115 [ASPEED_DEV_TIMER5] = 20, 116 [ASPEED_DEV_TIMER6] = 21, 117 [ASPEED_DEV_TIMER7] = 22, 118 [ASPEED_DEV_TIMER8] = 23, 119 [ASPEED_DEV_DP] = 28, 120 [ASPEED_DEV_EHCI1] = 33, 121 [ASPEED_DEV_EHCI2] = 37, 122 [ASPEED_DEV_LPC] = 128, 123 [ASPEED_DEV_IBT] = 128, 124 [ASPEED_DEV_KCS] = 128, 125 [ASPEED_DEV_ADC] = 130, 126 [ASPEED_DEV_GPIO] = 130, 127 [ASPEED_DEV_I2C] = 130, 128 [ASPEED_DEV_FMC] = 131, 129 [ASPEED_DEV_WDT] = 131, 130 [ASPEED_DEV_PWM] = 131, 131 [ASPEED_DEV_I3C] = 131, 132 [ASPEED_DEV_UART0] = 132, 133 [ASPEED_DEV_UART1] = 132, 134 [ASPEED_DEV_UART2] = 132, 135 [ASPEED_DEV_UART3] = 132, 136 [ASPEED_DEV_UART5] = 132, 137 [ASPEED_DEV_UART6] = 132, 138 [ASPEED_DEV_UART7] = 132, 139 [ASPEED_DEV_UART8] = 132, 140 [ASPEED_DEV_UART9] = 132, 141 [ASPEED_DEV_UART10] = 132, 142 [ASPEED_DEV_UART11] = 132, 143 [ASPEED_DEV_UART12] = 132, 144 [ASPEED_DEV_ETH1] = 132, 145 [ASPEED_DEV_ETH2] = 132, 146 [ASPEED_DEV_ETH3] = 132, 147 [ASPEED_DEV_PECI] = 133, 148 [ASPEED_DEV_SDHCI] = 133, 149 }; 150 151 static const int aspeed_soc_ast2700a1_irqmap[] = { 152 [ASPEED_DEV_SDMC] = 0, 153 [ASPEED_DEV_HACE] = 4, 154 [ASPEED_DEV_XDMA] = 5, 155 [ASPEED_DEV_UART4] = 8, 156 [ASPEED_DEV_SCU] = 12, 157 [ASPEED_DEV_RTC] = 13, 158 [ASPEED_DEV_EMMC] = 15, 159 [ASPEED_DEV_TIMER1] = 16, 160 [ASPEED_DEV_TIMER2] = 17, 161 [ASPEED_DEV_TIMER3] = 18, 162 [ASPEED_DEV_TIMER4] = 19, 163 [ASPEED_DEV_TIMER5] = 20, 164 [ASPEED_DEV_TIMER6] = 21, 165 [ASPEED_DEV_TIMER7] = 22, 166 [ASPEED_DEV_TIMER8] = 23, 167 [ASPEED_DEV_DP] = 28, 168 [ASPEED_DEV_EHCI1] = 33, 169 [ASPEED_DEV_EHCI2] = 37, 170 [ASPEED_DEV_PCIE0] = 56, 171 [ASPEED_DEV_PCIE1] = 57, 172 [ASPEED_DEV_LPC] = 192, 173 [ASPEED_DEV_IBT] = 192, 174 [ASPEED_DEV_KCS] = 192, 175 [ASPEED_DEV_I2C] = 194, 176 [ASPEED_DEV_ADC] = 194, 177 [ASPEED_DEV_GPIO] = 194, 178 [ASPEED_DEV_FMC] = 195, 179 [ASPEED_DEV_WDT] = 195, 180 [ASPEED_DEV_PWM] = 195, 181 [ASPEED_DEV_I3C] = 195, 182 [ASPEED_DEV_PCIE2] = 196, 183 [ASPEED_DEV_UART0] = 196, 184 [ASPEED_DEV_UART1] = 196, 185 [ASPEED_DEV_UART2] = 196, 186 [ASPEED_DEV_UART3] = 196, 187 [ASPEED_DEV_UART5] = 196, 188 [ASPEED_DEV_UART6] = 196, 189 [ASPEED_DEV_UART7] = 196, 190 [ASPEED_DEV_UART8] = 196, 191 [ASPEED_DEV_UART9] = 196, 192 [ASPEED_DEV_UART10] = 196, 193 [ASPEED_DEV_UART11] = 196, 194 [ASPEED_DEV_UART12] = 196, 195 [ASPEED_DEV_ETH1] = 196, 196 [ASPEED_DEV_ETH2] = 196, 197 [ASPEED_DEV_ETH3] = 196, 198 [ASPEED_DEV_PECI] = 197, 199 [ASPEED_DEV_SDHCI] = 197, 200 }; 201 202 /* GICINT 128 */ 203 /* GICINT 192 */ 204 static const int ast2700_gic128_gic192_intcmap[] = { 205 [ASPEED_DEV_LPC] = 0, 206 [ASPEED_DEV_IBT] = 2, 207 [ASPEED_DEV_KCS] = 4, 208 }; 209 210 /* GICINT 129 */ 211 /* GICINT 193 */ 212 213 /* GICINT 130 */ 214 /* GICINT 194 */ 215 static const int ast2700_gic130_gic194_intcmap[] = { 216 [ASPEED_DEV_I2C] = 0, 217 [ASPEED_DEV_ADC] = 16, 218 [ASPEED_DEV_GPIO] = 18, 219 }; 220 221 /* GICINT 131 */ 222 /* GICINT 195 */ 223 static const int ast2700_gic131_gic195_intcmap[] = { 224 [ASPEED_DEV_I3C] = 0, 225 [ASPEED_DEV_WDT] = 16, 226 [ASPEED_DEV_FMC] = 25, 227 [ASPEED_DEV_PWM] = 29, 228 }; 229 230 /* GICINT 132 */ 231 /* GICINT 196 */ 232 static const int ast2700_gic132_gic196_intcmap[] = { 233 [ASPEED_DEV_ETH1] = 0, 234 [ASPEED_DEV_ETH2] = 1, 235 [ASPEED_DEV_ETH3] = 2, 236 [ASPEED_DEV_UART0] = 7, 237 [ASPEED_DEV_UART1] = 8, 238 [ASPEED_DEV_UART2] = 9, 239 [ASPEED_DEV_UART3] = 10, 240 [ASPEED_DEV_UART5] = 11, 241 [ASPEED_DEV_UART6] = 12, 242 [ASPEED_DEV_UART7] = 13, 243 [ASPEED_DEV_UART8] = 14, 244 [ASPEED_DEV_UART9] = 15, 245 [ASPEED_DEV_UART10] = 16, 246 [ASPEED_DEV_UART11] = 17, 247 [ASPEED_DEV_UART12] = 18, 248 [ASPEED_DEV_EHCI3] = 28, 249 [ASPEED_DEV_EHCI4] = 29, 250 [ASPEED_DEV_PCIE2] = 31, 251 }; 252 253 /* GICINT 133 */ 254 /* GICINT 197 */ 255 static const int ast2700_gic133_gic197_intcmap[] = { 256 [ASPEED_DEV_SDHCI] = 1, 257 [ASPEED_DEV_PECI] = 4, 258 }; 259 260 /* GICINT 128 ~ 136 */ 261 /* GICINT 192 ~ 201 */ 262 struct gic_intc_irq_info { 263 int irq; 264 int intc_idx; 265 int orgate_idx; 266 const int *ptr; 267 }; 268 269 static const struct gic_intc_irq_info ast2700_gic_intcmap[] = { 270 {192, 1, 0, ast2700_gic128_gic192_intcmap}, 271 {193, 1, 1, NULL}, 272 {194, 1, 2, ast2700_gic130_gic194_intcmap}, 273 {195, 1, 3, ast2700_gic131_gic195_intcmap}, 274 {196, 1, 4, ast2700_gic132_gic196_intcmap}, 275 {197, 1, 5, ast2700_gic133_gic197_intcmap}, 276 {198, 1, 6, NULL}, 277 {199, 1, 7, NULL}, 278 {200, 1, 8, NULL}, 279 {201, 1, 9, NULL}, 280 {128, 0, 1, ast2700_gic128_gic192_intcmap}, 281 {129, 0, 2, NULL}, 282 {130, 0, 3, ast2700_gic130_gic194_intcmap}, 283 {131, 0, 4, ast2700_gic131_gic195_intcmap}, 284 {132, 0, 5, ast2700_gic132_gic196_intcmap}, 285 {133, 0, 6, ast2700_gic133_gic197_intcmap}, 286 {134, 0, 7, NULL}, 287 {135, 0, 8, NULL}, 288 {136, 0, 9, NULL}, 289 }; 290 291 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) 292 { 293 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 294 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 295 int or_idx; 296 int idx; 297 int i; 298 299 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 300 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 301 assert(ast2700_gic_intcmap[i].ptr); 302 or_idx = ast2700_gic_intcmap[i].orgate_idx; 303 idx = ast2700_gic_intcmap[i].intc_idx; 304 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 305 ast2700_gic_intcmap[i].ptr[dev]); 306 } 307 } 308 309 return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]); 310 } 311 312 static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev, 313 int index) 314 { 315 Aspeed27x0SoCState *a = ASPEED27X0_SOC(s); 316 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 317 int or_idx; 318 int idx; 319 int i; 320 321 for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { 322 if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) { 323 assert(ast2700_gic_intcmap[i].ptr); 324 or_idx = ast2700_gic_intcmap[i].orgate_idx; 325 idx = ast2700_gic_intcmap[i].intc_idx; 326 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 327 ast2700_gic_intcmap[i].ptr[dev] + index); 328 } 329 } 330 331 /* 332 * Invalid OR gate index, device IRQ should be between 128 to 136 333 * and 192 to 201. 334 */ 335 g_assert_not_reached(); 336 } 337 338 static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr, 339 unsigned int size) 340 { 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n", 343 __func__, addr); 344 return 0; 345 } 346 347 static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data, 348 unsigned int size) 349 { 350 AspeedSoCState *s = ASPEED_SOC(opaque); 351 ram_addr_t ram_size; 352 MemTxResult result; 353 354 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 355 &error_abort); 356 357 assert(ram_size > 0); 358 359 /* 360 * Emulate ddr capacity hardware behavior. 361 * If writes the data to the address which is beyond the ram size, 362 * it would write the data to the "address % ram_size". 363 */ 364 address_space_stl_le(&s->dram_as, addr % ram_size, data, 365 MEMTXATTRS_UNSPECIFIED, &result); 366 367 if (result != MEMTX_OK) { 368 qemu_log_mask(LOG_GUEST_ERROR, 369 "%s: DRAM write failed, addr:0x%" HWADDR_PRIx 370 ", data :0x%" PRIx64 "\n", 371 __func__, addr % ram_size, data); 372 } 373 } 374 375 static const MemoryRegionOps aspeed_ram_capacity_ops = { 376 .read = aspeed_ram_capacity_read, 377 .write = aspeed_ram_capacity_write, 378 .endianness = DEVICE_LITTLE_ENDIAN, 379 .impl.min_access_size = 4, 380 .valid = { 381 .min_access_size = 4, 382 .max_access_size = 4, 383 }, 384 }; 385 386 /* 387 * SDMC should be realized first to get correct RAM size and max size 388 * values 389 */ 390 static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp) 391 { 392 ram_addr_t ram_size, max_ram_size; 393 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 394 AspeedSoCState *s = ASPEED_SOC(dev); 395 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 396 397 ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size", 398 &error_abort); 399 max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size", 400 &error_abort); 401 402 memory_region_init(&s->dram_container, OBJECT(s), "ram-container", 403 ram_size); 404 memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); 405 address_space_init(&s->dram_as, s->dram_mr, "dram"); 406 407 /* 408 * Add a memory region beyond the RAM region to emulate 409 * ddr capacity hardware behavior. 410 */ 411 if (ram_size < max_ram_size) { 412 memory_region_init_io(&a->dram_empty, OBJECT(s), 413 &aspeed_ram_capacity_ops, s, 414 "ram-empty", max_ram_size - ram_size); 415 416 memory_region_add_subregion(s->memory, 417 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, 418 &a->dram_empty); 419 } 420 421 memory_region_add_subregion(s->memory, 422 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); 423 return true; 424 } 425 426 static void aspeed_soc_ast2700_init(Object *obj) 427 { 428 MachineState *ms = MACHINE(qdev_get_machine()); 429 MachineClass *mc = MACHINE_GET_CLASS(ms); 430 Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj); 431 AspeedSoCState *s = ASPEED_SOC(obj); 432 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 433 int i; 434 char socname[8]; 435 char typename[64]; 436 437 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 438 g_assert_not_reached(); 439 } 440 441 for (i = 0; i < sc->num_cpus; i++) { 442 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 443 aspeed_soc_cpu_type(sc)); 444 } 445 446 /* Coprocessors */ 447 if (mc->default_cpus > sc->num_cpus) { 448 object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC); 449 object_initialize_child(obj, "tsp", &a->tsp, TYPE_ASPEED27X0TSP_SOC); 450 } 451 452 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); 453 454 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); 455 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 456 sc->silicon_rev); 457 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 458 "hw-strap1"); 459 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 460 "hw-prot-key"); 461 462 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO); 463 qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", 464 sc->silicon_rev); 465 /* 466 * There is one hw-strap1 register in the SCU (CPU DIE) and another 467 * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design 468 * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the 469 * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and 470 * sets the value in the SCUIO hw-strap1 register. 471 */ 472 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), 473 "hw-strap1"); 474 475 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 476 object_initialize_child(obj, "fmc", &s->fmc, typename); 477 478 for (i = 0; i < sc->spis_num; i++) { 479 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname); 480 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 481 } 482 483 for (i = 0; i < sc->ehcis_num; i++) { 484 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 485 TYPE_PLATFORM_EHCI); 486 } 487 488 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 489 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 490 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 491 "ram-size"); 492 493 for (i = 0; i < sc->wdts_num; i++) { 494 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 495 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 496 } 497 498 for (i = 0; i < sc->macs_num; i++) { 499 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 500 TYPE_FTGMAC100); 501 502 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 503 } 504 505 for (i = 0; i < sc->uarts_num; i++) { 506 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 507 } 508 509 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); 510 object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO); 511 object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC); 512 object_initialize_child(obj, "intcio", &a->intc[1], 513 TYPE_ASPEED_2700_INTCIO); 514 515 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 516 object_initialize_child(obj, "adc", &s->adc, typename); 517 518 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 519 object_initialize_child(obj, "i2c", &s->i2c, typename); 520 521 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 522 object_initialize_child(obj, "gpio", &s->gpio, typename); 523 524 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 525 526 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 527 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 528 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort); 529 530 /* Init sd card slot class here so that they're under the correct parent */ 531 object_initialize_child(obj, "sd-controller.sdhci", 532 &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI); 533 534 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 535 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 536 537 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 538 TYPE_SYSBUS_SDHCI); 539 540 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 541 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 542 543 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 544 object_initialize_child(obj, "hace", &s->hace, typename); 545 546 for (i = 0; i < sc->pcie_num; i++) { 547 snprintf(typename, sizeof(typename), "aspeed.pcie-phy-%s", socname); 548 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i], typename); 549 object_property_set_int(OBJECT(&s->pcie_phy[i]), "id", i, &error_abort); 550 551 snprintf(typename, sizeof(typename), "aspeed.pcie-cfg-%s", socname); 552 object_initialize_child(obj, "pcie-cfg[*]", &s->pcie[i], typename); 553 object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort); 554 } 555 556 object_initialize_child(obj, "dpmcu", &s->dpmcu, 557 TYPE_UNIMPLEMENTED_DEVICE); 558 object_initialize_child(obj, "ltpi", &s->ltpi, 559 TYPE_UNIMPLEMENTED_DEVICE); 560 object_initialize_child(obj, "iomem", &s->iomem, 561 TYPE_UNIMPLEMENTED_DEVICE); 562 object_initialize_child(obj, "iomem0", &s->iomem0, 563 TYPE_UNIMPLEMENTED_DEVICE); 564 object_initialize_child(obj, "iomem1", &s->iomem1, 565 TYPE_UNIMPLEMENTED_DEVICE); 566 } 567 568 /* 569 * ASPEED ast2700 has 0x0 as cluster ID 570 * 571 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1 572 */ 573 static uint64_t aspeed_calc_affinity(int cpu) 574 { 575 return (0x0 << ARM_AFF1_SHIFT) | cpu; 576 } 577 578 static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) 579 { 580 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 581 AspeedSoCState *s = ASPEED_SOC(dev); 582 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 583 SysBusDevice *gicbusdev; 584 DeviceState *gicdev; 585 QList *redist_region_count; 586 int i; 587 588 gicbusdev = SYS_BUS_DEVICE(&a->gic); 589 gicdev = DEVICE(&a->gic); 590 qdev_prop_set_uint32(gicdev, "revision", 3); 591 qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); 592 qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL); 593 594 redist_region_count = qlist_new(); 595 qlist_append_int(redist_region_count, sc->num_cpus); 596 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); 597 598 if (!sysbus_realize(gicbusdev, errp)) { 599 return false; 600 } 601 602 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0, 603 sc->memmap[ASPEED_GIC_DIST]); 604 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1, 605 sc->memmap[ASPEED_GIC_REDIST]); 606 607 for (i = 0; i < sc->num_cpus; i++) { 608 DeviceState *cpudev = DEVICE(&a->cpu[i]); 609 int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL; 610 611 const int timer_irq[] = { 612 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 613 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 614 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 615 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 616 }; 617 int j; 618 619 for (j = 0; j < ARRAY_SIZE(timer_irq); j++) { 620 qdev_connect_gpio_out(cpudev, j, 621 qdev_get_gpio_in(gicdev, intidbase + timer_irq[j])); 622 } 623 624 qemu_irq irq = qdev_get_gpio_in(gicdev, 625 intidbase + ARCH_GIC_MAINT_IRQ); 626 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 627 0, irq); 628 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 629 qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ)); 630 631 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 632 sysbus_connect_irq(gicbusdev, i + sc->num_cpus, 633 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 634 sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus, 635 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 636 sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus, 637 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 638 sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus, 639 qdev_get_gpio_in(cpudev, ARM_CPU_NMI)); 640 sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus, 641 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI)); 642 } 643 644 return true; 645 } 646 647 static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp) 648 { 649 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 650 AspeedSoCState *s = ASPEED_SOC(dev); 651 MemoryRegion *mr; 652 Clock *sysclk; 653 654 sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); 655 clock_set_hz(sysclk, 200000000ULL); 656 qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk); 657 658 memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory", 659 UINT64_MAX); 660 if (!object_property_set_link(OBJECT(&a->ssp), "memory", 661 OBJECT(&a->ssp.memory), &error_abort)) { 662 return false; 663 } 664 665 mr = &s->sram; 666 memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias", 667 mr, 0, memory_region_size(mr)); 668 669 mr = &s->scu.iomem; 670 memory_region_init_alias(&a->ssp.scu_mr_alias, OBJECT(s), "ssp.scu.alias", 671 mr, 0, memory_region_size(mr)); 672 if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { 673 return false; 674 } 675 676 return true; 677 } 678 679 static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp) 680 { 681 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 682 AspeedSoCState *s = ASPEED_SOC(dev); 683 MemoryRegion *mr; 684 Clock *sysclk; 685 686 sysclk = clock_new(OBJECT(s), "TSP_SYSCLK"); 687 clock_set_hz(sysclk, 200000000ULL); 688 qdev_connect_clock_in(DEVICE(&a->tsp), "sysclk", sysclk); 689 690 memory_region_init(&a->tsp.memory, OBJECT(&a->tsp), "tsp-memory", 691 UINT64_MAX); 692 if (!object_property_set_link(OBJECT(&a->tsp), "memory", 693 OBJECT(&a->tsp.memory), &error_abort)) { 694 return false; 695 } 696 697 mr = &s->sram; 698 memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.alias", 699 mr, 0, memory_region_size(mr)); 700 701 mr = &s->scu.iomem; 702 memory_region_init_alias(&a->tsp.scu_mr_alias, OBJECT(s), "tsp.scu.alias", 703 mr, 0, memory_region_size(mr)); 704 if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) { 705 return false; 706 } 707 708 return true; 709 } 710 711 static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) 712 { 713 int i; 714 MachineState *ms = MACHINE(qdev_get_machine()); 715 MachineClass *mc = MACHINE_GET_CLASS(ms); 716 Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev); 717 AspeedSoCState *s = ASPEED_SOC(dev); 718 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 719 AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]); 720 AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]); 721 g_autofree char *name = NULL; 722 MemoryRegion *mmio_alias; 723 MemoryRegion *mmio_mr; 724 qemu_irq irq; 725 726 /* Default boot region (SPI memory or ROMs) */ 727 memory_region_init(&s->spi_boot_container, OBJECT(s), 728 "aspeed.spi_boot_container", 0x400000000); 729 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 730 &s->spi_boot_container); 731 732 /* CPU */ 733 for (i = 0; i < sc->num_cpus; i++) { 734 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 735 aspeed_calc_affinity(i), &error_abort); 736 737 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 738 &error_abort); 739 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 740 OBJECT(s->memory), &error_abort); 741 742 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 743 return; 744 } 745 } 746 747 /* GIC */ 748 if (!aspeed_soc_ast2700_gic_realize(dev, errp)) { 749 return; 750 } 751 752 /* INTC */ 753 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 754 return; 755 } 756 757 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 758 sc->memmap[ASPEED_DEV_INTC]); 759 760 /* INTCIO */ 761 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 762 return; 763 } 764 765 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 766 sc->memmap[ASPEED_DEV_INTCIO]); 767 768 /* irq sources -> orgates -> INTC */ 769 for (i = 0; i < ic->num_inpins; i++) { 770 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 771 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 772 } 773 774 /* INTC -> GIC192 - GIC201 */ 775 /* INTC -> GIC128 - GIC136 */ 776 for (i = 0; i < ic->num_outpins; i++) { 777 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 778 qdev_get_gpio_in(DEVICE(&a->gic), 779 ast2700_gic_intcmap[i].irq)); 780 } 781 782 /* irq source -> orgates -> INTCIO */ 783 for (i = 0; i < icio->num_inpins; i++) { 784 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 785 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 786 } 787 788 /* INTCIO -> INTC */ 789 for (i = 0; i < icio->num_outpins; i++) { 790 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 791 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 792 } 793 794 /* 795 * SDMC - SDRAM Memory Controller 796 * The SDMC controller is unlocked at SPL stage. 797 * At present, only supports to emulate booting 798 * start from u-boot stage. Set SDMC controller 799 * unlocked by default. It is a temporarily solution. 800 */ 801 object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, 802 &error_abort); 803 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 804 return; 805 } 806 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 807 sc->memmap[ASPEED_DEV_SDMC]); 808 809 /* RAM */ 810 if (!aspeed_soc_ast2700_dram_init(dev, errp)) { 811 return; 812 } 813 814 /* SRAM */ 815 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 816 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 817 errp)) { 818 return; 819 } 820 memory_region_add_subregion(s->memory, 821 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 822 823 /* VBOOTROM */ 824 if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom", 825 0x20000, errp)) { 826 return; 827 } 828 memory_region_add_subregion(s->memory, 829 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); 830 831 /* SCU */ 832 /* 833 * The SSP coprocessor uses two memory aliases (remap1 and remap2) 834 * to access shared memory regions in the PSP DRAM: 835 * 836 * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM 837 * offset 0x2000000 838 * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM 839 * offset 0x0 840 * 841 * The TSP coprocessor uses one memory alias (remap) to access a shared 842 * region in the PSP DRAM: 843 * 844 * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM 845 * offset 0x0 846 * 847 * These mappings correspond to the default values of the SCU registers: 848 * 849 * This configuration enables shared memory communication between the PSP 850 * and coprocessors, with address translation controlled by the SCU. 851 */ 852 if (mc->default_cpus > sc->num_cpus) { 853 memory_region_init_alias(&a->ssp.sdram_remap1_alias, OBJECT(a), 854 "ssp.sdram.remap1", s->memory, 855 0x400000000ULL, 32 * MiB); 856 memory_region_init_alias(&a->ssp.sdram_remap2_alias, OBJECT(a), 857 "ssp.sdram.remap2", s->memory, 858 0x42c000000ULL, 32 * MiB); 859 memory_region_init_alias(&a->tsp.sdram_remap_alias, OBJECT(a), 860 "tsp.sdram.remap", s->memory, 861 0x42e000000, 32 * MiB); 862 object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap1", 863 OBJECT(&a->ssp.sdram_remap1_alias), 864 &error_abort); 865 object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2", 866 OBJECT(&a->ssp.sdram_remap2_alias), 867 &error_abort); 868 object_property_set_link(OBJECT(&s->scu), "tsp-sdram-remap", 869 OBJECT(&a->tsp.sdram_remap_alias), 870 &error_abort); 871 } 872 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 873 return; 874 } 875 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 876 877 /* SCU1 */ 878 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) { 879 return; 880 } 881 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, 882 sc->memmap[ASPEED_DEV_SCUIO]); 883 884 /* 885 * Coprocessors must be realized after the DRAM, SRAM, and SCU regions. 886 * 887 * - DRAM: Coprocessors access shared memory through MemoryRegion aliases 888 * that point into PSP's DRAM space. These aliases are mapped into the 889 * coprocessors' SDRAM windows at specific offsets (e.g., 0x0 and 890 * 0x2000000), and configured according to SCU register defaults. 891 * Therefore, DRAM must be fully initialized before coprocessors can 892 * attach aliases to it. 893 * 894 * - SRAM: Used as shared memory between the PSP and coprocessors. 895 * Coprocessors access this memory via alias regions mapped to 896 * different physical addresses. 897 * 898 * - SCU: A single hardware block shared across all processors. 899 * Coprocessors access SCU registers through alias mappings. 900 * SCU must be initialized first to allow for consistent register 901 * state and memory remap configuration. 902 * 903 * To ensure correctness, the device realization order is explicitly 904 * managed: coprocessors are initialized only after DRAM, SRAM, and SCU 905 * are ready. 906 */ 907 if (mc->default_cpus > sc->num_cpus) { 908 if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { 909 return; 910 } 911 if (!aspeed_soc_ast2700_tsp_realize(dev, errp)) { 912 return; 913 } 914 } 915 916 /* UART */ 917 if (!aspeed_soc_uart_realize(s, errp)) { 918 return; 919 } 920 921 /* FMC, The number of CS is set at the board level */ 922 object_property_set_int(OBJECT(&s->fmc), "dram-base", 923 sc->memmap[ASPEED_DEV_SDRAM], 924 &error_abort); 925 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 926 &error_abort); 927 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 928 return; 929 } 930 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 931 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 932 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 933 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 934 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 935 936 /* Set up an alias on the FMC CE0 region (boot default) */ 937 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 938 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 939 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 940 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 941 942 /* SPI */ 943 for (i = 0; i < sc->spis_num; i++) { 944 object_property_set_link(OBJECT(&s->spi[i]), "dram", 945 OBJECT(s->dram_mr), &error_abort); 946 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 947 return; 948 } 949 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 950 sc->memmap[ASPEED_DEV_SPI0 + i]); 951 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 952 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 953 } 954 955 /* EHCI */ 956 for (i = 0; i < sc->ehcis_num; i++) { 957 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 958 return; 959 } 960 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 961 sc->memmap[ASPEED_DEV_EHCI1 + i]); 962 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 963 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 964 } 965 966 /* Net */ 967 for (i = 0; i < sc->macs_num; i++) { 968 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 969 &error_abort); 970 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true, 971 &error_abort); 972 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 973 return; 974 } 975 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 976 sc->memmap[ASPEED_DEV_ETH1 + i]); 977 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 978 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 979 980 object_property_set_link(OBJECT(&s->mii[i]), "nic", 981 OBJECT(&s->ftgmac100[i]), &error_abort); 982 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 983 return; 984 } 985 986 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 987 sc->memmap[ASPEED_DEV_MII1 + i]); 988 } 989 990 /* Watch dog */ 991 for (i = 0; i < sc->wdts_num; i++) { 992 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 993 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 994 995 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 996 &error_abort); 997 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 998 return; 999 } 1000 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 1001 } 1002 1003 /* SLI */ 1004 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) { 1005 return; 1006 } 1007 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sli), 0, sc->memmap[ASPEED_DEV_SLI]); 1008 1009 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) { 1010 return; 1011 } 1012 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sliio), 0, 1013 sc->memmap[ASPEED_DEV_SLIIO]); 1014 1015 /* ADC */ 1016 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 1017 return; 1018 } 1019 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 1020 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 1021 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 1022 1023 /* I2C */ 1024 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 1025 &error_abort); 1026 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 1027 return; 1028 } 1029 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 1030 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 1031 /* 1032 * The AST2700 I2C controller has one source INTC per bus. 1033 * 1034 * For AST2700 A0: 1035 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 1036 * 15, and the OR gate output pin is connected to the input pin of 1037 * GICINT130 of INTC (CPU Die). Then, the output pin is connected to 1038 * the GIC. 1039 * 1040 * For AST2700 A1: 1041 * I2C bus interrupts are connected to the OR gate from bit 0 to bit 1042 * 15, and the OR gate output pin is connected to the input pin of 1043 * GICINT194 of INTCIO (IO Die). Then, the output pin is connected 1044 * to the INTC (CPU Die) input pin, and its output pin is connected 1045 * to the GIC. 1046 * 1047 * I2C bus 0 is connected to the OR gate at bit 0. 1048 * I2C bus 15 is connected to the OR gate at bit 15. 1049 */ 1050 irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i); 1051 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 1052 } 1053 1054 /* GPIO */ 1055 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 1056 return; 1057 } 1058 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 1059 sc->memmap[ASPEED_DEV_GPIO]); 1060 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 1061 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 1062 1063 /* RTC */ 1064 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 1065 return; 1066 } 1067 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 1068 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 1069 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 1070 1071 /* SDHCI */ 1072 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 1073 return; 1074 } 1075 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 1076 sc->memmap[ASPEED_DEV_SDHCI]); 1077 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 1078 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 1079 1080 /* eMMC */ 1081 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 1082 return; 1083 } 1084 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 1085 sc->memmap[ASPEED_DEV_EMMC]); 1086 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 1087 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 1088 1089 /* Timer */ 1090 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 1091 &error_abort); 1092 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 1093 return; 1094 } 1095 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 1096 sc->memmap[ASPEED_DEV_TIMER1]); 1097 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 1098 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 1099 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 1100 } 1101 1102 /* HACE */ 1103 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 1104 &error_abort); 1105 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 1106 return; 1107 } 1108 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 1109 sc->memmap[ASPEED_DEV_HACE]); 1110 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 1111 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 1112 1113 /* PCIe */ 1114 for (i = 0; i < sc->pcie_num; i++) { 1115 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) { 1116 return; 1117 } 1118 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0, 1119 sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]); 1120 1121 object_property_set_int(OBJECT(&s->pcie[i]), "dram-base", 1122 sc->memmap[ASPEED_DEV_SDRAM], 1123 &error_abort); 1124 object_property_set_link(OBJECT(&s->pcie[i]), "dram", 1125 OBJECT(s->dram_mr), &error_abort); 1126 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) { 1127 return; 1128 } 1129 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[i]), 0, 1130 sc->memmap[ASPEED_DEV_PCIE0 + i]); 1131 irq = aspeed_soc_get_irq(s, ASPEED_DEV_PCIE0 + i); 1132 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq); 1133 1134 name = g_strdup_printf("aspeed.pcie-mmio.%d", i); 1135 mmio_alias = g_new0(MemoryRegion, 1); 1136 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc), 1); 1137 1138 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[i].rc), name, 1139 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i], 1140 0x20000000); 1141 memory_region_add_subregion(s->memory, 1142 sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i], 1143 mmio_alias); 1144 } 1145 1146 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), 1147 "aspeed.dpmcu", 1148 sc->memmap[ASPEED_DEV_DPMCU], 1149 AST2700_SOC_DPMCU_SIZE); 1150 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi), 1151 "aspeed.ltpi", 1152 sc->memmap[ASPEED_DEV_LTPI], 1153 AST2700_SOC_LTPI_SIZE); 1154 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), 1155 "aspeed.io", 1156 sc->memmap[ASPEED_DEV_IOMEM], 1157 AST2700_SOC_IO_SIZE); 1158 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0), 1159 "aspeed.iomem0", 1160 sc->memmap[ASPEED_DEV_IOMEM0], 1161 AST2700_SOC_IOMEM_SIZE); 1162 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1), 1163 "aspeed.iomem1", 1164 sc->memmap[ASPEED_DEV_IOMEM1], 1165 AST2700_SOC_IOMEM_SIZE); 1166 } 1167 1168 static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *data) 1169 { 1170 static const char * const valid_cpu_types[] = { 1171 ARM_CPU_TYPE_NAME("cortex-a35"), 1172 NULL 1173 }; 1174 DeviceClass *dc = DEVICE_CLASS(oc); 1175 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1176 1177 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1178 dc->user_creatable = false; 1179 dc->realize = aspeed_soc_ast2700_realize; 1180 1181 sc->valid_cpu_types = valid_cpu_types; 1182 sc->silicon_rev = AST2700_A0_SILICON_REV; 1183 sc->sram_size = 0x20000; 1184 sc->pcie_num = 0; 1185 sc->spis_num = 3; 1186 sc->ehcis_num = 2; 1187 sc->wdts_num = 8; 1188 sc->macs_num = 1; 1189 sc->uarts_num = 13; 1190 sc->num_cpus = 4; 1191 sc->uarts_base = ASPEED_DEV_UART0; 1192 sc->irqmap = aspeed_soc_ast2700a0_irqmap; 1193 sc->memmap = aspeed_soc_ast2700_memmap; 1194 sc->get_irq = aspeed_soc_ast2700_get_irq; 1195 } 1196 1197 static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) 1198 { 1199 static const char * const valid_cpu_types[] = { 1200 ARM_CPU_TYPE_NAME("cortex-a35"), 1201 NULL 1202 }; 1203 DeviceClass *dc = DEVICE_CLASS(oc); 1204 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 1205 1206 /* Reason: The Aspeed SoC can only be instantiated from a board */ 1207 dc->user_creatable = false; 1208 dc->realize = aspeed_soc_ast2700_realize; 1209 1210 sc->valid_cpu_types = valid_cpu_types; 1211 sc->silicon_rev = AST2700_A1_SILICON_REV; 1212 sc->sram_size = 0x20000; 1213 sc->pcie_num = 3; 1214 sc->spis_num = 3; 1215 sc->ehcis_num = 4; 1216 sc->wdts_num = 8; 1217 sc->macs_num = 3; 1218 sc->uarts_num = 13; 1219 sc->num_cpus = 4; 1220 sc->uarts_base = ASPEED_DEV_UART0; 1221 sc->irqmap = aspeed_soc_ast2700a1_irqmap; 1222 sc->memmap = aspeed_soc_ast2700_memmap; 1223 sc->get_irq = aspeed_soc_ast2700_get_irq; 1224 } 1225 1226 static const TypeInfo aspeed_soc_ast27x0_types[] = { 1227 { 1228 .name = TYPE_ASPEED27X0_SOC, 1229 .parent = TYPE_ASPEED_SOC, 1230 .instance_size = sizeof(Aspeed27x0SoCState), 1231 .abstract = true, 1232 }, { 1233 .name = "ast2700-a0", 1234 .parent = TYPE_ASPEED27X0_SOC, 1235 .instance_init = aspeed_soc_ast2700_init, 1236 .class_init = aspeed_soc_ast2700a0_class_init, 1237 }, 1238 { 1239 .name = "ast2700-a1", 1240 .parent = TYPE_ASPEED27X0_SOC, 1241 .instance_init = aspeed_soc_ast2700_init, 1242 .class_init = aspeed_soc_ast2700a1_class_init, 1243 }, 1244 }; 1245 1246 DEFINE_TYPES(aspeed_soc_ast27x0_types) 1247