1 /* 2 * ASPEED Ast27x0 SSP SoC 3 * 4 * Copyright (C) 2025 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * SPDX-License-Identifier: GPL-2.0-or-later 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/qdev-clock.h" 15 #include "hw/misc/unimp.h" 16 #include "hw/arm/aspeed_soc.h" 17 18 #define AST2700_SSP_SDRAM_SIZE (512 * MiB) 19 20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = { 21 [ASPEED_DEV_SDRAM] = 0x00000000, 22 [ASPEED_DEV_SRAM] = 0x70000000, 23 [ASPEED_DEV_INTC] = 0x72100000, 24 [ASPEED_DEV_SCU] = 0x72C02000, 25 [ASPEED_DEV_SCUIO] = 0x74C02000, 26 [ASPEED_DEV_UART0] = 0x74C33000, 27 [ASPEED_DEV_UART1] = 0x74C33100, 28 [ASPEED_DEV_UART2] = 0x74C33200, 29 [ASPEED_DEV_UART3] = 0x74C33300, 30 [ASPEED_DEV_UART4] = 0x72C1A000, 31 [ASPEED_DEV_INTCIO] = 0x74C18000, 32 [ASPEED_DEV_IPC0] = 0x72C1C000, 33 [ASPEED_DEV_IPC1] = 0x74C39000, 34 [ASPEED_DEV_UART5] = 0x74C33400, 35 [ASPEED_DEV_UART6] = 0x74C33500, 36 [ASPEED_DEV_UART7] = 0x74C33600, 37 [ASPEED_DEV_UART8] = 0x74C33700, 38 [ASPEED_DEV_UART9] = 0x74C33800, 39 [ASPEED_DEV_UART10] = 0x74C33900, 40 [ASPEED_DEV_UART11] = 0x74C33A00, 41 [ASPEED_DEV_UART12] = 0x74C33B00, 42 [ASPEED_DEV_TIMER1] = 0x72C10000, 43 }; 44 45 static const int aspeed_soc_ast27x0ssp_irqmap[] = { 46 [ASPEED_DEV_SCU] = 12, 47 [ASPEED_DEV_UART0] = 164, 48 [ASPEED_DEV_UART1] = 164, 49 [ASPEED_DEV_UART2] = 164, 50 [ASPEED_DEV_UART3] = 164, 51 [ASPEED_DEV_UART4] = 8, 52 [ASPEED_DEV_UART5] = 164, 53 [ASPEED_DEV_UART6] = 164, 54 [ASPEED_DEV_UART7] = 164, 55 [ASPEED_DEV_UART8] = 164, 56 [ASPEED_DEV_UART9] = 164, 57 [ASPEED_DEV_UART10] = 164, 58 [ASPEED_DEV_UART11] = 164, 59 [ASPEED_DEV_UART12] = 164, 60 [ASPEED_DEV_TIMER1] = 16, 61 }; 62 63 /* SSPINT 164 */ 64 static const int ast2700_ssp132_ssp164_intcmap[] = { 65 [ASPEED_DEV_UART0] = 7, 66 [ASPEED_DEV_UART1] = 8, 67 [ASPEED_DEV_UART2] = 9, 68 [ASPEED_DEV_UART3] = 10, 69 [ASPEED_DEV_UART5] = 11, 70 [ASPEED_DEV_UART6] = 12, 71 [ASPEED_DEV_UART7] = 13, 72 [ASPEED_DEV_UART8] = 14, 73 [ASPEED_DEV_UART9] = 15, 74 [ASPEED_DEV_UART10] = 16, 75 [ASPEED_DEV_UART11] = 17, 76 [ASPEED_DEV_UART12] = 18, 77 }; 78 79 struct nvic_intc_irq_info { 80 int irq; 81 int intc_idx; 82 int orgate_idx; 83 const int *ptr; 84 }; 85 86 static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = { 87 {160, 1, 0, NULL}, 88 {161, 1, 1, NULL}, 89 {162, 1, 2, NULL}, 90 {163, 1, 3, NULL}, 91 {164, 1, 4, ast2700_ssp132_ssp164_intcmap}, 92 {165, 1, 5, NULL}, 93 {166, 1, 6, NULL}, 94 {167, 1, 7, NULL}, 95 {168, 1, 8, NULL}, 96 {169, 1, 9, NULL}, 97 {128, 0, 1, NULL}, 98 {129, 0, 2, NULL}, 99 {130, 0, 3, NULL}, 100 {131, 0, 4, NULL}, 101 {132, 0, 5, ast2700_ssp132_ssp164_intcmap}, 102 {133, 0, 6, NULL}, 103 {134, 0, 7, NULL}, 104 {135, 0, 8, NULL}, 105 {136, 0, 9, NULL}, 106 }; 107 108 static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev) 109 { 110 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s); 111 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 112 113 int or_idx; 114 int idx; 115 int i; 116 117 for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) { 118 if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) { 119 assert(ast2700_ssp_intcmap[i].ptr); 120 or_idx = ast2700_ssp_intcmap[i].orgate_idx; 121 idx = ast2700_ssp_intcmap[i].intc_idx; 122 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), 123 ast2700_ssp_intcmap[i].ptr[dev]); 124 } 125 } 126 127 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); 128 } 129 130 static void aspeed_soc_ast27x0ssp_init(Object *obj) 131 { 132 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj); 133 AspeedSoCState *s = ASPEED_SOC(obj); 134 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 135 int i; 136 137 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); 138 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 139 140 for (i = 0; i < sc->uarts_num; i++) { 141 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 142 } 143 144 object_initialize_child(obj, "intc0", &a->intc[0], 145 TYPE_ASPEED_2700SSP_INTC); 146 object_initialize_child(obj, "intc1", &a->intc[1], 147 TYPE_ASPEED_2700SSP_INTCIO); 148 149 object_initialize_child(obj, "timerctrl", &s->timerctrl, 150 TYPE_UNIMPLEMENTED_DEVICE); 151 object_initialize_child(obj, "ipc0", &a->ipc[0], 152 TYPE_UNIMPLEMENTED_DEVICE); 153 object_initialize_child(obj, "ipc1", &a->ipc[1], 154 TYPE_UNIMPLEMENTED_DEVICE); 155 object_initialize_child(obj, "scuio", &a->scuio, 156 TYPE_UNIMPLEMENTED_DEVICE); 157 } 158 159 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp) 160 { 161 Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc); 162 AspeedSoCState *s = ASPEED_SOC(dev_soc); 163 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 164 DeviceState *armv7m; 165 g_autofree char *name = NULL; 166 int i; 167 168 if (!clock_has_source(s->sysclk)) { 169 error_setg(errp, "sysclk clock must be wired up by the board code"); 170 return; 171 } 172 173 /* AST27X0 SSP Core */ 174 armv7m = DEVICE(&a->armv7m); 175 qdev_prop_set_uint32(armv7m, "num-irq", 256); 176 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); 177 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 178 object_property_set_link(OBJECT(&a->armv7m), "memory", 179 OBJECT(s->memory), &error_abort); 180 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); 181 182 /* SDRAM */ 183 name = g_strdup_printf("aspeed.sdram-container.%d", 184 CPU(a->armv7m.cpu)->cpu_index); 185 186 if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name, 187 AST2700_SSP_SDRAM_SIZE, errp)) { 188 return; 189 } 190 /* SDRAM remap alias used by PSP to access SSP SDRAM */ 191 memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap2_alias); 192 memory_region_add_subregion(&s->dram_container, 193 memory_region_size(&a->sdram_remap2_alias), 194 &a->sdram_remap1_alias); 195 memory_region_add_subregion(s->memory, 196 sc->memmap[ASPEED_DEV_SDRAM], 197 &s->dram_container); 198 199 /* SRAM */ 200 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], 201 &a->sram_mr_alias); 202 203 /* SCU */ 204 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], 205 &a->scu_mr_alias); 206 207 /* INTC */ 208 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { 209 return; 210 } 211 212 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, 213 sc->memmap[ASPEED_DEV_INTC]); 214 215 /* INTCIO */ 216 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) { 217 return; 218 } 219 220 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0, 221 sc->memmap[ASPEED_DEV_INTCIO]); 222 223 /* irq source orgates -> INTC0 */ 224 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) { 225 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, 226 qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); 227 } 228 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) { 229 assert(i < ARRAY_SIZE(ast2700_ssp_intcmap)); 230 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, 231 qdev_get_gpio_in(DEVICE(&a->armv7m), 232 ast2700_ssp_intcmap[i].irq)); 233 } 234 /* irq source orgates -> INTCIO */ 235 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) { 236 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0, 237 qdev_get_gpio_in(DEVICE(&a->intc[1]), i)); 238 } 239 /* INTCIO -> INTC */ 240 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) { 241 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i, 242 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); 243 } 244 /* UART */ 245 if (!aspeed_soc_uart_realize(s, errp)) { 246 return; 247 } 248 249 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl), 250 "aspeed.timerctrl", 251 sc->memmap[ASPEED_DEV_TIMER1], 0x200); 252 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]), 253 "aspeed.ipc0", 254 sc->memmap[ASPEED_DEV_IPC0], 0x1000); 255 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]), 256 "aspeed.ipc1", 257 sc->memmap[ASPEED_DEV_IPC1], 0x1000); 258 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio), 259 "aspeed.scuio", 260 sc->memmap[ASPEED_DEV_SCUIO], 0x1000); 261 } 262 263 static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *data) 264 { 265 static const char * const valid_cpu_types[] = { 266 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */ 267 NULL 268 }; 269 DeviceClass *dc = DEVICE_CLASS(klass); 270 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 271 272 /* Reason: The Aspeed SoC can only be instantiated from a board */ 273 dc->user_creatable = false; 274 dc->realize = aspeed_soc_ast27x0ssp_realize; 275 276 sc->valid_cpu_types = valid_cpu_types; 277 sc->spis_num = 0; 278 sc->ehcis_num = 0; 279 sc->wdts_num = 0; 280 sc->macs_num = 0; 281 sc->uarts_num = 13; 282 sc->uarts_base = ASPEED_DEV_UART0; 283 sc->irqmap = aspeed_soc_ast27x0ssp_irqmap; 284 sc->memmap = aspeed_soc_ast27x0ssp_memmap; 285 sc->num_cpus = 1; 286 sc->get_irq = aspeed_soc_ast27x0ssp_get_irq; 287 } 288 289 static const TypeInfo aspeed_soc_ast27x0ssp_types[] = { 290 { 291 .name = TYPE_ASPEED27X0SSP_SOC, 292 .parent = TYPE_ASPEED_SOC, 293 .instance_size = sizeof(Aspeed27x0SSPSoCState), 294 .instance_init = aspeed_soc_ast27x0ssp_init, 295 .class_init = aspeed_soc_ast27x0ssp_class_init, 296 }, 297 }; 298 299 DEFINE_TYPES(aspeed_soc_ast27x0ssp_types) 300