xref: /openbmc/qemu/hw/arm/aspeed_ast2600.c (revision fa3673e4)
1 /*
2  * ASPEED SoC 2600 family
3  *
4  * Copyright (c) 2016-2019, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later.  See
7  * the COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/misc/unimp.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "qemu/module.h"
15 #include "qemu/error-report.h"
16 #include "hw/i2c/aspeed_i2c.h"
17 #include "net/net.h"
18 #include "sysemu/sysemu.h"
19 
20 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
21 #define ASPEED_SOC_DPMCU_SIZE       0x00040000
22 
23 static const hwaddr aspeed_soc_ast2600_memmap[] = {
24     [ASPEED_DEV_SPI_BOOT]  = ASPEED_SOC_SPI_BOOT_ADDR,
25     [ASPEED_DEV_SRAM]      = 0x10000000,
26     [ASPEED_DEV_DPMCU]     = 0x18000000,
27     /* 0x16000000     0x17FFFFFF : AHB BUS do LPC Bus bridge */
28     [ASPEED_DEV_IOMEM]     = 0x1E600000,
29     [ASPEED_DEV_PWM]       = 0x1E610000,
30     [ASPEED_DEV_FMC]       = 0x1E620000,
31     [ASPEED_DEV_SPI1]      = 0x1E630000,
32     [ASPEED_DEV_SPI2]      = 0x1E631000,
33     [ASPEED_DEV_EHCI1]     = 0x1E6A1000,
34     [ASPEED_DEV_EHCI2]     = 0x1E6A3000,
35     [ASPEED_DEV_MII1]      = 0x1E650000,
36     [ASPEED_DEV_MII2]      = 0x1E650008,
37     [ASPEED_DEV_MII3]      = 0x1E650010,
38     [ASPEED_DEV_MII4]      = 0x1E650018,
39     [ASPEED_DEV_ETH1]      = 0x1E660000,
40     [ASPEED_DEV_ETH3]      = 0x1E670000,
41     [ASPEED_DEV_ETH2]      = 0x1E680000,
42     [ASPEED_DEV_ETH4]      = 0x1E690000,
43     [ASPEED_DEV_VIC]       = 0x1E6C0000,
44     [ASPEED_DEV_HACE]      = 0x1E6D0000,
45     [ASPEED_DEV_SDMC]      = 0x1E6E0000,
46     [ASPEED_DEV_SCU]       = 0x1E6E2000,
47     [ASPEED_DEV_XDMA]      = 0x1E6E7000,
48     [ASPEED_DEV_ADC]       = 0x1E6E9000,
49     [ASPEED_DEV_DP]        = 0x1E6EB000,
50     [ASPEED_DEV_SBC]       = 0x1E6F2000,
51     [ASPEED_DEV_EMMC_BC]   = 0x1E6f5000,
52     [ASPEED_DEV_VIDEO]     = 0x1E700000,
53     [ASPEED_DEV_SDHCI]     = 0x1E740000,
54     [ASPEED_DEV_EMMC]      = 0x1E750000,
55     [ASPEED_DEV_GPIO]      = 0x1E780000,
56     [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
57     [ASPEED_DEV_RTC]       = 0x1E781000,
58     [ASPEED_DEV_TIMER1]    = 0x1E782000,
59     [ASPEED_DEV_WDT]       = 0x1E785000,
60     [ASPEED_DEV_LPC]       = 0x1E789000,
61     [ASPEED_DEV_IBT]       = 0x1E789140,
62     [ASPEED_DEV_I2C]       = 0x1E78A000,
63     [ASPEED_DEV_PECI]      = 0x1E78B000,
64     [ASPEED_DEV_UART1]     = 0x1E783000,
65     [ASPEED_DEV_UART2]     = 0x1E78D000,
66     [ASPEED_DEV_UART3]     = 0x1E78E000,
67     [ASPEED_DEV_UART4]     = 0x1E78F000,
68     [ASPEED_DEV_UART5]     = 0x1E784000,
69     [ASPEED_DEV_UART6]     = 0x1E790000,
70     [ASPEED_DEV_UART7]     = 0x1E790100,
71     [ASPEED_DEV_UART8]     = 0x1E790200,
72     [ASPEED_DEV_UART9]     = 0x1E790300,
73     [ASPEED_DEV_UART10]    = 0x1E790400,
74     [ASPEED_DEV_UART11]    = 0x1E790500,
75     [ASPEED_DEV_UART12]    = 0x1E790600,
76     [ASPEED_DEV_UART13]    = 0x1E790700,
77     [ASPEED_DEV_VUART]     = 0x1E787000,
78     [ASPEED_DEV_I3C]       = 0x1E7A0000,
79     [ASPEED_DEV_SDRAM]     = 0x80000000,
80 };
81 
82 #define ASPEED_A7MPCORE_ADDR 0x40460000
83 
84 #define AST2600_MAX_IRQ 197
85 
86 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
87 static const int aspeed_soc_ast2600_irqmap[] = {
88     [ASPEED_DEV_UART1]     = 47,
89     [ASPEED_DEV_UART2]     = 48,
90     [ASPEED_DEV_UART3]     = 49,
91     [ASPEED_DEV_UART4]     = 50,
92     [ASPEED_DEV_UART5]     = 8,
93     [ASPEED_DEV_UART6]     = 57,
94     [ASPEED_DEV_UART7]     = 58,
95     [ASPEED_DEV_UART8]     = 59,
96     [ASPEED_DEV_UART9]     = 60,
97     [ASPEED_DEV_UART10]    = 61,
98     [ASPEED_DEV_UART11]    = 62,
99     [ASPEED_DEV_UART12]    = 63,
100     [ASPEED_DEV_UART13]    = 64,
101     [ASPEED_DEV_VUART]     = 8,
102     [ASPEED_DEV_FMC]       = 39,
103     [ASPEED_DEV_SDMC]      = 0,
104     [ASPEED_DEV_SCU]       = 12,
105     [ASPEED_DEV_ADC]       = 78,
106     [ASPEED_DEV_XDMA]      = 6,
107     [ASPEED_DEV_SDHCI]     = 43,
108     [ASPEED_DEV_EHCI1]     = 5,
109     [ASPEED_DEV_EHCI2]     = 9,
110     [ASPEED_DEV_EMMC]      = 15,
111     [ASPEED_DEV_GPIO]      = 40,
112     [ASPEED_DEV_GPIO_1_8V] = 11,
113     [ASPEED_DEV_RTC]       = 13,
114     [ASPEED_DEV_TIMER1]    = 16,
115     [ASPEED_DEV_TIMER2]    = 17,
116     [ASPEED_DEV_TIMER3]    = 18,
117     [ASPEED_DEV_TIMER4]    = 19,
118     [ASPEED_DEV_TIMER5]    = 20,
119     [ASPEED_DEV_TIMER6]    = 21,
120     [ASPEED_DEV_TIMER7]    = 22,
121     [ASPEED_DEV_TIMER8]    = 23,
122     [ASPEED_DEV_WDT]       = 24,
123     [ASPEED_DEV_PWM]       = 44,
124     [ASPEED_DEV_LPC]       = 35,
125     [ASPEED_DEV_IBT]       = 143,
126     [ASPEED_DEV_I2C]       = 110,   /* 110 -> 125 */
127     [ASPEED_DEV_PECI]      = 38,
128     [ASPEED_DEV_ETH1]      = 2,
129     [ASPEED_DEV_ETH2]      = 3,
130     [ASPEED_DEV_HACE]      = 4,
131     [ASPEED_DEV_ETH3]      = 32,
132     [ASPEED_DEV_ETH4]      = 33,
133     [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
134     [ASPEED_DEV_DP]        = 62,
135     [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
136 };
137 
138 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
139 {
140     Aspeed2600SoCState *a = ASPEED2600_SOC(s);
141     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
142 
143     return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
144 }
145 
146 static void aspeed_soc_ast2600_init(Object *obj)
147 {
148     Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
149     AspeedSoCState *s = ASPEED_SOC(obj);
150     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
151     int i;
152     char socname[8];
153     char typename[64];
154 
155     if (sscanf(sc->name, "%7s", socname) != 1) {
156         g_assert_not_reached();
157     }
158 
159     for (i = 0; i < sc->num_cpus; i++) {
160         object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
161     }
162 
163     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
164     object_initialize_child(obj, "scu", &s->scu, typename);
165     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
166                          sc->silicon_rev);
167     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
168                               "hw-strap1");
169     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
170                               "hw-strap2");
171     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
172                               "hw-prot-key");
173 
174     object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
175                             TYPE_A15MPCORE_PRIV);
176 
177     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
178 
179     snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
180     object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
181 
182     snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
183     object_initialize_child(obj, "adc", &s->adc, typename);
184 
185     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
186     object_initialize_child(obj, "i2c", &s->i2c, typename);
187 
188     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
189 
190     snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
191     object_initialize_child(obj, "fmc", &s->fmc, typename);
192 
193     for (i = 0; i < sc->spis_num; i++) {
194         snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
195         object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
196     }
197 
198     for (i = 0; i < sc->ehcis_num; i++) {
199         object_initialize_child(obj, "ehci[*]", &s->ehci[i],
200                                 TYPE_PLATFORM_EHCI);
201     }
202 
203     snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
204     object_initialize_child(obj, "sdmc", &s->sdmc, typename);
205     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
206                               "ram-size");
207 
208     for (i = 0; i < sc->wdts_num; i++) {
209         snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
210         object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
211     }
212 
213     for (i = 0; i < sc->macs_num; i++) {
214         object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
215                                 TYPE_FTGMAC100);
216 
217         object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
218     }
219 
220     for (i = 0; i < sc->uarts_num; i++) {
221         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
222     }
223 
224     snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
225     object_initialize_child(obj, "xdma", &s->xdma, typename);
226 
227     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
228     object_initialize_child(obj, "gpio", &s->gpio, typename);
229 
230     snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
231     object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
232 
233     object_initialize_child(obj, "sd-controller", &s->sdhci,
234                             TYPE_ASPEED_SDHCI);
235 
236     object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
237 
238     /* Init sd card slot class here so that they're under the correct parent */
239     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
240         object_initialize_child(obj, "sd-controller.sdhci[*]",
241                                 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
242     }
243 
244     object_initialize_child(obj, "emmc-controller", &s->emmc,
245                             TYPE_ASPEED_SDHCI);
246 
247     object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
248 
249     object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
250                             TYPE_SYSBUS_SDHCI);
251 
252     object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
253 
254     snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
255     object_initialize_child(obj, "hace", &s->hace, typename);
256 
257     object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
258 
259     object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
260 
261     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
262     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
263     object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
264     object_initialize_child(obj, "emmc-boot-controller",
265                             &s->emmc_boot_controller,
266                             TYPE_UNIMPLEMENTED_DEVICE);
267 }
268 
269 /*
270  * ASPEED ast2600 has 0xf as cluster ID
271  *
272  * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
273  */
274 static uint64_t aspeed_calc_affinity(int cpu)
275 {
276     return (0xf << ARM_AFF1_SHIFT) | cpu;
277 }
278 
279 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
280 {
281     int i;
282     Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
283     AspeedSoCState *s = ASPEED_SOC(dev);
284     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
285     Error *err = NULL;
286     qemu_irq irq;
287     g_autofree char *sram_name = NULL;
288 
289     /* Default boot region (SPI memory or ROMs) */
290     memory_region_init(&s->spi_boot_container, OBJECT(s),
291                        "aspeed.spi_boot_container", 0x10000000);
292     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
293                                 &s->spi_boot_container);
294 
295     /* IO space */
296     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
297                                   sc->memmap[ASPEED_DEV_IOMEM],
298                                   ASPEED_SOC_IOMEM_SIZE);
299 
300     /* Video engine stub */
301     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
302                                   sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
303 
304     /* eMMC Boot Controller stub */
305     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
306                                   "aspeed.emmc-boot-controller",
307                                   sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
308 
309     /* CPU */
310     for (i = 0; i < sc->num_cpus; i++) {
311         if (sc->num_cpus > 1) {
312             object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
313                                     ASPEED_A7MPCORE_ADDR, &error_abort);
314         }
315         object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
316                                 aspeed_calc_affinity(i), &error_abort);
317 
318         object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
319                                 &error_abort);
320         object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
321                                 &error_abort);
322         object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
323                                 &error_abort);
324         object_property_set_link(OBJECT(&a->cpu[i]), "memory",
325                                  OBJECT(s->memory), &error_abort);
326 
327         if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
328             return;
329         }
330     }
331 
332     /* A7MPCORE */
333     object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
334                             &error_abort);
335     object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
336                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
337                             &error_abort);
338 
339     sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
340     aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
341 
342     for (i = 0; i < sc->num_cpus; i++) {
343         SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
344         DeviceState  *d   = DEVICE(&a->cpu[i]);
345 
346         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
347         sysbus_connect_irq(sbd, i, irq);
348         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
349         sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
350         irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
351         sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
352         irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
353         sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
354     }
355 
356     /* SRAM */
357     sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
358     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
359     if (err) {
360         error_propagate(errp, err);
361         return;
362     }
363     memory_region_add_subregion(s->memory,
364                                 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
365 
366     /* DPMCU */
367     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
368                                   sc->memmap[ASPEED_DEV_DPMCU],
369                                   ASPEED_SOC_DPMCU_SIZE);
370 
371     /* SCU */
372     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
373         return;
374     }
375     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
376 
377     /* RTC */
378     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
379         return;
380     }
381     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
382     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
383                        aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
384 
385     /* Timer */
386     object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
387                              &error_abort);
388     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
389         return;
390     }
391     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
392                     sc->memmap[ASPEED_DEV_TIMER1]);
393     for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
394         irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
395         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
396     }
397 
398     /* ADC */
399     if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
400         return;
401     }
402     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
403     sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
404                        aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
405 
406     /* UART */
407     if (!aspeed_soc_uart_realize(s, errp)) {
408         return;
409     }
410 
411     /* I2C */
412     object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
413                              &error_abort);
414     if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
415         return;
416     }
417     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
418     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
419         irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
420                                sc->irqmap[ASPEED_DEV_I2C] + i);
421         /* The AST2600 I2C controller has one IRQ per bus. */
422         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
423     }
424 
425     /* PECI */
426     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
427         return;
428     }
429     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
430                     sc->memmap[ASPEED_DEV_PECI]);
431     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
432                        aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
433 
434     /* FMC, The number of CS is set at the board level */
435     object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
436                              &error_abort);
437     if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
438         return;
439     }
440     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
441     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
442                     ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
443     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
444                        aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
445 
446     /* Set up an alias on the FMC CE0 region (boot default) */
447     MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
448     memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
449                              fmc0_mmio, 0, memory_region_size(fmc0_mmio));
450     memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
451 
452     /* SPI */
453     for (i = 0; i < sc->spis_num; i++) {
454         object_property_set_link(OBJECT(&s->spi[i]), "dram",
455                                  OBJECT(s->dram_mr), &error_abort);
456         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
457             return;
458         }
459         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
460                         sc->memmap[ASPEED_DEV_SPI1 + i]);
461         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
462                         ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
463     }
464 
465     /* EHCI */
466     for (i = 0; i < sc->ehcis_num; i++) {
467         if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
468             return;
469         }
470         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
471                         sc->memmap[ASPEED_DEV_EHCI1 + i]);
472         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
473                            aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
474     }
475 
476     /* SDMC - SDRAM Memory Controller */
477     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
478         return;
479     }
480     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
481                     sc->memmap[ASPEED_DEV_SDMC]);
482 
483     /* Watch dog */
484     for (i = 0; i < sc->wdts_num; i++) {
485         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
486         hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
487 
488         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
489                                  &error_abort);
490         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
491             return;
492         }
493         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
494     }
495 
496     /* RAM */
497     if (!aspeed_soc_dram_init(s, errp)) {
498         return;
499     }
500 
501     /* Net */
502     for (i = 0; i < sc->macs_num; i++) {
503         object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
504                                  &error_abort);
505         if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
506             return;
507         }
508         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
509                         sc->memmap[ASPEED_DEV_ETH1 + i]);
510         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
511                            aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
512 
513         object_property_set_link(OBJECT(&s->mii[i]), "nic",
514                                  OBJECT(&s->ftgmac100[i]), &error_abort);
515         if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
516             return;
517         }
518 
519         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
520                         sc->memmap[ASPEED_DEV_MII1 + i]);
521     }
522 
523     /* XDMA */
524     if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
525         return;
526     }
527     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
528                     sc->memmap[ASPEED_DEV_XDMA]);
529     sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
530                        aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
531 
532     /* GPIO */
533     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
534         return;
535     }
536     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
537     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
538                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
539 
540     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
541         return;
542     }
543     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
544                     sc->memmap[ASPEED_DEV_GPIO_1_8V]);
545     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
546                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
547 
548     /* SDHCI */
549     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
550         return;
551     }
552     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
553                     sc->memmap[ASPEED_DEV_SDHCI]);
554     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
555                        aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
556 
557     /* eMMC */
558     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
559         return;
560     }
561     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
562                     sc->memmap[ASPEED_DEV_EMMC]);
563     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
564                        aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
565 
566     /* LPC */
567     if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
568         return;
569     }
570     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
571 
572     /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
573     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
574                        aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
575 
576     /*
577      * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
578      *
579      * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
580      * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
581      * shared across the subdevices, and the shared IRQ output to the VIC is at
582      * offset 0.
583      */
584     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
585                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
586                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
587 
588     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
589                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
590                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
591 
592     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
593                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
594                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
595 
596     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
597                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
598                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
599 
600     /* HACE */
601     object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
602                              &error_abort);
603     if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
604         return;
605     }
606     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
607                     sc->memmap[ASPEED_DEV_HACE]);
608     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
609                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
610 
611     /* I3C */
612     if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
613         return;
614     }
615     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
616     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
617         irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
618                                sc->irqmap[ASPEED_DEV_I3C] + i);
619         /* The AST2600 I3C controller has one IRQ per bus. */
620         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
621     }
622 
623     /* Secure Boot Controller */
624     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
625         return;
626     }
627     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
628 }
629 
630 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
631 {
632     DeviceClass *dc = DEVICE_CLASS(oc);
633     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
634 
635     dc->realize      = aspeed_soc_ast2600_realize;
636 
637     sc->name         = "ast2600-a3";
638     sc->cpu_type     = ARM_CPU_TYPE_NAME("cortex-a7");
639     sc->silicon_rev  = AST2600_A3_SILICON_REV;
640     sc->sram_size    = 0x16400;
641     sc->spis_num     = 2;
642     sc->ehcis_num    = 2;
643     sc->wdts_num     = 4;
644     sc->macs_num     = 4;
645     sc->uarts_num    = 13;
646     sc->irqmap       = aspeed_soc_ast2600_irqmap;
647     sc->memmap       = aspeed_soc_ast2600_memmap;
648     sc->num_cpus     = 2;
649     sc->get_irq      = aspeed_soc_ast2600_get_irq;
650 }
651 
652 static const TypeInfo aspeed_soc_ast2600_types[] = {
653     {
654         .name           = TYPE_ASPEED2600_SOC,
655         .parent         = TYPE_ASPEED_SOC,
656         .instance_size  = sizeof(Aspeed2600SoCState),
657         .abstract       = true,
658     }, {
659         .name           = "ast2600-a3",
660         .parent         = TYPE_ASPEED2600_SOC,
661         .instance_init  = aspeed_soc_ast2600_init,
662         .class_init     = aspeed_soc_ast2600_class_init,
663     },
664 };
665 
666 DEFINE_TYPES(aspeed_soc_ast2600_types)
667