1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 object_initialize_child(obj, "scu", &s->scu, typename); 135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 136 sc->silicon_rev); 137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 138 "hw-strap1"); 139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 140 "hw-strap2"); 141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 142 "hw-prot-key"); 143 144 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 145 TYPE_A15MPCORE_PRIV); 146 147 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 148 149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 150 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 151 152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 153 object_initialize_child(obj, "i2c", &s->i2c, typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 156 object_initialize_child(obj, "fmc", &s->fmc, typename); 157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 158 159 for (i = 0; i < sc->spis_num; i++) { 160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 161 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 162 } 163 164 for (i = 0; i < sc->ehcis_num; i++) { 165 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 166 TYPE_PLATFORM_EHCI); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 171 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 172 "ram-size"); 173 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 174 "max-ram-size"); 175 176 for (i = 0; i < sc->wdts_num; i++) { 177 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 178 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 179 } 180 181 for (i = 0; i < sc->macs_num; i++) { 182 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 183 TYPE_FTGMAC100); 184 185 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 186 } 187 188 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 191 object_initialize_child(obj, "gpio", &s->gpio, typename); 192 193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 195 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 TYPE_ASPEED_SDHCI); 198 199 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 200 201 /* Init sd card slot class here so that they're under the correct parent */ 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 203 object_initialize_child(obj, "sd-controller.sdhci[*]", 204 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 205 } 206 207 object_initialize_child(obj, "emmc-controller", &s->emmc, 208 TYPE_ASPEED_SDHCI); 209 210 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 211 212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 213 TYPE_SYSBUS_SDHCI); 214 } 215 216 /* 217 * ASPEED ast2600 has 0xf as cluster ID 218 * 219 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 220 */ 221 static uint64_t aspeed_calc_affinity(int cpu) 222 { 223 return (0xf << ARM_AFF1_SHIFT) | cpu; 224 } 225 226 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 227 { 228 int i; 229 AspeedSoCState *s = ASPEED_SOC(dev); 230 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 231 Error *err = NULL, *local_err = NULL; 232 qemu_irq irq; 233 234 /* IO space */ 235 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 236 ASPEED_SOC_IOMEM_SIZE); 237 238 /* Video engine stub */ 239 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 240 0x1000); 241 242 /* CPU */ 243 for (i = 0; i < sc->num_cpus; i++) { 244 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 245 "psci-conduit", &error_abort); 246 if (sc->num_cpus > 1) { 247 object_property_set_int(OBJECT(&s->cpu[i]), 248 ASPEED_A7MPCORE_ADDR, 249 "reset-cbar", &error_abort); 250 } 251 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 252 "mp-affinity", &error_abort); 253 254 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 255 &error_abort); 256 257 /* 258 * TODO: the secondary CPUs are started and a boot helper 259 * is needed when using -kernel 260 */ 261 262 qdev_realize(DEVICE(&s->cpu[i]), NULL, &err); 263 if (err) { 264 error_propagate(errp, err); 265 return; 266 } 267 } 268 269 /* A7MPCORE */ 270 object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu", 271 &error_abort); 272 object_property_set_int(OBJECT(&s->a7mpcore), 273 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 274 "num-irq", &error_abort); 275 276 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 278 279 for (i = 0; i < sc->num_cpus; i++) { 280 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 281 DeviceState *d = DEVICE(qemu_get_cpu(i)); 282 283 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 284 sysbus_connect_irq(sbd, i, irq); 285 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 286 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 287 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 288 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 289 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 290 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 291 } 292 293 /* SRAM */ 294 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 295 sc->sram_size, &err); 296 if (err) { 297 error_propagate(errp, err); 298 return; 299 } 300 memory_region_add_subregion(get_system_memory(), 301 sc->memmap[ASPEED_SRAM], &s->sram); 302 303 /* SCU */ 304 sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err); 305 if (err) { 306 error_propagate(errp, err); 307 return; 308 } 309 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 310 311 /* RTC */ 312 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err); 313 if (err) { 314 error_propagate(errp, err); 315 return; 316 } 317 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 318 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 319 aspeed_soc_get_irq(s, ASPEED_RTC)); 320 321 /* Timer */ 322 object_property_set_link(OBJECT(&s->timerctrl), 323 OBJECT(&s->scu), "scu", &error_abort); 324 sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err); 325 if (err) { 326 error_propagate(errp, err); 327 return; 328 } 329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 330 sc->memmap[ASPEED_TIMER1]); 331 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 332 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 334 } 335 336 /* UART - attach an 8250 to the IO space as our UART5 */ 337 if (serial_hd(0)) { 338 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 339 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 340 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 341 } 342 343 /* I2C */ 344 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 345 if (err) { 346 error_propagate(errp, err); 347 return; 348 } 349 sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err); 350 if (err) { 351 error_propagate(errp, err); 352 return; 353 } 354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 355 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 356 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 357 sc->irqmap[ASPEED_I2C] + i); 358 /* 359 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 360 * IRQ (AST2400 and AST2500) and connect all bussses. 361 */ 362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 363 } 364 365 /* FMC, The number of CS is set at the board level */ 366 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 367 if (err) { 368 error_propagate(errp, err); 369 return; 370 } 371 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 372 "sdram-base", &err); 373 if (err) { 374 error_propagate(errp, err); 375 return; 376 } 377 sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err); 378 if (err) { 379 error_propagate(errp, err); 380 return; 381 } 382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 383 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 384 s->fmc.ctrl->flash_window_base); 385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 386 aspeed_soc_get_irq(s, ASPEED_FMC)); 387 388 /* SPI */ 389 for (i = 0; i < sc->spis_num; i++) { 390 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 391 "dram", &err); 392 if (err) { 393 error_propagate(errp, err); 394 return; 395 } 396 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 397 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err); 398 error_propagate(&err, local_err); 399 if (err) { 400 error_propagate(errp, err); 401 return; 402 } 403 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 404 sc->memmap[ASPEED_SPI1 + i]); 405 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 406 s->spi[i].ctrl->flash_window_base); 407 } 408 409 /* EHCI */ 410 for (i = 0; i < sc->ehcis_num; i++) { 411 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err); 412 if (err) { 413 error_propagate(errp, err); 414 return; 415 } 416 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 417 sc->memmap[ASPEED_EHCI1 + i]); 418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 419 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 420 } 421 422 /* SDMC - SDRAM Memory Controller */ 423 sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err); 424 if (err) { 425 error_propagate(errp, err); 426 return; 427 } 428 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 429 430 /* Watch dog */ 431 for (i = 0; i < sc->wdts_num; i++) { 432 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 433 434 object_property_set_link(OBJECT(&s->wdt[i]), 435 OBJECT(&s->scu), "scu", &error_abort); 436 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err); 437 if (err) { 438 error_propagate(errp, err); 439 return; 440 } 441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 442 sc->memmap[ASPEED_WDT] + i * awc->offset); 443 } 444 445 /* Net */ 446 for (i = 0; i < sc->macs_num; i++) { 447 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 448 &err); 449 sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err); 450 error_propagate(&err, local_err); 451 if (err) { 452 error_propagate(errp, err); 453 return; 454 } 455 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 456 sc->memmap[ASPEED_ETH1 + i]); 457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 458 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 459 460 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 461 "nic", &error_abort); 462 sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err); 463 if (err) { 464 error_propagate(errp, err); 465 return; 466 } 467 468 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 469 sc->memmap[ASPEED_MII1 + i]); 470 } 471 472 /* XDMA */ 473 sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err); 474 if (err) { 475 error_propagate(errp, err); 476 return; 477 } 478 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 479 sc->memmap[ASPEED_XDMA]); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 481 aspeed_soc_get_irq(s, ASPEED_XDMA)); 482 483 /* GPIO */ 484 sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err); 485 if (err) { 486 error_propagate(errp, err); 487 return; 488 } 489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 491 aspeed_soc_get_irq(s, ASPEED_GPIO)); 492 493 sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err); 494 if (err) { 495 error_propagate(errp, err); 496 return; 497 } 498 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 499 sc->memmap[ASPEED_GPIO_1_8V]); 500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 501 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 502 503 /* SDHCI */ 504 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err); 505 if (err) { 506 error_propagate(errp, err); 507 return; 508 } 509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 510 sc->memmap[ASPEED_SDHCI]); 511 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 512 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 513 514 /* eMMC */ 515 sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err); 516 if (err) { 517 error_propagate(errp, err); 518 return; 519 } 520 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 521 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 522 aspeed_soc_get_irq(s, ASPEED_EMMC)); 523 } 524 525 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 526 { 527 DeviceClass *dc = DEVICE_CLASS(oc); 528 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 529 530 dc->realize = aspeed_soc_ast2600_realize; 531 532 sc->name = "ast2600-a1"; 533 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 534 sc->silicon_rev = AST2600_A1_SILICON_REV; 535 sc->sram_size = 0x10000; 536 sc->spis_num = 2; 537 sc->ehcis_num = 2; 538 sc->wdts_num = 4; 539 sc->macs_num = 4; 540 sc->irqmap = aspeed_soc_ast2600_irqmap; 541 sc->memmap = aspeed_soc_ast2600_memmap; 542 sc->num_cpus = 2; 543 } 544 545 static const TypeInfo aspeed_soc_ast2600_type_info = { 546 .name = "ast2600-a1", 547 .parent = TYPE_ASPEED_SOC, 548 .instance_size = sizeof(AspeedSoCState), 549 .instance_init = aspeed_soc_ast2600_init, 550 .class_init = aspeed_soc_ast2600_class_init, 551 .class_size = sizeof(AspeedSoCClass), 552 }; 553 554 static void aspeed_soc_register_types(void) 555 { 556 type_register_static(&aspeed_soc_ast2600_type_info); 557 }; 558 559 type_init(aspeed_soc_register_types) 560