1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 [ASPEED_DEV_DPMCU] = 0x18000000, 27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 28 [ASPEED_DEV_IOMEM] = 0x1E600000, 29 [ASPEED_DEV_PWM] = 0x1E610000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_SPI2] = 0x1E631000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 35 [ASPEED_DEV_MII1] = 0x1E650000, 36 [ASPEED_DEV_MII2] = 0x1E650008, 37 [ASPEED_DEV_MII3] = 0x1E650010, 38 [ASPEED_DEV_MII4] = 0x1E650018, 39 [ASPEED_DEV_ETH1] = 0x1E660000, 40 [ASPEED_DEV_ETH3] = 0x1E670000, 41 [ASPEED_DEV_ETH2] = 0x1E680000, 42 [ASPEED_DEV_ETH4] = 0x1E690000, 43 [ASPEED_DEV_VIC] = 0x1E6C0000, 44 [ASPEED_DEV_HACE] = 0x1E6D0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_DP] = 0x1E6EB000, 50 [ASPEED_DEV_SBC] = 0x1E6F2000, 51 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 52 [ASPEED_DEV_VIDEO] = 0x1E700000, 53 [ASPEED_DEV_SDHCI] = 0x1E740000, 54 [ASPEED_DEV_EMMC] = 0x1E750000, 55 [ASPEED_DEV_GPIO] = 0x1E780000, 56 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 57 [ASPEED_DEV_RTC] = 0x1E781000, 58 [ASPEED_DEV_TIMER1] = 0x1E782000, 59 [ASPEED_DEV_WDT] = 0x1E785000, 60 [ASPEED_DEV_LPC] = 0x1E789000, 61 [ASPEED_DEV_IBT] = 0x1E789140, 62 [ASPEED_DEV_I2C] = 0x1E78A000, 63 [ASPEED_DEV_UART1] = 0x1E783000, 64 [ASPEED_DEV_UART5] = 0x1E784000, 65 [ASPEED_DEV_VUART] = 0x1E787000, 66 [ASPEED_DEV_I3C] = 0x1E7A0000, 67 [ASPEED_DEV_SDRAM] = 0x80000000, 68 }; 69 70 #define ASPEED_A7MPCORE_ADDR 0x40460000 71 72 #define AST2600_MAX_IRQ 197 73 74 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 75 static const int aspeed_soc_ast2600_irqmap[] = { 76 [ASPEED_DEV_UART1] = 47, 77 [ASPEED_DEV_UART2] = 48, 78 [ASPEED_DEV_UART3] = 49, 79 [ASPEED_DEV_UART4] = 50, 80 [ASPEED_DEV_UART5] = 8, 81 [ASPEED_DEV_VUART] = 8, 82 [ASPEED_DEV_FMC] = 39, 83 [ASPEED_DEV_SDMC] = 0, 84 [ASPEED_DEV_SCU] = 12, 85 [ASPEED_DEV_ADC] = 78, 86 [ASPEED_DEV_XDMA] = 6, 87 [ASPEED_DEV_SDHCI] = 43, 88 [ASPEED_DEV_EHCI1] = 5, 89 [ASPEED_DEV_EHCI2] = 9, 90 [ASPEED_DEV_EMMC] = 15, 91 [ASPEED_DEV_GPIO] = 40, 92 [ASPEED_DEV_GPIO_1_8V] = 11, 93 [ASPEED_DEV_RTC] = 13, 94 [ASPEED_DEV_TIMER1] = 16, 95 [ASPEED_DEV_TIMER2] = 17, 96 [ASPEED_DEV_TIMER3] = 18, 97 [ASPEED_DEV_TIMER4] = 19, 98 [ASPEED_DEV_TIMER5] = 20, 99 [ASPEED_DEV_TIMER6] = 21, 100 [ASPEED_DEV_TIMER7] = 22, 101 [ASPEED_DEV_TIMER8] = 23, 102 [ASPEED_DEV_WDT] = 24, 103 [ASPEED_DEV_PWM] = 44, 104 [ASPEED_DEV_LPC] = 35, 105 [ASPEED_DEV_IBT] = 143, 106 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 107 [ASPEED_DEV_ETH1] = 2, 108 [ASPEED_DEV_ETH2] = 3, 109 [ASPEED_DEV_HACE] = 4, 110 [ASPEED_DEV_ETH3] = 32, 111 [ASPEED_DEV_ETH4] = 33, 112 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 113 [ASPEED_DEV_DP] = 62, 114 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 115 }; 116 117 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 118 { 119 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 120 121 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 122 } 123 124 static void aspeed_soc_ast2600_init(Object *obj) 125 { 126 AspeedSoCState *s = ASPEED_SOC(obj); 127 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 128 int i; 129 char socname[8]; 130 char typename[64]; 131 132 if (sscanf(sc->name, "%7s", socname) != 1) { 133 g_assert_not_reached(); 134 } 135 136 for (i = 0; i < sc->num_cpus; i++) { 137 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 138 } 139 140 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 141 object_initialize_child(obj, "scu", &s->scu, typename); 142 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 143 sc->silicon_rev); 144 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 145 "hw-strap1"); 146 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 147 "hw-strap2"); 148 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 149 "hw-prot-key"); 150 151 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 152 TYPE_A15MPCORE_PRIV); 153 154 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 155 156 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 157 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 158 159 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 160 object_initialize_child(obj, "adc", &s->adc, typename); 161 162 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 163 object_initialize_child(obj, "i2c", &s->i2c, typename); 164 165 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 166 object_initialize_child(obj, "fmc", &s->fmc, typename); 167 168 for (i = 0; i < sc->spis_num; i++) { 169 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 170 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 171 } 172 173 for (i = 0; i < sc->ehcis_num; i++) { 174 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 175 TYPE_PLATFORM_EHCI); 176 } 177 178 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 179 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 180 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 181 "ram-size"); 182 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 183 "max-ram-size"); 184 185 for (i = 0; i < sc->wdts_num; i++) { 186 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 187 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 188 } 189 190 for (i = 0; i < sc->macs_num; i++) { 191 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 192 TYPE_FTGMAC100); 193 194 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 195 } 196 197 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 198 object_initialize_child(obj, "xdma", &s->xdma, typename); 199 200 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 201 object_initialize_child(obj, "gpio", &s->gpio, typename); 202 203 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 204 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 205 206 object_initialize_child(obj, "sd-controller", &s->sdhci, 207 TYPE_ASPEED_SDHCI); 208 209 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 210 211 /* Init sd card slot class here so that they're under the correct parent */ 212 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 213 object_initialize_child(obj, "sd-controller.sdhci[*]", 214 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 215 } 216 217 object_initialize_child(obj, "emmc-controller", &s->emmc, 218 TYPE_ASPEED_SDHCI); 219 220 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 221 222 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 223 TYPE_SYSBUS_SDHCI); 224 225 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 226 227 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 228 object_initialize_child(obj, "hace", &s->hace, typename); 229 230 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 231 232 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 233 } 234 235 /* 236 * ASPEED ast2600 has 0xf as cluster ID 237 * 238 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 239 */ 240 static uint64_t aspeed_calc_affinity(int cpu) 241 { 242 return (0xf << ARM_AFF1_SHIFT) | cpu; 243 } 244 245 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 246 { 247 int i; 248 AspeedSoCState *s = ASPEED_SOC(dev); 249 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 250 Error *err = NULL; 251 qemu_irq irq; 252 253 /* IO space */ 254 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 255 ASPEED_SOC_IOMEM_SIZE); 256 257 /* Video engine stub */ 258 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 259 0x1000); 260 261 /* eMMC Boot Controller stub */ 262 create_unimplemented_device("aspeed.emmc-boot-controller", 263 sc->memmap[ASPEED_DEV_EMMC_BC], 264 0x1000); 265 266 /* CPU */ 267 for (i = 0; i < sc->num_cpus; i++) { 268 if (sc->num_cpus > 1) { 269 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 270 ASPEED_A7MPCORE_ADDR, &error_abort); 271 } 272 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 273 aspeed_calc_affinity(i), &error_abort); 274 275 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 276 &error_abort); 277 278 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 279 return; 280 } 281 } 282 283 /* A7MPCORE */ 284 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 285 &error_abort); 286 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 287 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 288 &error_abort); 289 290 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 292 293 for (i = 0; i < sc->num_cpus; i++) { 294 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 295 DeviceState *d = DEVICE(qemu_get_cpu(i)); 296 297 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 298 sysbus_connect_irq(sbd, i, irq); 299 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 300 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 301 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 302 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 303 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 304 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 305 } 306 307 /* SRAM */ 308 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 309 sc->sram_size, &err); 310 if (err) { 311 error_propagate(errp, err); 312 return; 313 } 314 memory_region_add_subregion(get_system_memory(), 315 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 316 317 /* DPMCU */ 318 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 319 ASPEED_SOC_DPMCU_SIZE); 320 321 /* SCU */ 322 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 323 return; 324 } 325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 326 327 /* RTC */ 328 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 329 return; 330 } 331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 332 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 333 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 334 335 /* Timer */ 336 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 337 &error_abort); 338 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 339 return; 340 } 341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 342 sc->memmap[ASPEED_DEV_TIMER1]); 343 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 344 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 346 } 347 348 /* ADC */ 349 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 350 return; 351 } 352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 354 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 355 356 /* UART - attach an 8250 to the IO space as our UART */ 357 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 358 aspeed_soc_get_irq(s, s->uart_default), 38400, 359 serial_hd(0), DEVICE_LITTLE_ENDIAN); 360 361 /* I2C */ 362 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 363 &error_abort); 364 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 365 return; 366 } 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 368 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 369 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 370 sc->irqmap[ASPEED_DEV_I2C] + i); 371 /* The AST2600 I2C controller has one IRQ per bus. */ 372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 373 } 374 375 /* FMC, The number of CS is set at the board level */ 376 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 377 &error_abort); 378 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 379 return; 380 } 381 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 383 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 384 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 385 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 386 387 /* SPI */ 388 for (i = 0; i < sc->spis_num; i++) { 389 object_property_set_link(OBJECT(&s->spi[i]), "dram", 390 OBJECT(s->dram_mr), &error_abort); 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 392 return; 393 } 394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 395 sc->memmap[ASPEED_DEV_SPI1 + i]); 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 397 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 398 } 399 400 /* EHCI */ 401 for (i = 0; i < sc->ehcis_num; i++) { 402 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 403 return; 404 } 405 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 406 sc->memmap[ASPEED_DEV_EHCI1 + i]); 407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 408 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 409 } 410 411 /* SDMC - SDRAM Memory Controller */ 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 413 return; 414 } 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 416 417 /* Watch dog */ 418 for (i = 0; i < sc->wdts_num; i++) { 419 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 420 421 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 422 &error_abort); 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 424 return; 425 } 426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 427 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 428 } 429 430 /* Net */ 431 for (i = 0; i < sc->macs_num; i++) { 432 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 433 &error_abort); 434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 435 return; 436 } 437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 438 sc->memmap[ASPEED_DEV_ETH1 + i]); 439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 440 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 441 442 object_property_set_link(OBJECT(&s->mii[i]), "nic", 443 OBJECT(&s->ftgmac100[i]), &error_abort); 444 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 445 return; 446 } 447 448 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 449 sc->memmap[ASPEED_DEV_MII1 + i]); 450 } 451 452 /* XDMA */ 453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 454 return; 455 } 456 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 457 sc->memmap[ASPEED_DEV_XDMA]); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 459 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 460 461 /* GPIO */ 462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 463 return; 464 } 465 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 467 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 468 469 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 470 return; 471 } 472 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 473 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 475 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 476 477 /* SDHCI */ 478 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 479 return; 480 } 481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 482 sc->memmap[ASPEED_DEV_SDHCI]); 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 484 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 485 486 /* eMMC */ 487 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 488 return; 489 } 490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 492 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 493 494 /* LPC */ 495 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 496 return; 497 } 498 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 499 500 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 502 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 503 504 /* 505 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 506 * 507 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 508 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 509 * shared across the subdevices, and the shared IRQ output to the VIC is at 510 * offset 0. 511 */ 512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 513 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 514 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 515 516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 517 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 518 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 519 520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 521 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 522 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 523 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 525 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 526 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 527 528 /* HACE */ 529 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 530 &error_abort); 531 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 532 return; 533 } 534 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 535 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 536 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 537 538 /* I3C */ 539 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 540 return; 541 } 542 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 543 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 544 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 545 sc->irqmap[ASPEED_DEV_I3C] + i); 546 /* The AST2600 I3C controller has one IRQ per bus. */ 547 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 548 } 549 550 /* Secure Boot Controller */ 551 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 552 return; 553 } 554 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 555 } 556 557 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 558 { 559 DeviceClass *dc = DEVICE_CLASS(oc); 560 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 561 562 dc->realize = aspeed_soc_ast2600_realize; 563 564 sc->name = "ast2600-a3"; 565 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 566 sc->silicon_rev = AST2600_A3_SILICON_REV; 567 sc->sram_size = 0x16400; 568 sc->spis_num = 2; 569 sc->ehcis_num = 2; 570 sc->wdts_num = 4; 571 sc->macs_num = 4; 572 sc->irqmap = aspeed_soc_ast2600_irqmap; 573 sc->memmap = aspeed_soc_ast2600_memmap; 574 sc->num_cpus = 2; 575 } 576 577 static const TypeInfo aspeed_soc_ast2600_type_info = { 578 .name = "ast2600-a3", 579 .parent = TYPE_ASPEED_SOC, 580 .instance_size = sizeof(AspeedSoCState), 581 .instance_init = aspeed_soc_ast2600_init, 582 .class_init = aspeed_soc_ast2600_class_init, 583 .class_size = sizeof(AspeedSoCClass), 584 }; 585 586 static void aspeed_soc_register_types(void) 587 { 588 type_register_static(&aspeed_soc_ast2600_type_info); 589 }; 590 591 type_init(aspeed_soc_register_types) 592