1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_MII1] = 0x1E650000, 35 [ASPEED_MII2] = 0x1E650008, 36 [ASPEED_MII3] = 0x1E650010, 37 [ASPEED_MII4] = 0x1E650018, 38 [ASPEED_ETH1] = 0x1E660000, 39 [ASPEED_ETH3] = 0x1E670000, 40 [ASPEED_ETH2] = 0x1E680000, 41 [ASPEED_ETH4] = 0x1E690000, 42 [ASPEED_VIC] = 0x1E6C0000, 43 [ASPEED_SDMC] = 0x1E6E0000, 44 [ASPEED_SCU] = 0x1E6E2000, 45 [ASPEED_XDMA] = 0x1E6E7000, 46 [ASPEED_ADC] = 0x1E6E9000, 47 [ASPEED_VIDEO] = 0x1E700000, 48 [ASPEED_SDHCI] = 0x1E740000, 49 [ASPEED_GPIO] = 0x1E780000, 50 [ASPEED_GPIO_1_8V] = 0x1E780800, 51 [ASPEED_RTC] = 0x1E781000, 52 [ASPEED_TIMER1] = 0x1E782000, 53 [ASPEED_WDT] = 0x1E785000, 54 [ASPEED_LPC] = 0x1E789000, 55 [ASPEED_IBT] = 0x1E789140, 56 [ASPEED_I2C] = 0x1E78A000, 57 [ASPEED_UART1] = 0x1E783000, 58 [ASPEED_UART5] = 0x1E784000, 59 [ASPEED_VUART] = 0x1E787000, 60 [ASPEED_SDRAM] = 0x80000000, 61 }; 62 63 #define ASPEED_A7MPCORE_ADDR 0x40460000 64 65 #define ASPEED_SOC_AST2600_MAX_IRQ 128 66 67 static const int aspeed_soc_ast2600_irqmap[] = { 68 [ASPEED_UART1] = 47, 69 [ASPEED_UART2] = 48, 70 [ASPEED_UART3] = 49, 71 [ASPEED_UART4] = 50, 72 [ASPEED_UART5] = 8, 73 [ASPEED_VUART] = 8, 74 [ASPEED_FMC] = 39, 75 [ASPEED_SDMC] = 0, 76 [ASPEED_SCU] = 12, 77 [ASPEED_ADC] = 78, 78 [ASPEED_XDMA] = 6, 79 [ASPEED_SDHCI] = 43, 80 [ASPEED_GPIO] = 40, 81 [ASPEED_GPIO_1_8V] = 11, 82 [ASPEED_RTC] = 13, 83 [ASPEED_TIMER1] = 16, 84 [ASPEED_TIMER2] = 17, 85 [ASPEED_TIMER3] = 18, 86 [ASPEED_TIMER4] = 19, 87 [ASPEED_TIMER5] = 20, 88 [ASPEED_TIMER6] = 21, 89 [ASPEED_TIMER7] = 22, 90 [ASPEED_TIMER8] = 23, 91 [ASPEED_WDT] = 24, 92 [ASPEED_PWM] = 44, 93 [ASPEED_LPC] = 35, 94 [ASPEED_IBT] = 35, /* LPC */ 95 [ASPEED_I2C] = 110, /* 110 -> 125 */ 96 [ASPEED_ETH1] = 2, 97 [ASPEED_ETH2] = 3, 98 [ASPEED_ETH3] = 32, 99 [ASPEED_ETH4] = 33, 100 101 }; 102 103 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 104 { 105 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 106 107 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 108 } 109 110 static void aspeed_soc_ast2600_init(Object *obj) 111 { 112 AspeedSoCState *s = ASPEED_SOC(obj); 113 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 114 int i; 115 char socname[8]; 116 char typename[64]; 117 118 if (sscanf(sc->name, "%7s", socname) != 1) { 119 g_assert_not_reached(); 120 } 121 122 for (i = 0; i < sc->num_cpus; i++) { 123 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 124 sizeof(s->cpu[i]), sc->cpu_type, 125 &error_abort, NULL); 126 } 127 128 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 129 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 130 typename); 131 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 132 sc->silicon_rev); 133 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 134 "hw-strap1", &error_abort); 135 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 136 "hw-strap2", &error_abort); 137 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 138 "hw-prot-key", &error_abort); 139 140 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 141 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 142 143 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 144 TYPE_ASPEED_RTC); 145 146 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 147 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 148 sizeof(s->timerctrl), typename); 149 object_property_add_const_link(OBJECT(&s->timerctrl), "scu", 150 OBJECT(&s->scu), &error_abort); 151 152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 153 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 154 typename); 155 156 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 157 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 158 typename); 159 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", 160 &error_abort); 161 object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", 162 &error_abort); 163 164 for (i = 0; i < sc->spis_num; i++) { 165 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 166 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 167 sizeof(s->spi[i]), typename); 168 } 169 170 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 171 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 172 typename); 173 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 174 "ram-size", &error_abort); 175 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 176 "max-ram-size", &error_abort); 177 178 for (i = 0; i < sc->wdts_num; i++) { 179 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 180 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 181 sizeof(s->wdt[i]), typename); 182 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu", 183 OBJECT(&s->scu), &error_abort); 184 } 185 186 for (i = 0; i < sc->macs_num; i++) { 187 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 188 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 189 190 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 191 TYPE_ASPEED_MII); 192 object_property_add_const_link(OBJECT(&s->mii[i]), "nic", 193 OBJECT(&s->ftgmac100[i]), 194 &error_abort); 195 } 196 197 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 198 TYPE_ASPEED_XDMA); 199 200 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 201 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 202 typename); 203 204 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 205 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 206 sizeof(s->gpio_1_8v), typename); 207 208 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci), 209 TYPE_ASPEED_SDHCI); 210 211 /* Init sd card slot class here so that they're under the correct parent */ 212 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 213 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]), 214 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 215 } 216 } 217 218 /* 219 * ASPEED ast2600 has 0xf as cluster ID 220 * 221 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 222 */ 223 static uint64_t aspeed_calc_affinity(int cpu) 224 { 225 return (0xf << ARM_AFF1_SHIFT) | cpu; 226 } 227 228 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 229 { 230 int i; 231 AspeedSoCState *s = ASPEED_SOC(dev); 232 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 233 Error *err = NULL, *local_err = NULL; 234 qemu_irq irq; 235 236 /* IO space */ 237 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 238 ASPEED_SOC_IOMEM_SIZE); 239 240 /* Video engine stub */ 241 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 242 0x1000); 243 244 if (s->num_cpus > sc->num_cpus) { 245 warn_report("%s: invalid number of CPUs %d, using default %d", 246 sc->name, s->num_cpus, sc->num_cpus); 247 s->num_cpus = sc->num_cpus; 248 } 249 250 /* CPU */ 251 for (i = 0; i < s->num_cpus; i++) { 252 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 253 "psci-conduit", &error_abort); 254 if (s->num_cpus > 1) { 255 object_property_set_int(OBJECT(&s->cpu[i]), 256 ASPEED_A7MPCORE_ADDR, 257 "reset-cbar", &error_abort); 258 } 259 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 260 "mp-affinity", &error_abort); 261 262 /* 263 * TODO: the secondary CPUs are started and a boot helper 264 * is needed when using -kernel 265 */ 266 267 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 268 if (err) { 269 error_propagate(errp, err); 270 return; 271 } 272 } 273 274 /* A7MPCORE */ 275 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", 276 &error_abort); 277 object_property_set_int(OBJECT(&s->a7mpcore), 278 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 279 "num-irq", &error_abort); 280 281 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 282 &error_abort); 283 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 284 285 for (i = 0; i < s->num_cpus; i++) { 286 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 287 DeviceState *d = DEVICE(qemu_get_cpu(i)); 288 289 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 290 sysbus_connect_irq(sbd, i, irq); 291 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 292 sysbus_connect_irq(sbd, i + s->num_cpus, irq); 293 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 294 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); 295 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 296 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); 297 } 298 299 /* SRAM */ 300 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 301 sc->sram_size, &err); 302 if (err) { 303 error_propagate(errp, err); 304 return; 305 } 306 memory_region_add_subregion(get_system_memory(), 307 sc->memmap[ASPEED_SRAM], &s->sram); 308 309 /* SCU */ 310 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 311 if (err) { 312 error_propagate(errp, err); 313 return; 314 } 315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 316 317 /* RTC */ 318 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 319 if (err) { 320 error_propagate(errp, err); 321 return; 322 } 323 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 325 aspeed_soc_get_irq(s, ASPEED_RTC)); 326 327 /* Timer */ 328 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 329 if (err) { 330 error_propagate(errp, err); 331 return; 332 } 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 334 sc->memmap[ASPEED_TIMER1]); 335 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 336 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 338 } 339 340 /* UART - attach an 8250 to the IO space as our UART5 */ 341 if (serial_hd(0)) { 342 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 343 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 344 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 345 } 346 347 /* I2C */ 348 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 349 if (err) { 350 error_propagate(errp, err); 351 return; 352 } 353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 354 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 355 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 356 sc->irqmap[ASPEED_I2C] + i); 357 /* 358 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 359 * IRQ (AST2400 and AST2500) and connect all bussses. 360 */ 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 362 } 363 364 /* FMC, The number of CS is set at the board level */ 365 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 366 "sdram-base", &err); 367 if (err) { 368 error_propagate(errp, err); 369 return; 370 } 371 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 372 if (err) { 373 error_propagate(errp, err); 374 return; 375 } 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 378 s->fmc.ctrl->flash_window_base); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 380 aspeed_soc_get_irq(s, ASPEED_FMC)); 381 382 /* SPI */ 383 for (i = 0; i < sc->spis_num; i++) { 384 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 385 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 386 &local_err); 387 error_propagate(&err, local_err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 393 sc->memmap[ASPEED_SPI1 + i]); 394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 395 s->spi[i].ctrl->flash_window_base); 396 } 397 398 /* SDMC - SDRAM Memory Controller */ 399 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 400 if (err) { 401 error_propagate(errp, err); 402 return; 403 } 404 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 405 406 /* Watch dog */ 407 for (i = 0; i < sc->wdts_num; i++) { 408 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 409 410 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 411 if (err) { 412 error_propagate(errp, err); 413 return; 414 } 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 416 sc->memmap[ASPEED_WDT] + i * awc->offset); 417 } 418 419 /* Net */ 420 for (i = 0; i < nb_nics && i < sc->macs_num; i++) { 421 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); 422 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 423 &err); 424 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 425 &local_err); 426 error_propagate(&err, local_err); 427 if (err) { 428 error_propagate(errp, err); 429 return; 430 } 431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 432 sc->memmap[ASPEED_ETH1 + i]); 433 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 434 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 435 436 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 437 &err); 438 if (err) { 439 error_propagate(errp, err); 440 return; 441 } 442 443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 444 sc->memmap[ASPEED_MII1 + i]); 445 } 446 447 /* XDMA */ 448 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 449 if (err) { 450 error_propagate(errp, err); 451 return; 452 } 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 454 sc->memmap[ASPEED_XDMA]); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 456 aspeed_soc_get_irq(s, ASPEED_XDMA)); 457 458 /* GPIO */ 459 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 460 if (err) { 461 error_propagate(errp, err); 462 return; 463 } 464 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 465 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 466 aspeed_soc_get_irq(s, ASPEED_GPIO)); 467 468 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 469 if (err) { 470 error_propagate(errp, err); 471 return; 472 } 473 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 474 sc->memmap[ASPEED_GPIO_1_8V]); 475 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 476 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 477 478 /* SDHCI */ 479 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 480 if (err) { 481 error_propagate(errp, err); 482 return; 483 } 484 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 485 sc->memmap[ASPEED_SDHCI]); 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 487 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 488 } 489 490 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 491 { 492 DeviceClass *dc = DEVICE_CLASS(oc); 493 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 494 495 dc->realize = aspeed_soc_ast2600_realize; 496 497 sc->name = "ast2600-a0"; 498 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 499 sc->silicon_rev = AST2600_A0_SILICON_REV; 500 sc->sram_size = 0x10000; 501 sc->spis_num = 2; 502 sc->wdts_num = 4; 503 sc->macs_num = 4; 504 sc->irqmap = aspeed_soc_ast2600_irqmap; 505 sc->memmap = aspeed_soc_ast2600_memmap; 506 sc->num_cpus = 2; 507 } 508 509 static const TypeInfo aspeed_soc_ast2600_type_info = { 510 .name = "ast2600-a0", 511 .parent = TYPE_ASPEED_SOC, 512 .instance_size = sizeof(AspeedSoCState), 513 .instance_init = aspeed_soc_ast2600_init, 514 .class_init = aspeed_soc_ast2600_class_init, 515 .class_size = sizeof(AspeedSoCClass), 516 }; 517 518 static void aspeed_soc_register_types(void) 519 { 520 type_register_static(&aspeed_soc_ast2600_type_info); 521 }; 522 523 type_init(aspeed_soc_register_types) 524