1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "system/system.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_MII1] = 0x1E650000, 37 [ASPEED_DEV_MII2] = 0x1E650008, 38 [ASPEED_DEV_MII3] = 0x1E650010, 39 [ASPEED_DEV_MII4] = 0x1E650018, 40 [ASPEED_DEV_ETH1] = 0x1E660000, 41 [ASPEED_DEV_ETH3] = 0x1E670000, 42 [ASPEED_DEV_ETH2] = 0x1E680000, 43 [ASPEED_DEV_ETH4] = 0x1E690000, 44 [ASPEED_DEV_VIC] = 0x1E6C0000, 45 [ASPEED_DEV_HACE] = 0x1E6D0000, 46 [ASPEED_DEV_SDMC] = 0x1E6E0000, 47 [ASPEED_DEV_SCU] = 0x1E6E2000, 48 [ASPEED_DEV_XDMA] = 0x1E6E7000, 49 [ASPEED_DEV_ADC] = 0x1E6E9000, 50 [ASPEED_DEV_DP] = 0x1E6EB000, 51 [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED200, 52 [ASPEED_DEV_SBC] = 0x1E6F2000, 53 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 54 [ASPEED_DEV_VIDEO] = 0x1E700000, 55 [ASPEED_DEV_SDHCI] = 0x1E740000, 56 [ASPEED_DEV_EMMC] = 0x1E750000, 57 [ASPEED_DEV_PCIE0] = 0x1E770000, 58 [ASPEED_DEV_GPIO] = 0x1E780000, 59 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 60 [ASPEED_DEV_RTC] = 0x1E781000, 61 [ASPEED_DEV_TIMER1] = 0x1E782000, 62 [ASPEED_DEV_WDT] = 0x1E785000, 63 [ASPEED_DEV_LPC] = 0x1E789000, 64 [ASPEED_DEV_IBT] = 0x1E789140, 65 [ASPEED_DEV_I2C] = 0x1E78A000, 66 [ASPEED_DEV_PECI] = 0x1E78B000, 67 [ASPEED_DEV_UART1] = 0x1E783000, 68 [ASPEED_DEV_UART2] = 0x1E78D000, 69 [ASPEED_DEV_UART3] = 0x1E78E000, 70 [ASPEED_DEV_UART4] = 0x1E78F000, 71 [ASPEED_DEV_UART5] = 0x1E784000, 72 [ASPEED_DEV_UART6] = 0x1E790000, 73 [ASPEED_DEV_UART7] = 0x1E790100, 74 [ASPEED_DEV_UART8] = 0x1E790200, 75 [ASPEED_DEV_UART9] = 0x1E790300, 76 [ASPEED_DEV_UART10] = 0x1E790400, 77 [ASPEED_DEV_UART11] = 0x1E790500, 78 [ASPEED_DEV_UART12] = 0x1E790600, 79 [ASPEED_DEV_UART13] = 0x1E790700, 80 [ASPEED_DEV_VUART] = 0x1E787000, 81 [ASPEED_DEV_FSI1] = 0x1E79B000, 82 [ASPEED_DEV_FSI2] = 0x1E79B100, 83 [ASPEED_DEV_I3C] = 0x1E7A0000, 84 [ASPEED_DEV_PCIE_MMIO1] = 0x70000000, 85 [ASPEED_DEV_SDRAM] = 0x80000000, 86 }; 87 88 #define ASPEED_A7MPCORE_ADDR 0x40460000 89 90 #define AST2600_MAX_IRQ 197 91 92 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 93 static const int aspeed_soc_ast2600_irqmap[] = { 94 [ASPEED_DEV_UART1] = 47, 95 [ASPEED_DEV_UART2] = 48, 96 [ASPEED_DEV_UART3] = 49, 97 [ASPEED_DEV_UART4] = 50, 98 [ASPEED_DEV_UART5] = 8, 99 [ASPEED_DEV_UART6] = 57, 100 [ASPEED_DEV_UART7] = 58, 101 [ASPEED_DEV_UART8] = 59, 102 [ASPEED_DEV_UART9] = 60, 103 [ASPEED_DEV_UART10] = 61, 104 [ASPEED_DEV_UART11] = 62, 105 [ASPEED_DEV_UART12] = 63, 106 [ASPEED_DEV_UART13] = 64, 107 [ASPEED_DEV_VUART] = 8, 108 [ASPEED_DEV_FMC] = 39, 109 [ASPEED_DEV_SDMC] = 0, 110 [ASPEED_DEV_SCU] = 12, 111 [ASPEED_DEV_ADC] = 78, 112 [ASPEED_DEV_XDMA] = 6, 113 [ASPEED_DEV_SDHCI] = 43, 114 [ASPEED_DEV_EHCI1] = 5, 115 [ASPEED_DEV_EHCI2] = 9, 116 [ASPEED_DEV_EMMC] = 15, 117 [ASPEED_DEV_GPIO] = 40, 118 [ASPEED_DEV_GPIO_1_8V] = 11, 119 [ASPEED_DEV_RTC] = 13, 120 [ASPEED_DEV_TIMER1] = 16, 121 [ASPEED_DEV_TIMER2] = 17, 122 [ASPEED_DEV_TIMER3] = 18, 123 [ASPEED_DEV_TIMER4] = 19, 124 [ASPEED_DEV_TIMER5] = 20, 125 [ASPEED_DEV_TIMER6] = 21, 126 [ASPEED_DEV_TIMER7] = 22, 127 [ASPEED_DEV_TIMER8] = 23, 128 [ASPEED_DEV_WDT] = 24, 129 [ASPEED_DEV_PWM] = 44, 130 [ASPEED_DEV_LPC] = 35, 131 [ASPEED_DEV_IBT] = 143, 132 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 133 [ASPEED_DEV_PCIE0] = 168, 134 [ASPEED_DEV_PECI] = 38, 135 [ASPEED_DEV_ETH1] = 2, 136 [ASPEED_DEV_ETH2] = 3, 137 [ASPEED_DEV_HACE] = 4, 138 [ASPEED_DEV_ETH3] = 32, 139 [ASPEED_DEV_ETH4] = 33, 140 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 141 [ASPEED_DEV_DP] = 62, 142 [ASPEED_DEV_FSI1] = 100, 143 [ASPEED_DEV_FSI2] = 101, 144 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 145 }; 146 147 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 148 { 149 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 150 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 151 152 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 153 } 154 155 static void aspeed_soc_ast2600_init(Object *obj) 156 { 157 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 158 AspeedSoCState *s = ASPEED_SOC(obj); 159 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 160 int i; 161 char socname[8]; 162 char typename[64]; 163 164 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 165 g_assert_not_reached(); 166 } 167 168 for (i = 0; i < sc->num_cpus; i++) { 169 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 170 aspeed_soc_cpu_type(sc)); 171 } 172 173 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 174 object_initialize_child(obj, "scu", &s->scu, typename); 175 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 176 sc->silicon_rev); 177 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 178 "hw-strap1"); 179 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 180 "hw-strap2"); 181 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 182 "hw-prot-key"); 183 184 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 185 TYPE_A15MPCORE_PRIV); 186 187 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 188 189 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 190 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 191 192 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 193 object_initialize_child(obj, "adc", &s->adc, typename); 194 195 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 196 object_initialize_child(obj, "i2c", &s->i2c, typename); 197 198 object_initialize_child(obj, "pcie-cfg", &s->pcie[0], TYPE_ASPEED_PCIE_CFG); 199 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[0], 200 TYPE_ASPEED_PCIE_PHY); 201 202 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 203 204 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 205 object_initialize_child(obj, "fmc", &s->fmc, typename); 206 207 for (i = 0; i < sc->spis_num; i++) { 208 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 209 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 210 } 211 212 for (i = 0; i < sc->ehcis_num; i++) { 213 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 214 TYPE_PLATFORM_EHCI); 215 } 216 217 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 218 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 219 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 220 "ram-size"); 221 222 for (i = 0; i < sc->wdts_num; i++) { 223 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 224 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 225 } 226 227 for (i = 0; i < sc->macs_num; i++) { 228 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 229 TYPE_FTGMAC100); 230 231 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 232 } 233 234 for (i = 0; i < sc->uarts_num; i++) { 235 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 236 } 237 238 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 239 object_initialize_child(obj, "xdma", &s->xdma, typename); 240 241 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 242 object_initialize_child(obj, "gpio", &s->gpio, typename); 243 244 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 245 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 246 247 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 248 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 249 250 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 251 252 /* Init sd card slot class here so that they're under the correct parent */ 253 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 254 object_initialize_child(obj, "sd-controller.sdhci[*]", 255 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 256 } 257 258 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 259 260 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 261 262 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 263 TYPE_SYSBUS_SDHCI); 264 265 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 266 267 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 268 object_initialize_child(obj, "hace", &s->hace, typename); 269 270 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 271 272 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); 273 274 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 275 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 276 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 277 object_initialize_child(obj, "emmc-boot-controller", 278 &s->emmc_boot_controller, 279 TYPE_UNIMPLEMENTED_DEVICE); 280 281 for (i = 0; i < ASPEED_FSI_NUM; i++) { 282 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 283 } 284 } 285 286 /* 287 * ASPEED ast2600 has 0xf as cluster ID 288 * 289 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 290 */ 291 static uint64_t aspeed_calc_affinity(int cpu) 292 { 293 return (0xf << ARM_AFF1_SHIFT) | cpu; 294 } 295 296 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 297 { 298 int i; 299 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 300 AspeedSoCState *s = ASPEED_SOC(dev); 301 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 302 qemu_irq irq; 303 g_autofree char *name = NULL; 304 MemoryRegion *mmio_alias; 305 MemoryRegion *mmio_mr; 306 307 /* Default boot region (SPI memory or ROMs) */ 308 memory_region_init(&s->spi_boot_container, OBJECT(s), 309 "aspeed.spi_boot_container", 0x10000000); 310 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 311 &s->spi_boot_container); 312 313 /* IO space */ 314 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 315 sc->memmap[ASPEED_DEV_IOMEM], 316 ASPEED_SOC_IOMEM_SIZE); 317 318 /* Video engine stub */ 319 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 320 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 321 322 /* eMMC Boot Controller stub */ 323 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 324 "aspeed.emmc-boot-controller", 325 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 326 327 /* CPU */ 328 for (i = 0; i < sc->num_cpus; i++) { 329 if (sc->num_cpus > 1) { 330 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 331 ASPEED_A7MPCORE_ADDR, &error_abort); 332 } 333 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 334 aspeed_calc_affinity(i), &error_abort); 335 336 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 337 &error_abort); 338 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 339 &error_abort); 340 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 341 &error_abort); 342 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 343 OBJECT(s->memory), &error_abort); 344 345 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 346 return; 347 } 348 } 349 350 /* A7MPCORE */ 351 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 352 &error_abort); 353 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 354 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 355 &error_abort); 356 357 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 358 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 359 360 for (i = 0; i < sc->num_cpus; i++) { 361 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 362 DeviceState *d = DEVICE(&a->cpu[i]); 363 364 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 365 sysbus_connect_irq(sbd, i, irq); 366 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 367 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 368 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 369 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 370 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 371 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 372 } 373 374 /* SRAM */ 375 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 376 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 377 errp)) { 378 return; 379 } 380 memory_region_add_subregion(s->memory, 381 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 382 383 /* DPMCU */ 384 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 385 sc->memmap[ASPEED_DEV_DPMCU], 386 ASPEED_SOC_DPMCU_SIZE); 387 388 /* SCU */ 389 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 390 return; 391 } 392 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 393 394 /* RTC */ 395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 396 return; 397 } 398 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 399 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 400 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 401 402 /* Timer */ 403 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 404 &error_abort); 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 406 return; 407 } 408 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 409 sc->memmap[ASPEED_DEV_TIMER1]); 410 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 411 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 413 } 414 415 /* ADC */ 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 417 return; 418 } 419 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 421 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 422 423 /* UART */ 424 if (!aspeed_soc_uart_realize(s, errp)) { 425 return; 426 } 427 428 /* I2C */ 429 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 430 &error_abort); 431 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 432 return; 433 } 434 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 435 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 436 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 437 sc->irqmap[ASPEED_DEV_I2C] + i); 438 /* The AST2600 I2C controller has one IRQ per bus. */ 439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 440 } 441 442 /* PECI */ 443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 444 return; 445 } 446 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 447 sc->memmap[ASPEED_DEV_PECI]); 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 449 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 450 451 /* 452 * PCIe Root Complex (RC) 453 * 454 * H2X register space (single block 0x00-0xFF): 455 * 0x00-0x7F : shared by RC_L (PCIe0) and RC_H (PCIe1) 456 * 0x80-0xBF : RC_L only 457 * 0xC0-0xFF : RC_H only 458 * 459 * Model scope / limitations: 460 * - Firmware supports RC_H only; this QEMU model does not support RC_L. 461 * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000] 462 * (aka MMIO1). 463 * 464 * Indexing convention (this model): 465 * - Expose a single logical instance at index 0. 466 * - pcie[0] -> hardware RC_H (PCIe1) 467 * - phy[0] -> hardware PHY1 468 * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000 469 * - RC_L / PCIe0 is not created and mapped. 470 */ 471 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { 472 return; 473 } 474 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, 475 sc->memmap[ASPEED_DEV_PCIE_PHY1]); 476 477 object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", 478 sc->memmap[ASPEED_DEV_SDRAM], 479 &error_abort); 480 object_property_set_link(OBJECT(&s->pcie[0]), "dram", OBJECT(s->dram_mr), 481 &error_abort); 482 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { 483 return; 484 } 485 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0, 486 sc->memmap[ASPEED_DEV_PCIE0]); 487 488 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 489 sc->irqmap[ASPEED_DEV_PCIE0]); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[0].rc), 0, irq); 491 492 name = g_strdup_printf("aspeed.pcie-mmio.0"); 493 494 mmio_alias = g_new0(MemoryRegion, 1); 495 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[0].rc), 1); 496 497 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[0].rc), name, 498 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1], 499 0x10000000); 500 memory_region_add_subregion(s->memory, 501 sc->memmap[ASPEED_DEV_PCIE_MMIO1], 502 mmio_alias); 503 504 /* FMC, The number of CS is set at the board level */ 505 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 506 &error_abort); 507 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 508 return; 509 } 510 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 511 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 512 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 514 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 515 516 /* Set up an alias on the FMC CE0 region (boot default) */ 517 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 518 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 519 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 520 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 521 522 /* SPI */ 523 for (i = 0; i < sc->spis_num; i++) { 524 object_property_set_link(OBJECT(&s->spi[i]), "dram", 525 OBJECT(s->dram_mr), &error_abort); 526 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 527 return; 528 } 529 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 530 sc->memmap[ASPEED_DEV_SPI1 + i]); 531 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 532 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 533 } 534 535 /* EHCI */ 536 for (i = 0; i < sc->ehcis_num; i++) { 537 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 538 return; 539 } 540 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 541 sc->memmap[ASPEED_DEV_EHCI1 + i]); 542 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 543 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 544 } 545 546 /* SDMC - SDRAM Memory Controller */ 547 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 548 return; 549 } 550 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 551 sc->memmap[ASPEED_DEV_SDMC]); 552 553 /* Watch dog */ 554 for (i = 0; i < sc->wdts_num; i++) { 555 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 556 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 557 558 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 559 &error_abort); 560 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 561 return; 562 } 563 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 564 } 565 566 /* RAM */ 567 if (!aspeed_soc_dram_init(s, errp)) { 568 return; 569 } 570 571 /* Net */ 572 for (i = 0; i < sc->macs_num; i++) { 573 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 574 &error_abort); 575 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 576 return; 577 } 578 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 579 sc->memmap[ASPEED_DEV_ETH1 + i]); 580 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 581 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 582 583 object_property_set_link(OBJECT(&s->mii[i]), "nic", 584 OBJECT(&s->ftgmac100[i]), &error_abort); 585 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 586 return; 587 } 588 589 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 590 sc->memmap[ASPEED_DEV_MII1 + i]); 591 } 592 593 /* XDMA */ 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 595 return; 596 } 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 598 sc->memmap[ASPEED_DEV_XDMA]); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 600 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 601 602 /* GPIO */ 603 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 604 return; 605 } 606 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 607 sc->memmap[ASPEED_DEV_GPIO]); 608 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 609 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 610 611 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 612 return; 613 } 614 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 615 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 616 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 617 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 618 619 /* SDHCI */ 620 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 621 return; 622 } 623 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 624 sc->memmap[ASPEED_DEV_SDHCI]); 625 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 626 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 627 628 /* eMMC */ 629 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 630 return; 631 } 632 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 633 sc->memmap[ASPEED_DEV_EMMC]); 634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 635 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 636 637 /* LPC */ 638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 639 return; 640 } 641 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 642 643 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 644 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 645 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 646 647 /* 648 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 649 * 650 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 651 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 652 * shared across the subdevices, and the shared IRQ output to the VIC is at 653 * offset 0. 654 */ 655 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 656 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 657 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 658 659 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 660 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 661 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 662 663 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 664 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 665 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 666 667 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 668 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 669 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 670 671 /* HACE */ 672 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 673 &error_abort); 674 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 675 return; 676 } 677 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 678 sc->memmap[ASPEED_DEV_HACE]); 679 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 680 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 681 682 /* I3C */ 683 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 684 return; 685 } 686 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 687 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 688 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 689 sc->irqmap[ASPEED_DEV_I3C] + i); 690 /* The AST2600 I3C controller has one IRQ per bus. */ 691 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 692 } 693 694 /* Secure Boot Controller */ 695 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 696 return; 697 } 698 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 699 700 /* FSI */ 701 for (i = 0; i < ASPEED_FSI_NUM; i++) { 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 703 return; 704 } 705 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 706 sc->memmap[ASPEED_DEV_FSI1 + i]); 707 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 708 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 709 } 710 } 711 712 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 713 { 714 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 715 "hw-strap1", &error_abort); 716 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 717 } 718 719 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data) 720 { 721 static const char * const valid_cpu_types[] = { 722 ARM_CPU_TYPE_NAME("cortex-a7"), 723 NULL 724 }; 725 DeviceClass *dc = DEVICE_CLASS(oc); 726 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 727 728 dc->realize = aspeed_soc_ast2600_realize; 729 /* Reason: The Aspeed SoC can only be instantiated from a board */ 730 dc->user_creatable = false; 731 732 sc->valid_cpu_types = valid_cpu_types; 733 sc->silicon_rev = AST2600_A3_SILICON_REV; 734 sc->sram_size = 0x16400; 735 sc->spis_num = 2; 736 sc->ehcis_num = 2; 737 sc->wdts_num = 4; 738 sc->macs_num = 4; 739 sc->uarts_num = 13; 740 sc->uarts_base = ASPEED_DEV_UART1; 741 sc->irqmap = aspeed_soc_ast2600_irqmap; 742 sc->memmap = aspeed_soc_ast2600_memmap; 743 sc->num_cpus = 2; 744 sc->get_irq = aspeed_soc_ast2600_get_irq; 745 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 746 } 747 748 static const TypeInfo aspeed_soc_ast2600_types[] = { 749 { 750 .name = TYPE_ASPEED2600_SOC, 751 .parent = TYPE_ASPEED_SOC, 752 .instance_size = sizeof(Aspeed2600SoCState), 753 .abstract = true, 754 }, { 755 .name = "ast2600-a3", 756 .parent = TYPE_ASPEED2600_SOC, 757 .instance_init = aspeed_soc_ast2600_init, 758 .class_init = aspeed_soc_ast2600_class_init, 759 }, 760 }; 761 762 DEFINE_TYPES(aspeed_soc_ast2600_types) 763