1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_MII1] = 0x1E650000, 37 [ASPEED_DEV_MII2] = 0x1E650008, 38 [ASPEED_DEV_MII3] = 0x1E650010, 39 [ASPEED_DEV_MII4] = 0x1E650018, 40 [ASPEED_DEV_ETH1] = 0x1E660000, 41 [ASPEED_DEV_ETH3] = 0x1E670000, 42 [ASPEED_DEV_ETH2] = 0x1E680000, 43 [ASPEED_DEV_ETH4] = 0x1E690000, 44 [ASPEED_DEV_VIC] = 0x1E6C0000, 45 [ASPEED_DEV_HACE] = 0x1E6D0000, 46 [ASPEED_DEV_SDMC] = 0x1E6E0000, 47 [ASPEED_DEV_SCU] = 0x1E6E2000, 48 [ASPEED_DEV_XDMA] = 0x1E6E7000, 49 [ASPEED_DEV_ADC] = 0x1E6E9000, 50 [ASPEED_DEV_DP] = 0x1E6EB000, 51 [ASPEED_DEV_SBC] = 0x1E6F2000, 52 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 53 [ASPEED_DEV_VIDEO] = 0x1E700000, 54 [ASPEED_DEV_SDHCI] = 0x1E740000, 55 [ASPEED_DEV_EMMC] = 0x1E750000, 56 [ASPEED_DEV_GPIO] = 0x1E780000, 57 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 58 [ASPEED_DEV_RTC] = 0x1E781000, 59 [ASPEED_DEV_TIMER1] = 0x1E782000, 60 [ASPEED_DEV_WDT] = 0x1E785000, 61 [ASPEED_DEV_LPC] = 0x1E789000, 62 [ASPEED_DEV_IBT] = 0x1E789140, 63 [ASPEED_DEV_I2C] = 0x1E78A000, 64 [ASPEED_DEV_PECI] = 0x1E78B000, 65 [ASPEED_DEV_UART1] = 0x1E783000, 66 [ASPEED_DEV_UART2] = 0x1E78D000, 67 [ASPEED_DEV_UART3] = 0x1E78E000, 68 [ASPEED_DEV_UART4] = 0x1E78F000, 69 [ASPEED_DEV_UART5] = 0x1E784000, 70 [ASPEED_DEV_UART6] = 0x1E790000, 71 [ASPEED_DEV_UART7] = 0x1E790100, 72 [ASPEED_DEV_UART8] = 0x1E790200, 73 [ASPEED_DEV_UART9] = 0x1E790300, 74 [ASPEED_DEV_UART10] = 0x1E790400, 75 [ASPEED_DEV_UART11] = 0x1E790500, 76 [ASPEED_DEV_UART12] = 0x1E790600, 77 [ASPEED_DEV_UART13] = 0x1E790700, 78 [ASPEED_DEV_VUART] = 0x1E787000, 79 [ASPEED_DEV_I3C] = 0x1E7A0000, 80 [ASPEED_DEV_SDRAM] = 0x80000000, 81 }; 82 83 #define ASPEED_A7MPCORE_ADDR 0x40460000 84 85 #define AST2600_MAX_IRQ 197 86 87 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 88 static const int aspeed_soc_ast2600_irqmap[] = { 89 [ASPEED_DEV_UART1] = 47, 90 [ASPEED_DEV_UART2] = 48, 91 [ASPEED_DEV_UART3] = 49, 92 [ASPEED_DEV_UART4] = 50, 93 [ASPEED_DEV_UART5] = 8, 94 [ASPEED_DEV_UART6] = 57, 95 [ASPEED_DEV_UART7] = 58, 96 [ASPEED_DEV_UART8] = 59, 97 [ASPEED_DEV_UART9] = 60, 98 [ASPEED_DEV_UART10] = 61, 99 [ASPEED_DEV_UART11] = 62, 100 [ASPEED_DEV_UART12] = 63, 101 [ASPEED_DEV_UART13] = 64, 102 [ASPEED_DEV_VUART] = 8, 103 [ASPEED_DEV_FMC] = 39, 104 [ASPEED_DEV_SDMC] = 0, 105 [ASPEED_DEV_SCU] = 12, 106 [ASPEED_DEV_ADC] = 78, 107 [ASPEED_DEV_XDMA] = 6, 108 [ASPEED_DEV_SDHCI] = 43, 109 [ASPEED_DEV_EHCI1] = 5, 110 [ASPEED_DEV_EHCI2] = 9, 111 [ASPEED_DEV_EMMC] = 15, 112 [ASPEED_DEV_GPIO] = 40, 113 [ASPEED_DEV_GPIO_1_8V] = 11, 114 [ASPEED_DEV_RTC] = 13, 115 [ASPEED_DEV_TIMER1] = 16, 116 [ASPEED_DEV_TIMER2] = 17, 117 [ASPEED_DEV_TIMER3] = 18, 118 [ASPEED_DEV_TIMER4] = 19, 119 [ASPEED_DEV_TIMER5] = 20, 120 [ASPEED_DEV_TIMER6] = 21, 121 [ASPEED_DEV_TIMER7] = 22, 122 [ASPEED_DEV_TIMER8] = 23, 123 [ASPEED_DEV_WDT] = 24, 124 [ASPEED_DEV_PWM] = 44, 125 [ASPEED_DEV_LPC] = 35, 126 [ASPEED_DEV_IBT] = 143, 127 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 128 [ASPEED_DEV_PECI] = 38, 129 [ASPEED_DEV_ETH1] = 2, 130 [ASPEED_DEV_ETH2] = 3, 131 [ASPEED_DEV_HACE] = 4, 132 [ASPEED_DEV_ETH3] = 32, 133 [ASPEED_DEV_ETH4] = 33, 134 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 135 [ASPEED_DEV_DP] = 62, 136 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 137 }; 138 139 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 140 { 141 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 142 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 143 144 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 145 } 146 147 static void aspeed_soc_ast2600_init(Object *obj) 148 { 149 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 150 AspeedSoCState *s = ASPEED_SOC(obj); 151 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 152 int i; 153 char socname[8]; 154 char typename[64]; 155 156 if (sscanf(sc->name, "%7s", socname) != 1) { 157 g_assert_not_reached(); 158 } 159 160 for (i = 0; i < sc->num_cpus; i++) { 161 object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); 162 } 163 164 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 165 object_initialize_child(obj, "scu", &s->scu, typename); 166 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 167 sc->silicon_rev); 168 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 169 "hw-strap1"); 170 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 171 "hw-strap2"); 172 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 173 "hw-prot-key"); 174 175 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 176 TYPE_A15MPCORE_PRIV); 177 178 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 179 180 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 181 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 182 183 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 184 object_initialize_child(obj, "adc", &s->adc, typename); 185 186 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 187 object_initialize_child(obj, "i2c", &s->i2c, typename); 188 189 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 190 191 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 192 object_initialize_child(obj, "fmc", &s->fmc, typename); 193 194 for (i = 0; i < sc->spis_num; i++) { 195 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 196 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 197 } 198 199 for (i = 0; i < sc->ehcis_num; i++) { 200 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 201 TYPE_PLATFORM_EHCI); 202 } 203 204 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 205 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 206 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 207 "ram-size"); 208 209 for (i = 0; i < sc->wdts_num; i++) { 210 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 211 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 212 } 213 214 for (i = 0; i < sc->macs_num; i++) { 215 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 216 TYPE_FTGMAC100); 217 218 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 219 } 220 221 for (i = 0; i < sc->uarts_num; i++) { 222 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 223 } 224 225 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 226 object_initialize_child(obj, "xdma", &s->xdma, typename); 227 228 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 229 object_initialize_child(obj, "gpio", &s->gpio, typename); 230 231 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 232 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 233 234 object_initialize_child(obj, "sd-controller", &s->sdhci, 235 TYPE_ASPEED_SDHCI); 236 237 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 238 239 /* Init sd card slot class here so that they're under the correct parent */ 240 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 241 object_initialize_child(obj, "sd-controller.sdhci[*]", 242 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 243 } 244 245 object_initialize_child(obj, "emmc-controller", &s->emmc, 246 TYPE_ASPEED_SDHCI); 247 248 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 249 250 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 251 TYPE_SYSBUS_SDHCI); 252 253 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 254 255 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 256 object_initialize_child(obj, "hace", &s->hace, typename); 257 258 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 259 260 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 261 262 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 263 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 264 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 265 object_initialize_child(obj, "emmc-boot-controller", 266 &s->emmc_boot_controller, 267 TYPE_UNIMPLEMENTED_DEVICE); 268 } 269 270 /* 271 * ASPEED ast2600 has 0xf as cluster ID 272 * 273 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 274 */ 275 static uint64_t aspeed_calc_affinity(int cpu) 276 { 277 return (0xf << ARM_AFF1_SHIFT) | cpu; 278 } 279 280 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 281 { 282 int i; 283 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 284 AspeedSoCState *s = ASPEED_SOC(dev); 285 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 286 qemu_irq irq; 287 g_autofree char *sram_name = NULL; 288 289 /* Default boot region (SPI memory or ROMs) */ 290 memory_region_init(&s->spi_boot_container, OBJECT(s), 291 "aspeed.spi_boot_container", 0x10000000); 292 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 293 &s->spi_boot_container); 294 295 /* IO space */ 296 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 297 sc->memmap[ASPEED_DEV_IOMEM], 298 ASPEED_SOC_IOMEM_SIZE); 299 300 /* Video engine stub */ 301 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 302 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 303 304 /* eMMC Boot Controller stub */ 305 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 306 "aspeed.emmc-boot-controller", 307 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 308 309 /* CPU */ 310 for (i = 0; i < sc->num_cpus; i++) { 311 if (sc->num_cpus > 1) { 312 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 313 ASPEED_A7MPCORE_ADDR, &error_abort); 314 } 315 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 316 aspeed_calc_affinity(i), &error_abort); 317 318 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 319 &error_abort); 320 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 321 &error_abort); 322 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 323 &error_abort); 324 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 325 OBJECT(s->memory), &error_abort); 326 327 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 328 return; 329 } 330 } 331 332 /* A7MPCORE */ 333 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 334 &error_abort); 335 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 336 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 337 &error_abort); 338 339 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 340 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 341 342 for (i = 0; i < sc->num_cpus; i++) { 343 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 344 DeviceState *d = DEVICE(&a->cpu[i]); 345 346 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 347 sysbus_connect_irq(sbd, i, irq); 348 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 349 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 350 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 351 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 352 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 353 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 354 } 355 356 /* SRAM */ 357 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 358 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 359 errp)) { 360 return; 361 } 362 memory_region_add_subregion(s->memory, 363 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 364 365 /* DPMCU */ 366 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 367 sc->memmap[ASPEED_DEV_DPMCU], 368 ASPEED_SOC_DPMCU_SIZE); 369 370 /* SCU */ 371 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 372 return; 373 } 374 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 375 376 /* RTC */ 377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 378 return; 379 } 380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 382 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 383 384 /* Timer */ 385 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 386 &error_abort); 387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 388 return; 389 } 390 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 391 sc->memmap[ASPEED_DEV_TIMER1]); 392 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 393 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 395 } 396 397 /* ADC */ 398 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 399 return; 400 } 401 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 402 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 403 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 404 405 /* UART */ 406 if (!aspeed_soc_uart_realize(s, errp)) { 407 return; 408 } 409 410 /* I2C */ 411 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 412 &error_abort); 413 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 414 return; 415 } 416 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 417 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 418 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 419 sc->irqmap[ASPEED_DEV_I2C] + i); 420 /* The AST2600 I2C controller has one IRQ per bus. */ 421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 422 } 423 424 /* PECI */ 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 426 return; 427 } 428 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 429 sc->memmap[ASPEED_DEV_PECI]); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 431 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 432 433 /* FMC, The number of CS is set at the board level */ 434 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 435 &error_abort); 436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 437 return; 438 } 439 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 440 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 441 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 443 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 444 445 /* Set up an alias on the FMC CE0 region (boot default) */ 446 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 447 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 448 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 449 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 450 451 /* SPI */ 452 for (i = 0; i < sc->spis_num; i++) { 453 object_property_set_link(OBJECT(&s->spi[i]), "dram", 454 OBJECT(s->dram_mr), &error_abort); 455 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 456 return; 457 } 458 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 459 sc->memmap[ASPEED_DEV_SPI1 + i]); 460 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 461 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 462 } 463 464 /* EHCI */ 465 for (i = 0; i < sc->ehcis_num; i++) { 466 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 467 return; 468 } 469 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 470 sc->memmap[ASPEED_DEV_EHCI1 + i]); 471 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 472 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 473 } 474 475 /* SDMC - SDRAM Memory Controller */ 476 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 477 return; 478 } 479 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 480 sc->memmap[ASPEED_DEV_SDMC]); 481 482 /* Watch dog */ 483 for (i = 0; i < sc->wdts_num; i++) { 484 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 485 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 486 487 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 488 &error_abort); 489 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 490 return; 491 } 492 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 493 } 494 495 /* RAM */ 496 if (!aspeed_soc_dram_init(s, errp)) { 497 return; 498 } 499 500 /* Net */ 501 for (i = 0; i < sc->macs_num; i++) { 502 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 503 &error_abort); 504 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 505 return; 506 } 507 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 508 sc->memmap[ASPEED_DEV_ETH1 + i]); 509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 510 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 511 512 object_property_set_link(OBJECT(&s->mii[i]), "nic", 513 OBJECT(&s->ftgmac100[i]), &error_abort); 514 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 515 return; 516 } 517 518 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 519 sc->memmap[ASPEED_DEV_MII1 + i]); 520 } 521 522 /* XDMA */ 523 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 524 return; 525 } 526 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 527 sc->memmap[ASPEED_DEV_XDMA]); 528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 529 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 530 531 /* GPIO */ 532 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 533 return; 534 } 535 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 536 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 537 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 538 539 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 540 return; 541 } 542 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 543 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 544 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 545 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 546 547 /* SDHCI */ 548 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 549 return; 550 } 551 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 552 sc->memmap[ASPEED_DEV_SDHCI]); 553 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 554 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 555 556 /* eMMC */ 557 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 558 return; 559 } 560 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 561 sc->memmap[ASPEED_DEV_EMMC]); 562 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 563 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 564 565 /* LPC */ 566 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 567 return; 568 } 569 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 570 571 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 572 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 573 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 574 575 /* 576 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 577 * 578 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 579 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 580 * shared across the subdevices, and the shared IRQ output to the VIC is at 581 * offset 0. 582 */ 583 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 584 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 585 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 586 587 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 588 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 589 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 590 591 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 592 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 593 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 594 595 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 596 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 597 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 598 599 /* HACE */ 600 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 601 &error_abort); 602 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 603 return; 604 } 605 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 606 sc->memmap[ASPEED_DEV_HACE]); 607 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 608 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 609 610 /* I3C */ 611 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 612 return; 613 } 614 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 615 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 616 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 617 sc->irqmap[ASPEED_DEV_I3C] + i); 618 /* The AST2600 I3C controller has one IRQ per bus. */ 619 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 620 } 621 622 /* Secure Boot Controller */ 623 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 624 return; 625 } 626 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 627 } 628 629 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 630 { 631 DeviceClass *dc = DEVICE_CLASS(oc); 632 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 633 634 dc->realize = aspeed_soc_ast2600_realize; 635 636 sc->name = "ast2600-a3"; 637 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 638 sc->silicon_rev = AST2600_A3_SILICON_REV; 639 sc->sram_size = 0x16400; 640 sc->spis_num = 2; 641 sc->ehcis_num = 2; 642 sc->wdts_num = 4; 643 sc->macs_num = 4; 644 sc->uarts_num = 13; 645 sc->irqmap = aspeed_soc_ast2600_irqmap; 646 sc->memmap = aspeed_soc_ast2600_memmap; 647 sc->num_cpus = 2; 648 sc->get_irq = aspeed_soc_ast2600_get_irq; 649 } 650 651 static const TypeInfo aspeed_soc_ast2600_types[] = { 652 { 653 .name = TYPE_ASPEED2600_SOC, 654 .parent = TYPE_ASPEED_SOC, 655 .instance_size = sizeof(Aspeed2600SoCState), 656 .abstract = true, 657 }, { 658 .name = "ast2600-a3", 659 .parent = TYPE_ASPEED2600_SOC, 660 .instance_init = aspeed_soc_ast2600_init, 661 .class_init = aspeed_soc_ast2600_class_init, 662 }, 663 }; 664 665 DEFINE_TYPES(aspeed_soc_ast2600_types) 666