1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 22 23 static const hwaddr aspeed_soc_ast2600_memmap[] = { 24 [ASPEED_DEV_SRAM] = 0x10000000, 25 [ASPEED_DEV_DPMCU] = 0x18000000, 26 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 27 [ASPEED_DEV_IOMEM] = 0x1E600000, 28 [ASPEED_DEV_PWM] = 0x1E610000, 29 [ASPEED_DEV_FMC] = 0x1E620000, 30 [ASPEED_DEV_SPI1] = 0x1E630000, 31 [ASPEED_DEV_SPI2] = 0x1E631000, 32 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 33 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 34 [ASPEED_DEV_MII1] = 0x1E650000, 35 [ASPEED_DEV_MII2] = 0x1E650008, 36 [ASPEED_DEV_MII3] = 0x1E650010, 37 [ASPEED_DEV_MII4] = 0x1E650018, 38 [ASPEED_DEV_ETH1] = 0x1E660000, 39 [ASPEED_DEV_ETH3] = 0x1E670000, 40 [ASPEED_DEV_ETH2] = 0x1E680000, 41 [ASPEED_DEV_ETH4] = 0x1E690000, 42 [ASPEED_DEV_VIC] = 0x1E6C0000, 43 [ASPEED_DEV_HACE] = 0x1E6D0000, 44 [ASPEED_DEV_SDMC] = 0x1E6E0000, 45 [ASPEED_DEV_SCU] = 0x1E6E2000, 46 [ASPEED_DEV_XDMA] = 0x1E6E7000, 47 [ASPEED_DEV_ADC] = 0x1E6E9000, 48 [ASPEED_DEV_DP] = 0x1E6EB000, 49 [ASPEED_DEV_SBC] = 0x1E6F2000, 50 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 51 [ASPEED_DEV_VIDEO] = 0x1E700000, 52 [ASPEED_DEV_SDHCI] = 0x1E740000, 53 [ASPEED_DEV_EMMC] = 0x1E750000, 54 [ASPEED_DEV_GPIO] = 0x1E780000, 55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 56 [ASPEED_DEV_RTC] = 0x1E781000, 57 [ASPEED_DEV_TIMER1] = 0x1E782000, 58 [ASPEED_DEV_WDT] = 0x1E785000, 59 [ASPEED_DEV_LPC] = 0x1E789000, 60 [ASPEED_DEV_IBT] = 0x1E789140, 61 [ASPEED_DEV_I2C] = 0x1E78A000, 62 [ASPEED_DEV_PECI] = 0x1E78B000, 63 [ASPEED_DEV_UART1] = 0x1E783000, 64 [ASPEED_DEV_UART2] = 0x1E78D000, 65 [ASPEED_DEV_UART3] = 0x1E78E000, 66 [ASPEED_DEV_UART4] = 0x1E78F000, 67 [ASPEED_DEV_UART5] = 0x1E784000, 68 [ASPEED_DEV_UART6] = 0x1E790000, 69 [ASPEED_DEV_UART7] = 0x1E790100, 70 [ASPEED_DEV_UART8] = 0x1E790200, 71 [ASPEED_DEV_UART9] = 0x1E790300, 72 [ASPEED_DEV_UART10] = 0x1E790400, 73 [ASPEED_DEV_UART11] = 0x1E790500, 74 [ASPEED_DEV_UART12] = 0x1E790600, 75 [ASPEED_DEV_UART13] = 0x1E790700, 76 [ASPEED_DEV_VUART] = 0x1E787000, 77 [ASPEED_DEV_I3C] = 0x1E7A0000, 78 [ASPEED_DEV_SDRAM] = 0x80000000, 79 }; 80 81 #define ASPEED_A7MPCORE_ADDR 0x40460000 82 83 #define AST2600_MAX_IRQ 197 84 85 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 86 static const int aspeed_soc_ast2600_irqmap[] = { 87 [ASPEED_DEV_UART1] = 47, 88 [ASPEED_DEV_UART2] = 48, 89 [ASPEED_DEV_UART3] = 49, 90 [ASPEED_DEV_UART4] = 50, 91 [ASPEED_DEV_UART5] = 8, 92 [ASPEED_DEV_UART6] = 57, 93 [ASPEED_DEV_UART7] = 58, 94 [ASPEED_DEV_UART8] = 59, 95 [ASPEED_DEV_UART9] = 60, 96 [ASPEED_DEV_UART10] = 61, 97 [ASPEED_DEV_UART11] = 62, 98 [ASPEED_DEV_UART12] = 63, 99 [ASPEED_DEV_UART13] = 64, 100 [ASPEED_DEV_VUART] = 8, 101 [ASPEED_DEV_FMC] = 39, 102 [ASPEED_DEV_SDMC] = 0, 103 [ASPEED_DEV_SCU] = 12, 104 [ASPEED_DEV_ADC] = 78, 105 [ASPEED_DEV_XDMA] = 6, 106 [ASPEED_DEV_SDHCI] = 43, 107 [ASPEED_DEV_EHCI1] = 5, 108 [ASPEED_DEV_EHCI2] = 9, 109 [ASPEED_DEV_EMMC] = 15, 110 [ASPEED_DEV_GPIO] = 40, 111 [ASPEED_DEV_GPIO_1_8V] = 11, 112 [ASPEED_DEV_RTC] = 13, 113 [ASPEED_DEV_TIMER1] = 16, 114 [ASPEED_DEV_TIMER2] = 17, 115 [ASPEED_DEV_TIMER3] = 18, 116 [ASPEED_DEV_TIMER4] = 19, 117 [ASPEED_DEV_TIMER5] = 20, 118 [ASPEED_DEV_TIMER6] = 21, 119 [ASPEED_DEV_TIMER7] = 22, 120 [ASPEED_DEV_TIMER8] = 23, 121 [ASPEED_DEV_WDT] = 24, 122 [ASPEED_DEV_PWM] = 44, 123 [ASPEED_DEV_LPC] = 35, 124 [ASPEED_DEV_IBT] = 143, 125 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 126 [ASPEED_DEV_PECI] = 38, 127 [ASPEED_DEV_ETH1] = 2, 128 [ASPEED_DEV_ETH2] = 3, 129 [ASPEED_DEV_HACE] = 4, 130 [ASPEED_DEV_ETH3] = 32, 131 [ASPEED_DEV_ETH4] = 33, 132 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 133 [ASPEED_DEV_DP] = 62, 134 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 135 }; 136 137 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 138 { 139 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 140 141 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); 142 } 143 144 static void aspeed_soc_ast2600_init(Object *obj) 145 { 146 AspeedSoCState *s = ASPEED_SOC(obj); 147 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 148 int i; 149 char socname[8]; 150 char typename[64]; 151 152 if (sscanf(sc->name, "%7s", socname) != 1) { 153 g_assert_not_reached(); 154 } 155 156 for (i = 0; i < sc->num_cpus; i++) { 157 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 158 } 159 160 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 161 object_initialize_child(obj, "scu", &s->scu, typename); 162 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 163 sc->silicon_rev); 164 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 165 "hw-strap1"); 166 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 167 "hw-strap2"); 168 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 169 "hw-prot-key"); 170 171 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 172 TYPE_A15MPCORE_PRIV); 173 174 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 175 176 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 177 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 178 179 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 180 object_initialize_child(obj, "adc", &s->adc, typename); 181 182 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 183 object_initialize_child(obj, "i2c", &s->i2c, typename); 184 185 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 186 187 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 188 object_initialize_child(obj, "fmc", &s->fmc, typename); 189 190 for (i = 0; i < sc->spis_num; i++) { 191 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 192 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 193 } 194 195 for (i = 0; i < sc->ehcis_num; i++) { 196 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 197 TYPE_PLATFORM_EHCI); 198 } 199 200 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 201 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 202 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 203 "ram-size"); 204 205 for (i = 0; i < sc->wdts_num; i++) { 206 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 207 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 208 } 209 210 for (i = 0; i < sc->macs_num; i++) { 211 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 212 TYPE_FTGMAC100); 213 214 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 215 } 216 217 for (i = 0; i < sc->uarts_num; i++) { 218 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 219 } 220 221 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 222 object_initialize_child(obj, "xdma", &s->xdma, typename); 223 224 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 225 object_initialize_child(obj, "gpio", &s->gpio, typename); 226 227 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 228 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 229 230 object_initialize_child(obj, "sd-controller", &s->sdhci, 231 TYPE_ASPEED_SDHCI); 232 233 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 234 235 /* Init sd card slot class here so that they're under the correct parent */ 236 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 237 object_initialize_child(obj, "sd-controller.sdhci[*]", 238 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 239 } 240 241 object_initialize_child(obj, "emmc-controller", &s->emmc, 242 TYPE_ASPEED_SDHCI); 243 244 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 245 246 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 247 TYPE_SYSBUS_SDHCI); 248 249 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 250 251 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 252 object_initialize_child(obj, "hace", &s->hace, typename); 253 254 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 255 256 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 257 258 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 259 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 260 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 261 object_initialize_child(obj, "emmc-boot-controller", 262 &s->emmc_boot_controller, 263 TYPE_UNIMPLEMENTED_DEVICE); 264 } 265 266 /* 267 * ASPEED ast2600 has 0xf as cluster ID 268 * 269 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 270 */ 271 static uint64_t aspeed_calc_affinity(int cpu) 272 { 273 return (0xf << ARM_AFF1_SHIFT) | cpu; 274 } 275 276 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 277 { 278 int i; 279 AspeedSoCState *s = ASPEED_SOC(dev); 280 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 281 Error *err = NULL; 282 qemu_irq irq; 283 g_autofree char *sram_name = NULL; 284 285 /* IO space */ 286 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 287 sc->memmap[ASPEED_DEV_IOMEM], 288 ASPEED_SOC_IOMEM_SIZE); 289 290 /* Video engine stub */ 291 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 292 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 293 294 /* eMMC Boot Controller stub */ 295 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 296 "aspeed.emmc-boot-controller", 297 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 298 299 /* CPU */ 300 for (i = 0; i < sc->num_cpus; i++) { 301 if (sc->num_cpus > 1) { 302 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 303 ASPEED_A7MPCORE_ADDR, &error_abort); 304 } 305 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 306 aspeed_calc_affinity(i), &error_abort); 307 308 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 309 &error_abort); 310 object_property_set_link(OBJECT(&s->cpu[i]), "memory", 311 OBJECT(s->memory), &error_abort); 312 313 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 314 return; 315 } 316 } 317 318 /* A7MPCORE */ 319 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 320 &error_abort); 321 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 322 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 323 &error_abort); 324 325 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 326 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 327 328 for (i = 0; i < sc->num_cpus; i++) { 329 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 330 DeviceState *d = DEVICE(&s->cpu[i]); 331 332 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 333 sysbus_connect_irq(sbd, i, irq); 334 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 335 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 336 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 337 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 338 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 339 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 340 } 341 342 /* SRAM */ 343 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index); 344 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); 345 if (err) { 346 error_propagate(errp, err); 347 return; 348 } 349 memory_region_add_subregion(s->memory, 350 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 351 352 /* DPMCU */ 353 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 354 sc->memmap[ASPEED_DEV_DPMCU], 355 ASPEED_SOC_DPMCU_SIZE); 356 357 /* SCU */ 358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 359 return; 360 } 361 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 362 363 /* RTC */ 364 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 365 return; 366 } 367 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 368 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 369 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 370 371 /* Timer */ 372 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 373 &error_abort); 374 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 375 return; 376 } 377 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 378 sc->memmap[ASPEED_DEV_TIMER1]); 379 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 380 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 381 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 382 } 383 384 /* ADC */ 385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 386 return; 387 } 388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 389 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 390 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 391 392 /* UART */ 393 if (!aspeed_soc_uart_realize(s, errp)) { 394 return; 395 } 396 397 /* I2C */ 398 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 399 &error_abort); 400 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 401 return; 402 } 403 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 404 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 405 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 406 sc->irqmap[ASPEED_DEV_I2C] + i); 407 /* The AST2600 I2C controller has one IRQ per bus. */ 408 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 409 } 410 411 /* PECI */ 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 413 return; 414 } 415 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 416 sc->memmap[ASPEED_DEV_PECI]); 417 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 418 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 419 420 /* FMC, The number of CS is set at the board level */ 421 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 422 &error_abort); 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 424 return; 425 } 426 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 427 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 428 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 430 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 431 432 /* SPI */ 433 for (i = 0; i < sc->spis_num; i++) { 434 object_property_set_link(OBJECT(&s->spi[i]), "dram", 435 OBJECT(s->dram_mr), &error_abort); 436 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 437 return; 438 } 439 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 440 sc->memmap[ASPEED_DEV_SPI1 + i]); 441 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 442 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 443 } 444 445 /* EHCI */ 446 for (i = 0; i < sc->ehcis_num; i++) { 447 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 448 return; 449 } 450 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 451 sc->memmap[ASPEED_DEV_EHCI1 + i]); 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 453 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 454 } 455 456 /* SDMC - SDRAM Memory Controller */ 457 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 458 return; 459 } 460 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 461 sc->memmap[ASPEED_DEV_SDMC]); 462 463 /* Watch dog */ 464 for (i = 0; i < sc->wdts_num; i++) { 465 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 466 467 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 468 &error_abort); 469 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 470 return; 471 } 472 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 473 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 474 } 475 476 /* RAM */ 477 if (!aspeed_soc_dram_init(s, errp)) { 478 return; 479 } 480 481 /* Net */ 482 for (i = 0; i < sc->macs_num; i++) { 483 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 484 &error_abort); 485 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 486 return; 487 } 488 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 489 sc->memmap[ASPEED_DEV_ETH1 + i]); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 491 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 492 493 object_property_set_link(OBJECT(&s->mii[i]), "nic", 494 OBJECT(&s->ftgmac100[i]), &error_abort); 495 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 496 return; 497 } 498 499 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 500 sc->memmap[ASPEED_DEV_MII1 + i]); 501 } 502 503 /* XDMA */ 504 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 505 return; 506 } 507 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 508 sc->memmap[ASPEED_DEV_XDMA]); 509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 510 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 511 512 /* GPIO */ 513 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 514 return; 515 } 516 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 518 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 519 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 521 return; 522 } 523 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 524 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 525 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 526 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 527 528 /* SDHCI */ 529 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 530 return; 531 } 532 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 533 sc->memmap[ASPEED_DEV_SDHCI]); 534 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 535 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 536 537 /* eMMC */ 538 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 539 return; 540 } 541 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 542 sc->memmap[ASPEED_DEV_EMMC]); 543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 544 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 545 546 /* LPC */ 547 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 548 return; 549 } 550 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 551 552 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 553 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 554 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 555 556 /* 557 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 558 * 559 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 560 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 561 * shared across the subdevices, and the shared IRQ output to the VIC is at 562 * offset 0. 563 */ 564 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 565 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 566 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 567 568 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 569 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 570 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 571 572 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 573 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 574 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 575 576 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 577 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 578 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 579 580 /* HACE */ 581 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 582 &error_abort); 583 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 584 return; 585 } 586 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 587 sc->memmap[ASPEED_DEV_HACE]); 588 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 589 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 590 591 /* I3C */ 592 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 593 return; 594 } 595 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 596 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 597 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 598 sc->irqmap[ASPEED_DEV_I3C] + i); 599 /* The AST2600 I3C controller has one IRQ per bus. */ 600 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 601 } 602 603 /* Secure Boot Controller */ 604 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 605 return; 606 } 607 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 608 } 609 610 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 611 { 612 DeviceClass *dc = DEVICE_CLASS(oc); 613 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 614 615 dc->realize = aspeed_soc_ast2600_realize; 616 617 sc->name = "ast2600-a3"; 618 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 619 sc->silicon_rev = AST2600_A3_SILICON_REV; 620 sc->sram_size = 0x16400; 621 sc->spis_num = 2; 622 sc->ehcis_num = 2; 623 sc->wdts_num = 4; 624 sc->macs_num = 4; 625 sc->uarts_num = 13; 626 sc->irqmap = aspeed_soc_ast2600_irqmap; 627 sc->memmap = aspeed_soc_ast2600_memmap; 628 sc->num_cpus = 2; 629 sc->get_irq = aspeed_soc_ast2600_get_irq; 630 } 631 632 static const TypeInfo aspeed_soc_ast2600_type_info = { 633 .name = "ast2600-a3", 634 .parent = TYPE_ASPEED_SOC, 635 .instance_size = sizeof(AspeedSoCState), 636 .instance_init = aspeed_soc_ast2600_init, 637 .class_init = aspeed_soc_ast2600_class_init, 638 .class_size = sizeof(AspeedSoCClass), 639 }; 640 641 static void aspeed_soc_register_types(void) 642 { 643 type_register_static(&aspeed_soc_ast2600_type_info); 644 }; 645 646 type_init(aspeed_soc_register_types) 647