1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "system/system.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_MII1] = 0x1E650000, 37 [ASPEED_DEV_MII2] = 0x1E650008, 38 [ASPEED_DEV_MII3] = 0x1E650010, 39 [ASPEED_DEV_MII4] = 0x1E650018, 40 [ASPEED_DEV_ETH1] = 0x1E660000, 41 [ASPEED_DEV_ETH3] = 0x1E670000, 42 [ASPEED_DEV_ETH2] = 0x1E680000, 43 [ASPEED_DEV_ETH4] = 0x1E690000, 44 [ASPEED_DEV_VIC] = 0x1E6C0000, 45 [ASPEED_DEV_HACE] = 0x1E6D0000, 46 [ASPEED_DEV_SDMC] = 0x1E6E0000, 47 [ASPEED_DEV_SCU] = 0x1E6E2000, 48 [ASPEED_DEV_GFX] = 0x1E6E6000, 49 [ASPEED_DEV_XDMA] = 0x1E6E7000, 50 [ASPEED_DEV_ADC] = 0x1E6E9000, 51 [ASPEED_DEV_DP] = 0x1E6EB000, 52 [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED200, 53 [ASPEED_DEV_SBC] = 0x1E6F2000, 54 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 55 [ASPEED_DEV_VIDEO] = 0x1E700000, 56 [ASPEED_DEV_SDHCI] = 0x1E740000, 57 [ASPEED_DEV_EMMC] = 0x1E750000, 58 [ASPEED_DEV_PCIE0] = 0x1E770000, 59 [ASPEED_DEV_GPIO] = 0x1E780000, 60 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 61 [ASPEED_DEV_RTC] = 0x1E781000, 62 [ASPEED_DEV_TIMER1] = 0x1E782000, 63 [ASPEED_DEV_WDT] = 0x1E785000, 64 [ASPEED_DEV_LPC] = 0x1E789000, 65 [ASPEED_DEV_IBT] = 0x1E789140, 66 [ASPEED_DEV_I2C] = 0x1E78A000, 67 [ASPEED_DEV_PECI] = 0x1E78B000, 68 [ASPEED_DEV_UART1] = 0x1E783000, 69 [ASPEED_DEV_UART2] = 0x1E78D000, 70 [ASPEED_DEV_UART3] = 0x1E78E000, 71 [ASPEED_DEV_UART4] = 0x1E78F000, 72 [ASPEED_DEV_UART5] = 0x1E784000, 73 [ASPEED_DEV_UART6] = 0x1E790000, 74 [ASPEED_DEV_UART7] = 0x1E790100, 75 [ASPEED_DEV_UART8] = 0x1E790200, 76 [ASPEED_DEV_UART9] = 0x1E790300, 77 [ASPEED_DEV_UART10] = 0x1E790400, 78 [ASPEED_DEV_UART11] = 0x1E790500, 79 [ASPEED_DEV_UART12] = 0x1E790600, 80 [ASPEED_DEV_UART13] = 0x1E790700, 81 [ASPEED_DEV_VUART] = 0x1E787000, 82 [ASPEED_DEV_FSI1] = 0x1E79B000, 83 [ASPEED_DEV_FSI2] = 0x1E79B100, 84 [ASPEED_DEV_I3C] = 0x1E7A0000, 85 [ASPEED_DEV_PCIE_MMIO1] = 0x70000000, 86 [ASPEED_DEV_SDRAM] = 0x80000000, 87 }; 88 89 #define ASPEED_A7MPCORE_ADDR 0x40460000 90 91 #define AST2600_MAX_IRQ 197 92 93 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 94 static const int aspeed_soc_ast2600_irqmap[] = { 95 [ASPEED_DEV_UART1] = 47, 96 [ASPEED_DEV_UART2] = 48, 97 [ASPEED_DEV_UART3] = 49, 98 [ASPEED_DEV_UART4] = 50, 99 [ASPEED_DEV_UART5] = 8, 100 [ASPEED_DEV_UART6] = 57, 101 [ASPEED_DEV_UART7] = 58, 102 [ASPEED_DEV_UART8] = 59, 103 [ASPEED_DEV_UART9] = 60, 104 [ASPEED_DEV_UART10] = 61, 105 [ASPEED_DEV_UART11] = 62, 106 [ASPEED_DEV_UART12] = 63, 107 [ASPEED_DEV_UART13] = 64, 108 [ASPEED_DEV_VUART] = 8, 109 [ASPEED_DEV_FMC] = 39, 110 [ASPEED_DEV_SDMC] = 0, 111 [ASPEED_DEV_SCU] = 12, 112 [ASPEED_DEV_ADC] = 78, 113 [ASPEED_DEV_GFX] = 14, 114 [ASPEED_DEV_XDMA] = 6, 115 [ASPEED_DEV_SDHCI] = 43, 116 [ASPEED_DEV_EHCI1] = 5, 117 [ASPEED_DEV_EHCI2] = 9, 118 [ASPEED_DEV_EMMC] = 15, 119 [ASPEED_DEV_GPIO] = 40, 120 [ASPEED_DEV_GPIO_1_8V] = 11, 121 [ASPEED_DEV_RTC] = 13, 122 [ASPEED_DEV_TIMER1] = 16, 123 [ASPEED_DEV_TIMER2] = 17, 124 [ASPEED_DEV_TIMER3] = 18, 125 [ASPEED_DEV_TIMER4] = 19, 126 [ASPEED_DEV_TIMER5] = 20, 127 [ASPEED_DEV_TIMER6] = 21, 128 [ASPEED_DEV_TIMER7] = 22, 129 [ASPEED_DEV_TIMER8] = 23, 130 [ASPEED_DEV_WDT] = 24, 131 [ASPEED_DEV_PWM] = 44, 132 [ASPEED_DEV_LPC] = 35, 133 [ASPEED_DEV_IBT] = 143, 134 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 135 [ASPEED_DEV_PCIE0] = 168, 136 [ASPEED_DEV_PECI] = 38, 137 [ASPEED_DEV_ETH1] = 2, 138 [ASPEED_DEV_ETH2] = 3, 139 [ASPEED_DEV_HACE] = 4, 140 [ASPEED_DEV_ETH3] = 32, 141 [ASPEED_DEV_ETH4] = 33, 142 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 143 [ASPEED_DEV_DP] = 62, 144 [ASPEED_DEV_FSI1] = 100, 145 [ASPEED_DEV_FSI2] = 101, 146 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 147 }; 148 149 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 150 { 151 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 153 154 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 155 } 156 157 static void aspeed_soc_ast2600_init(Object *obj) 158 { 159 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 160 AspeedSoCState *s = ASPEED_SOC(obj); 161 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 162 int i; 163 char socname[8]; 164 char typename[64]; 165 166 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 167 g_assert_not_reached(); 168 } 169 170 for (i = 0; i < sc->num_cpus; i++) { 171 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 172 aspeed_soc_cpu_type(sc)); 173 } 174 175 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 176 object_initialize_child(obj, "scu", &s->scu, typename); 177 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 178 sc->silicon_rev); 179 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 180 "hw-strap1"); 181 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 182 "hw-strap2"); 183 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 184 "hw-prot-key"); 185 186 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 187 TYPE_A15MPCORE_PRIV); 188 189 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 190 191 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 192 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 193 194 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 195 object_initialize_child(obj, "adc", &s->adc, typename); 196 197 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 198 object_initialize_child(obj, "i2c", &s->i2c, typename); 199 200 object_initialize_child(obj, "pcie-cfg", &s->pcie[0], TYPE_ASPEED_PCIE_CFG); 201 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[0], 202 TYPE_ASPEED_PCIE_PHY); 203 204 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 205 206 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 207 object_initialize_child(obj, "fmc", &s->fmc, typename); 208 209 for (i = 0; i < sc->spis_num; i++) { 210 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 211 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 212 } 213 214 for (i = 0; i < sc->ehcis_num; i++) { 215 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 216 TYPE_PLATFORM_EHCI); 217 } 218 219 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 220 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 221 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 222 "ram-size"); 223 224 for (i = 0; i < sc->wdts_num; i++) { 225 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 226 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 227 } 228 229 for (i = 0; i < sc->macs_num; i++) { 230 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 231 TYPE_FTGMAC100); 232 233 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 234 } 235 236 for (i = 0; i < sc->uarts_num; i++) { 237 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 238 } 239 240 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 241 object_initialize_child(obj, "xdma", &s->xdma, typename); 242 243 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 244 object_initialize_child(obj, "gpio", &s->gpio, typename); 245 246 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 247 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 248 249 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 250 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 251 252 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 253 254 /* Init sd card slot class here so that they're under the correct parent */ 255 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 256 object_initialize_child(obj, "sd-controller.sdhci[*]", 257 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 258 } 259 260 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 261 262 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 263 264 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 265 TYPE_SYSBUS_SDHCI); 266 267 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 268 269 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 270 object_initialize_child(obj, "hace", &s->hace, typename); 271 272 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 273 274 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); 275 276 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 277 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 278 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 279 object_initialize_child(obj, "emmc-boot-controller", 280 &s->emmc_boot_controller, 281 TYPE_UNIMPLEMENTED_DEVICE); 282 283 for (i = 0; i < ASPEED_FSI_NUM; i++) { 284 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 285 } 286 287 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 288 } 289 290 /* 291 * ASPEED ast2600 has 0xf as cluster ID 292 * 293 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 294 */ 295 static uint64_t aspeed_calc_affinity(int cpu) 296 { 297 return (0xf << ARM_AFF1_SHIFT) | cpu; 298 } 299 300 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 301 { 302 int i; 303 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 304 AspeedSoCState *s = ASPEED_SOC(dev); 305 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 306 qemu_irq irq; 307 g_autofree char *name = NULL; 308 MemoryRegion *mmio_alias; 309 MemoryRegion *mmio_mr; 310 311 /* Default boot region (SPI memory or ROMs) */ 312 memory_region_init(&s->spi_boot_container, OBJECT(s), 313 "aspeed.spi_boot_container", 0x10000000); 314 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 315 &s->spi_boot_container); 316 317 /* IO space */ 318 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 319 sc->memmap[ASPEED_DEV_IOMEM], 320 ASPEED_SOC_IOMEM_SIZE); 321 322 /* Video engine stub */ 323 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 324 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 325 326 /* eMMC Boot Controller stub */ 327 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 328 "aspeed.emmc-boot-controller", 329 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 330 331 /* CPU */ 332 for (i = 0; i < sc->num_cpus; i++) { 333 if (sc->num_cpus > 1) { 334 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 335 ASPEED_A7MPCORE_ADDR, &error_abort); 336 } 337 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 338 aspeed_calc_affinity(i), &error_abort); 339 340 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 341 &error_abort); 342 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 343 &error_abort); 344 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 345 &error_abort); 346 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 347 OBJECT(s->memory), &error_abort); 348 349 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 350 return; 351 } 352 } 353 354 /* A7MPCORE */ 355 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 356 &error_abort); 357 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 358 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 359 &error_abort); 360 361 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 363 364 for (i = 0; i < sc->num_cpus; i++) { 365 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 366 DeviceState *d = DEVICE(&a->cpu[i]); 367 368 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 369 sysbus_connect_irq(sbd, i, irq); 370 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 371 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 372 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 373 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 374 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 375 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 376 } 377 378 /* SRAM */ 379 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 380 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 381 errp)) { 382 return; 383 } 384 memory_region_add_subregion(s->memory, 385 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 386 387 /* DPMCU */ 388 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 389 sc->memmap[ASPEED_DEV_DPMCU], 390 ASPEED_SOC_DPMCU_SIZE); 391 392 /* SCU */ 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 394 return; 395 } 396 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 397 398 /* RTC */ 399 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 400 return; 401 } 402 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 404 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 405 406 /* Timer */ 407 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 408 &error_abort); 409 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 410 return; 411 } 412 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 413 sc->memmap[ASPEED_DEV_TIMER1]); 414 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 415 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 417 } 418 419 /* ADC */ 420 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 421 return; 422 } 423 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 425 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 426 427 /* UART */ 428 if (!aspeed_soc_uart_realize(s, errp)) { 429 return; 430 } 431 432 /* I2C */ 433 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 434 &error_abort); 435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 436 return; 437 } 438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 439 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 440 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 441 sc->irqmap[ASPEED_DEV_I2C] + i); 442 /* The AST2600 I2C controller has one IRQ per bus. */ 443 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 444 } 445 446 /* PECI */ 447 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 448 return; 449 } 450 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 451 sc->memmap[ASPEED_DEV_PECI]); 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 453 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 454 455 /* 456 * PCIe Root Complex (RC) 457 * 458 * H2X register space (single block 0x00-0xFF): 459 * 0x00-0x7F : shared by RC_L (PCIe0) and RC_H (PCIe1) 460 * 0x80-0xBF : RC_L only 461 * 0xC0-0xFF : RC_H only 462 * 463 * Model scope / limitations: 464 * - Firmware supports RC_H only; this QEMU model does not support RC_L. 465 * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000] 466 * (aka MMIO1). 467 * 468 * Indexing convention (this model): 469 * - Expose a single logical instance at index 0. 470 * - pcie[0] -> hardware RC_H (PCIe1) 471 * - phy[0] -> hardware PHY1 472 * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000 473 * - RC_L / PCIe0 is not created and mapped. 474 */ 475 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { 476 return; 477 } 478 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, 479 sc->memmap[ASPEED_DEV_PCIE_PHY1]); 480 481 object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", 482 sc->memmap[ASPEED_DEV_SDRAM], 483 &error_abort); 484 object_property_set_link(OBJECT(&s->pcie[0]), "dram", OBJECT(s->dram_mr), 485 &error_abort); 486 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { 487 return; 488 } 489 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0, 490 sc->memmap[ASPEED_DEV_PCIE0]); 491 492 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 493 sc->irqmap[ASPEED_DEV_PCIE0]); 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[0].rc), 0, irq); 495 496 name = g_strdup_printf("aspeed.pcie-mmio.0"); 497 498 mmio_alias = g_new0(MemoryRegion, 1); 499 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[0].rc), 1); 500 501 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[0].rc), name, 502 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1], 503 0x10000000); 504 memory_region_add_subregion(s->memory, 505 sc->memmap[ASPEED_DEV_PCIE_MMIO1], 506 mmio_alias); 507 508 /* FMC, The number of CS is set at the board level */ 509 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 510 &error_abort); 511 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 512 return; 513 } 514 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 515 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 516 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 518 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 519 520 /* Set up an alias on the FMC CE0 region (boot default) */ 521 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 522 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 523 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 524 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 525 526 /* SPI */ 527 for (i = 0; i < sc->spis_num; i++) { 528 object_property_set_link(OBJECT(&s->spi[i]), "dram", 529 OBJECT(s->dram_mr), &error_abort); 530 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 531 return; 532 } 533 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 534 sc->memmap[ASPEED_DEV_SPI1 + i]); 535 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 536 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 537 } 538 539 /* EHCI */ 540 for (i = 0; i < sc->ehcis_num; i++) { 541 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 542 return; 543 } 544 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 545 sc->memmap[ASPEED_DEV_EHCI1 + i]); 546 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 547 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 548 } 549 550 /* SDMC - SDRAM Memory Controller */ 551 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 552 return; 553 } 554 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 555 sc->memmap[ASPEED_DEV_SDMC]); 556 557 /* Watch dog */ 558 for (i = 0; i < sc->wdts_num; i++) { 559 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 560 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 561 562 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 563 &error_abort); 564 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 565 return; 566 } 567 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 568 } 569 570 /* RAM */ 571 if (!aspeed_soc_dram_init(s, errp)) { 572 return; 573 } 574 575 /* Net */ 576 for (i = 0; i < sc->macs_num; i++) { 577 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 578 &error_abort); 579 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 580 return; 581 } 582 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 583 sc->memmap[ASPEED_DEV_ETH1 + i]); 584 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 585 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 586 587 object_property_set_link(OBJECT(&s->mii[i]), "nic", 588 OBJECT(&s->ftgmac100[i]), &error_abort); 589 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 590 return; 591 } 592 593 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 594 sc->memmap[ASPEED_DEV_MII1 + i]); 595 } 596 597 /* XDMA */ 598 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 599 return; 600 } 601 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 602 sc->memmap[ASPEED_DEV_XDMA]); 603 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 604 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 605 606 /* GPIO */ 607 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 608 return; 609 } 610 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 611 sc->memmap[ASPEED_DEV_GPIO]); 612 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 613 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 614 615 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 616 return; 617 } 618 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 619 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 620 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 621 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 622 623 /* SDHCI */ 624 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 625 return; 626 } 627 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 628 sc->memmap[ASPEED_DEV_SDHCI]); 629 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 630 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 631 632 /* eMMC */ 633 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 634 return; 635 } 636 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 637 sc->memmap[ASPEED_DEV_EMMC]); 638 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 639 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 640 641 /* LPC */ 642 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 643 return; 644 } 645 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 646 647 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 648 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 649 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 650 651 /* 652 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 653 * 654 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 655 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 656 * shared across the subdevices, and the shared IRQ output to the VIC is at 657 * offset 0. 658 */ 659 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 660 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 661 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 662 663 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 664 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 665 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 666 667 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 668 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 669 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 670 671 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 672 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 673 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 674 675 /* HACE */ 676 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 677 &error_abort); 678 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 679 return; 680 } 681 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 682 sc->memmap[ASPEED_DEV_HACE]); 683 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 684 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 685 686 /* I3C */ 687 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 688 return; 689 } 690 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 691 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 692 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 693 sc->irqmap[ASPEED_DEV_I3C] + i); 694 /* The AST2600 I3C controller has one IRQ per bus. */ 695 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 696 } 697 698 /* Secure Boot Controller */ 699 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 700 return; 701 } 702 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 703 704 /* FSI */ 705 for (i = 0; i < ASPEED_FSI_NUM; i++) { 706 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 707 return; 708 } 709 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 710 sc->memmap[ASPEED_DEV_FSI1 + i]); 711 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 712 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 713 } 714 715 /* GFX */ 716 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 717 return; 718 } 719 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 720 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 721 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 722 } 723 724 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 725 { 726 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 727 "hw-strap1", &error_abort); 728 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 729 } 730 731 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data) 732 { 733 static const char * const valid_cpu_types[] = { 734 ARM_CPU_TYPE_NAME("cortex-a7"), 735 NULL 736 }; 737 DeviceClass *dc = DEVICE_CLASS(oc); 738 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 739 740 dc->realize = aspeed_soc_ast2600_realize; 741 /* Reason: The Aspeed SoC can only be instantiated from a board */ 742 dc->user_creatable = false; 743 744 sc->valid_cpu_types = valid_cpu_types; 745 sc->silicon_rev = AST2600_A3_SILICON_REV; 746 sc->sram_size = 0x16400; 747 sc->spis_num = 2; 748 sc->ehcis_num = 2; 749 sc->wdts_num = 4; 750 sc->macs_num = 4; 751 sc->uarts_num = 13; 752 sc->uarts_base = ASPEED_DEV_UART1; 753 sc->irqmap = aspeed_soc_ast2600_irqmap; 754 sc->memmap = aspeed_soc_ast2600_memmap; 755 sc->num_cpus = 2; 756 sc->get_irq = aspeed_soc_ast2600_get_irq; 757 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 758 } 759 760 static const TypeInfo aspeed_soc_ast2600_types[] = { 761 { 762 .name = TYPE_ASPEED2600_SOC, 763 .parent = TYPE_ASPEED_SOC, 764 .instance_size = sizeof(Aspeed2600SoCState), 765 .abstract = true, 766 }, { 767 .name = "ast2600-a3", 768 .parent = TYPE_ASPEED2600_SOC, 769 .instance_init = aspeed_soc_ast2600_init, 770 .class_init = aspeed_soc_ast2600_class_init, 771 }, 772 }; 773 774 DEFINE_TYPES(aspeed_soc_ast2600_types) 775