1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_MII1] = 0x1E650000, 35 [ASPEED_MII2] = 0x1E650008, 36 [ASPEED_MII3] = 0x1E650010, 37 [ASPEED_MII4] = 0x1E650018, 38 [ASPEED_ETH1] = 0x1E660000, 39 [ASPEED_ETH3] = 0x1E670000, 40 [ASPEED_ETH2] = 0x1E680000, 41 [ASPEED_ETH4] = 0x1E690000, 42 [ASPEED_VIC] = 0x1E6C0000, 43 [ASPEED_SDMC] = 0x1E6E0000, 44 [ASPEED_SCU] = 0x1E6E2000, 45 [ASPEED_XDMA] = 0x1E6E7000, 46 [ASPEED_ADC] = 0x1E6E9000, 47 [ASPEED_VIDEO] = 0x1E700000, 48 [ASPEED_SDHCI] = 0x1E740000, 49 [ASPEED_EMMC] = 0x1E750000, 50 [ASPEED_GPIO] = 0x1E780000, 51 [ASPEED_GPIO_1_8V] = 0x1E780800, 52 [ASPEED_RTC] = 0x1E781000, 53 [ASPEED_TIMER1] = 0x1E782000, 54 [ASPEED_WDT] = 0x1E785000, 55 [ASPEED_LPC] = 0x1E789000, 56 [ASPEED_IBT] = 0x1E789140, 57 [ASPEED_I2C] = 0x1E78A000, 58 [ASPEED_UART1] = 0x1E783000, 59 [ASPEED_UART5] = 0x1E784000, 60 [ASPEED_VUART] = 0x1E787000, 61 [ASPEED_SDRAM] = 0x80000000, 62 }; 63 64 #define ASPEED_A7MPCORE_ADDR 0x40460000 65 66 #define ASPEED_SOC_AST2600_MAX_IRQ 128 67 68 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 69 static const int aspeed_soc_ast2600_irqmap[] = { 70 [ASPEED_UART1] = 47, 71 [ASPEED_UART2] = 48, 72 [ASPEED_UART3] = 49, 73 [ASPEED_UART4] = 50, 74 [ASPEED_UART5] = 8, 75 [ASPEED_VUART] = 8, 76 [ASPEED_FMC] = 39, 77 [ASPEED_SDMC] = 0, 78 [ASPEED_SCU] = 12, 79 [ASPEED_ADC] = 78, 80 [ASPEED_XDMA] = 6, 81 [ASPEED_SDHCI] = 43, 82 [ASPEED_EMMC] = 15, 83 [ASPEED_GPIO] = 40, 84 [ASPEED_GPIO_1_8V] = 11, 85 [ASPEED_RTC] = 13, 86 [ASPEED_TIMER1] = 16, 87 [ASPEED_TIMER2] = 17, 88 [ASPEED_TIMER3] = 18, 89 [ASPEED_TIMER4] = 19, 90 [ASPEED_TIMER5] = 20, 91 [ASPEED_TIMER6] = 21, 92 [ASPEED_TIMER7] = 22, 93 [ASPEED_TIMER8] = 23, 94 [ASPEED_WDT] = 24, 95 [ASPEED_PWM] = 44, 96 [ASPEED_LPC] = 35, 97 [ASPEED_IBT] = 35, /* LPC */ 98 [ASPEED_I2C] = 110, /* 110 -> 125 */ 99 [ASPEED_ETH1] = 2, 100 [ASPEED_ETH2] = 3, 101 [ASPEED_ETH3] = 32, 102 [ASPEED_ETH4] = 33, 103 104 }; 105 106 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 107 { 108 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 109 110 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 111 } 112 113 static void aspeed_soc_ast2600_init(Object *obj) 114 { 115 AspeedSoCState *s = ASPEED_SOC(obj); 116 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 117 int i; 118 char socname[8]; 119 char typename[64]; 120 121 if (sscanf(sc->name, "%7s", socname) != 1) { 122 g_assert_not_reached(); 123 } 124 125 for (i = 0; i < sc->num_cpus; i++) { 126 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 127 sizeof(s->cpu[i]), sc->cpu_type, 128 &error_abort, NULL); 129 } 130 131 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 132 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 133 typename); 134 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 135 sc->silicon_rev); 136 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 137 "hw-strap1", &error_abort); 138 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 139 "hw-strap2", &error_abort); 140 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 141 "hw-prot-key", &error_abort); 142 143 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 144 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 145 146 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 147 TYPE_ASPEED_RTC); 148 149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 150 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 151 sizeof(s->timerctrl), typename); 152 153 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 154 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 155 typename); 156 157 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 158 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 159 typename); 160 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", 161 &error_abort); 162 163 for (i = 0; i < sc->spis_num; i++) { 164 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 165 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 166 sizeof(s->spi[i]), typename); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 171 typename); 172 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 173 "ram-size", &error_abort); 174 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 175 "max-ram-size", &error_abort); 176 177 for (i = 0; i < sc->wdts_num; i++) { 178 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 179 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 180 sizeof(s->wdt[i]), typename); 181 } 182 183 for (i = 0; i < sc->macs_num; i++) { 184 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 185 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 186 187 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 188 TYPE_ASPEED_MII); 189 } 190 191 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 192 TYPE_ASPEED_XDMA); 193 194 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 195 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 196 typename); 197 198 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 199 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 200 sizeof(s->gpio_1_8v), typename); 201 202 sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), 203 sizeof(s->sdhci), TYPE_ASPEED_SDHCI); 204 205 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 206 207 /* Init sd card slot class here so that they're under the correct parent */ 208 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 209 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 210 OBJECT(&s->sdhci.slots[i]), 211 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 212 } 213 214 sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), 215 sizeof(s->emmc), TYPE_ASPEED_SDHCI); 216 217 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 218 219 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 220 OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), 221 TYPE_SYSBUS_SDHCI); 222 } 223 224 /* 225 * ASPEED ast2600 has 0xf as cluster ID 226 * 227 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 228 */ 229 static uint64_t aspeed_calc_affinity(int cpu) 230 { 231 return (0xf << ARM_AFF1_SHIFT) | cpu; 232 } 233 234 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 235 { 236 int i; 237 AspeedSoCState *s = ASPEED_SOC(dev); 238 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 239 Error *err = NULL, *local_err = NULL; 240 qemu_irq irq; 241 242 /* IO space */ 243 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 244 ASPEED_SOC_IOMEM_SIZE); 245 246 /* Video engine stub */ 247 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 248 0x1000); 249 250 if (s->num_cpus > sc->num_cpus) { 251 warn_report("%s: invalid number of CPUs %d, using default %d", 252 sc->name, s->num_cpus, sc->num_cpus); 253 s->num_cpus = sc->num_cpus; 254 } 255 256 /* CPU */ 257 for (i = 0; i < s->num_cpus; i++) { 258 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 259 "psci-conduit", &error_abort); 260 if (s->num_cpus > 1) { 261 object_property_set_int(OBJECT(&s->cpu[i]), 262 ASPEED_A7MPCORE_ADDR, 263 "reset-cbar", &error_abort); 264 } 265 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 266 "mp-affinity", &error_abort); 267 268 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 269 &error_abort); 270 271 /* 272 * TODO: the secondary CPUs are started and a boot helper 273 * is needed when using -kernel 274 */ 275 276 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 277 if (err) { 278 error_propagate(errp, err); 279 return; 280 } 281 } 282 283 /* A7MPCORE */ 284 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", 285 &error_abort); 286 object_property_set_int(OBJECT(&s->a7mpcore), 287 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 288 "num-irq", &error_abort); 289 290 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 291 &error_abort); 292 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 293 294 for (i = 0; i < s->num_cpus; i++) { 295 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 296 DeviceState *d = DEVICE(qemu_get_cpu(i)); 297 298 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 299 sysbus_connect_irq(sbd, i, irq); 300 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 301 sysbus_connect_irq(sbd, i + s->num_cpus, irq); 302 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 303 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); 304 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 305 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); 306 } 307 308 /* SRAM */ 309 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 310 sc->sram_size, &err); 311 if (err) { 312 error_propagate(errp, err); 313 return; 314 } 315 memory_region_add_subregion(get_system_memory(), 316 sc->memmap[ASPEED_SRAM], &s->sram); 317 318 /* SCU */ 319 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 320 if (err) { 321 error_propagate(errp, err); 322 return; 323 } 324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 325 326 /* RTC */ 327 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 328 if (err) { 329 error_propagate(errp, err); 330 return; 331 } 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 334 aspeed_soc_get_irq(s, ASPEED_RTC)); 335 336 /* Timer */ 337 object_property_set_link(OBJECT(&s->timerctrl), 338 OBJECT(&s->scu), "scu", &error_abort); 339 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 340 if (err) { 341 error_propagate(errp, err); 342 return; 343 } 344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 345 sc->memmap[ASPEED_TIMER1]); 346 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 347 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 349 } 350 351 /* UART - attach an 8250 to the IO space as our UART5 */ 352 if (serial_hd(0)) { 353 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 354 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 355 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 356 } 357 358 /* I2C */ 359 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 360 if (err) { 361 error_propagate(errp, err); 362 return; 363 } 364 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 365 if (err) { 366 error_propagate(errp, err); 367 return; 368 } 369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 370 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 371 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 372 sc->irqmap[ASPEED_I2C] + i); 373 /* 374 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 375 * IRQ (AST2400 and AST2500) and connect all bussses. 376 */ 377 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 378 } 379 380 /* FMC, The number of CS is set at the board level */ 381 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 382 if (err) { 383 error_propagate(errp, err); 384 return; 385 } 386 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 387 "sdram-base", &err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 393 if (err) { 394 error_propagate(errp, err); 395 return; 396 } 397 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 399 s->fmc.ctrl->flash_window_base); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 401 aspeed_soc_get_irq(s, ASPEED_FMC)); 402 403 /* SPI */ 404 for (i = 0; i < sc->spis_num; i++) { 405 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 406 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 407 &local_err); 408 error_propagate(&err, local_err); 409 if (err) { 410 error_propagate(errp, err); 411 return; 412 } 413 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 414 sc->memmap[ASPEED_SPI1 + i]); 415 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 416 s->spi[i].ctrl->flash_window_base); 417 } 418 419 /* SDMC - SDRAM Memory Controller */ 420 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 421 if (err) { 422 error_propagate(errp, err); 423 return; 424 } 425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 426 427 /* Watch dog */ 428 for (i = 0; i < sc->wdts_num; i++) { 429 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 430 431 object_property_set_link(OBJECT(&s->wdt[i]), 432 OBJECT(&s->scu), "scu", &error_abort); 433 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 434 if (err) { 435 error_propagate(errp, err); 436 return; 437 } 438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 439 sc->memmap[ASPEED_WDT] + i * awc->offset); 440 } 441 442 /* Net */ 443 for (i = 0; i < nb_nics && i < sc->macs_num; i++) { 444 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); 445 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 446 &err); 447 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 448 &local_err); 449 error_propagate(&err, local_err); 450 if (err) { 451 error_propagate(errp, err); 452 return; 453 } 454 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 455 sc->memmap[ASPEED_ETH1 + i]); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 457 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 458 459 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 460 "nic", &error_abort); 461 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 462 &err); 463 if (err) { 464 error_propagate(errp, err); 465 return; 466 } 467 468 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 469 sc->memmap[ASPEED_MII1 + i]); 470 } 471 472 /* XDMA */ 473 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 474 if (err) { 475 error_propagate(errp, err); 476 return; 477 } 478 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 479 sc->memmap[ASPEED_XDMA]); 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 481 aspeed_soc_get_irq(s, ASPEED_XDMA)); 482 483 /* GPIO */ 484 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 485 if (err) { 486 error_propagate(errp, err); 487 return; 488 } 489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 491 aspeed_soc_get_irq(s, ASPEED_GPIO)); 492 493 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 494 if (err) { 495 error_propagate(errp, err); 496 return; 497 } 498 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 499 sc->memmap[ASPEED_GPIO_1_8V]); 500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 501 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 502 503 /* SDHCI */ 504 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 505 if (err) { 506 error_propagate(errp, err); 507 return; 508 } 509 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 510 sc->memmap[ASPEED_SDHCI]); 511 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 512 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 513 514 /* eMMC */ 515 object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); 516 if (err) { 517 error_propagate(errp, err); 518 return; 519 } 520 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 521 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 522 aspeed_soc_get_irq(s, ASPEED_EMMC)); 523 } 524 525 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 526 { 527 DeviceClass *dc = DEVICE_CLASS(oc); 528 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 529 530 dc->realize = aspeed_soc_ast2600_realize; 531 532 sc->name = "ast2600-a0"; 533 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 534 sc->silicon_rev = AST2600_A0_SILICON_REV; 535 sc->sram_size = 0x10000; 536 sc->spis_num = 2; 537 sc->wdts_num = 4; 538 sc->macs_num = 4; 539 sc->irqmap = aspeed_soc_ast2600_irqmap; 540 sc->memmap = aspeed_soc_ast2600_memmap; 541 sc->num_cpus = 2; 542 } 543 544 static const TypeInfo aspeed_soc_ast2600_type_info = { 545 .name = "ast2600-a0", 546 .parent = TYPE_ASPEED_SOC, 547 .instance_size = sizeof(AspeedSoCState), 548 .instance_init = aspeed_soc_ast2600_init, 549 .class_init = aspeed_soc_ast2600_class_init, 550 .class_size = sizeof(AspeedSoCClass), 551 }; 552 553 static void aspeed_soc_register_types(void) 554 { 555 type_register_static(&aspeed_soc_ast2600_type_info); 556 }; 557 558 type_init(aspeed_soc_register_types) 559