1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "system/system.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_MII1] = 0x1E650000, 37 [ASPEED_DEV_MII2] = 0x1E650008, 38 [ASPEED_DEV_MII3] = 0x1E650010, 39 [ASPEED_DEV_MII4] = 0x1E650018, 40 [ASPEED_DEV_ETH1] = 0x1E660000, 41 [ASPEED_DEV_ETH3] = 0x1E670000, 42 [ASPEED_DEV_ETH2] = 0x1E680000, 43 [ASPEED_DEV_ETH4] = 0x1E690000, 44 [ASPEED_DEV_VIC] = 0x1E6C0000, 45 [ASPEED_DEV_HACE] = 0x1E6D0000, 46 [ASPEED_DEV_SDMC] = 0x1E6E0000, 47 [ASPEED_DEV_SCU] = 0x1E6E2000, 48 [ASPEED_DEV_GFX] = 0x1E6E6000, 49 [ASPEED_DEV_XDMA] = 0x1E6E7000, 50 [ASPEED_DEV_ADC] = 0x1E6E9000, 51 [ASPEED_DEV_DP] = 0x1E6EB000, 52 [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED200, 53 [ASPEED_DEV_SBC] = 0x1E6F2000, 54 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 55 [ASPEED_DEV_VIDEO] = 0x1E700000, 56 [ASPEED_DEV_SDHCI] = 0x1E740000, 57 [ASPEED_DEV_EMMC] = 0x1E750000, 58 [ASPEED_DEV_PCIE0] = 0x1E770000, 59 [ASPEED_DEV_GPIO] = 0x1E780000, 60 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 61 [ASPEED_DEV_RTC] = 0x1E781000, 62 [ASPEED_DEV_TIMER1] = 0x1E782000, 63 [ASPEED_DEV_WDT] = 0x1E785000, 64 [ASPEED_DEV_LPC] = 0x1E789000, 65 [ASPEED_DEV_IBT] = 0x1E789140, 66 [ASPEED_DEV_I2C] = 0x1E78A000, 67 [ASPEED_DEV_PECI] = 0x1E78B000, 68 [ASPEED_DEV_UART1] = 0x1E783000, 69 [ASPEED_DEV_UART2] = 0x1E78D000, 70 [ASPEED_DEV_UART3] = 0x1E78E000, 71 [ASPEED_DEV_UART4] = 0x1E78F000, 72 [ASPEED_DEV_UART5] = 0x1E784000, 73 [ASPEED_DEV_UART6] = 0x1E790000, 74 [ASPEED_DEV_UART7] = 0x1E790100, 75 [ASPEED_DEV_UART8] = 0x1E790200, 76 [ASPEED_DEV_UART9] = 0x1E790300, 77 [ASPEED_DEV_UART10] = 0x1E790400, 78 [ASPEED_DEV_UART11] = 0x1E790500, 79 [ASPEED_DEV_UART12] = 0x1E790600, 80 [ASPEED_DEV_UART13] = 0x1E790700, 81 [ASPEED_DEV_VUART] = 0x1E787000, 82 [ASPEED_DEV_FSI1] = 0x1E79B000, 83 [ASPEED_DEV_FSI2] = 0x1E79B100, 84 [ASPEED_DEV_I3C] = 0x1E7A0000, 85 [ASPEED_DEV_PCIE_MMIO1] = 0x70000000, 86 [ASPEED_DEV_SDRAM] = 0x80000000, 87 }; 88 89 #define ASPEED_A7MPCORE_ADDR 0x40460000 90 91 #define AST2600_MAX_IRQ 197 92 93 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 94 static const int aspeed_soc_ast2600_irqmap[] = { 95 [ASPEED_DEV_UART1] = 47, 96 [ASPEED_DEV_UART2] = 48, 97 [ASPEED_DEV_UART3] = 49, 98 [ASPEED_DEV_UART4] = 50, 99 [ASPEED_DEV_UART5] = 8, 100 [ASPEED_DEV_UART6] = 57, 101 [ASPEED_DEV_UART7] = 58, 102 [ASPEED_DEV_UART8] = 59, 103 [ASPEED_DEV_UART9] = 60, 104 [ASPEED_DEV_UART10] = 61, 105 [ASPEED_DEV_UART11] = 62, 106 [ASPEED_DEV_UART12] = 63, 107 [ASPEED_DEV_UART13] = 64, 108 [ASPEED_DEV_VUART] = 8, 109 [ASPEED_DEV_FMC] = 39, 110 [ASPEED_DEV_SDMC] = 0, 111 [ASPEED_DEV_SCU] = 12, 112 [ASPEED_DEV_ADC] = 78, 113 [ASPEED_DEV_GFX] = 14, 114 [ASPEED_DEV_XDMA] = 6, 115 [ASPEED_DEV_SDHCI] = 43, 116 [ASPEED_DEV_EHCI1] = 5, 117 [ASPEED_DEV_EHCI2] = 9, 118 [ASPEED_DEV_EMMC] = 15, 119 [ASPEED_DEV_GPIO] = 40, 120 [ASPEED_DEV_GPIO_1_8V] = 11, 121 [ASPEED_DEV_RTC] = 13, 122 [ASPEED_DEV_TIMER1] = 16, 123 [ASPEED_DEV_TIMER2] = 17, 124 [ASPEED_DEV_TIMER3] = 18, 125 [ASPEED_DEV_TIMER4] = 19, 126 [ASPEED_DEV_TIMER5] = 20, 127 [ASPEED_DEV_TIMER6] = 21, 128 [ASPEED_DEV_TIMER7] = 22, 129 [ASPEED_DEV_TIMER8] = 23, 130 [ASPEED_DEV_WDT] = 24, 131 [ASPEED_DEV_PWM] = 44, 132 [ASPEED_DEV_LPC] = 35, 133 [ASPEED_DEV_IBT] = 143, 134 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 135 [ASPEED_DEV_PCIE0] = 168, 136 [ASPEED_DEV_PECI] = 38, 137 [ASPEED_DEV_ETH1] = 2, 138 [ASPEED_DEV_ETH2] = 3, 139 [ASPEED_DEV_HACE] = 4, 140 [ASPEED_DEV_ETH3] = 32, 141 [ASPEED_DEV_ETH4] = 33, 142 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 143 [ASPEED_DEV_DP] = 62, 144 [ASPEED_DEV_FSI1] = 100, 145 [ASPEED_DEV_FSI2] = 101, 146 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 147 }; 148 149 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 150 { 151 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 153 154 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 155 } 156 157 static void aspeed_soc_ast2600_init(Object *obj) 158 { 159 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 160 AspeedSoCState *s = ASPEED_SOC(obj); 161 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 162 int i; 163 char socname[8]; 164 char typename[64]; 165 166 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 167 g_assert_not_reached(); 168 } 169 170 for (i = 0; i < sc->num_cpus; i++) { 171 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 172 aspeed_soc_cpu_type(sc)); 173 } 174 175 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 176 object_initialize_child(obj, "scu", &s->scu, typename); 177 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 178 sc->silicon_rev); 179 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 180 "hw-strap1"); 181 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 182 "hw-strap2"); 183 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 184 "hw-prot-key"); 185 186 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 187 TYPE_A15MPCORE_PRIV); 188 189 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 190 191 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 192 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 193 194 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 195 object_initialize_child(obj, "adc", &s->adc, typename); 196 197 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 198 object_initialize_child(obj, "i2c", &s->i2c, typename); 199 200 object_initialize_child(obj, "pcie-cfg", &s->pcie[0], TYPE_ASPEED_PCIE_CFG); 201 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[0], 202 TYPE_ASPEED_PCIE_PHY); 203 204 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 205 206 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 207 object_initialize_child(obj, "fmc", &s->fmc, typename); 208 209 for (i = 0; i < sc->spis_num; i++) { 210 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 211 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 212 } 213 214 for (i = 0; i < sc->ehcis_num; i++) { 215 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 216 TYPE_PLATFORM_EHCI); 217 } 218 219 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 220 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 221 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 222 "ram-size"); 223 224 for (i = 0; i < sc->wdts_num; i++) { 225 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 226 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 227 } 228 229 for (i = 0; i < sc->macs_num; i++) { 230 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 231 TYPE_FTGMAC100); 232 233 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 234 } 235 236 for (i = 0; i < sc->uarts_num; i++) { 237 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 238 } 239 240 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 241 object_initialize_child(obj, "xdma", &s->xdma, typename); 242 243 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 244 object_initialize_child(obj, "gpio", &s->gpio, typename); 245 246 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 247 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 248 249 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 250 object_initialize_child(obj, "sd-controller", &s->sdhci, typename); 251 252 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 253 254 /* Init sd card slot class here so that they're under the correct parent */ 255 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 256 object_initialize_child(obj, "sd-controller.sdhci[*]", 257 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 258 } 259 260 object_initialize_child(obj, "emmc-controller", &s->emmc, typename); 261 262 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 263 264 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 265 TYPE_SYSBUS_SDHCI); 266 267 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 268 269 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT); 270 271 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 272 object_initialize_child(obj, "hace", &s->hace, typename); 273 274 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 275 276 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); 277 278 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 279 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 280 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 281 object_initialize_child(obj, "emmc-boot-controller", 282 &s->emmc_boot_controller, 283 TYPE_UNIMPLEMENTED_DEVICE); 284 285 for (i = 0; i < ASPEED_FSI_NUM; i++) { 286 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 287 } 288 289 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 290 291 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 292 } 293 294 /* 295 * ASPEED ast2600 has 0xf as cluster ID 296 * 297 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 298 */ 299 static uint64_t aspeed_calc_affinity(int cpu) 300 { 301 return (0xf << ARM_AFF1_SHIFT) | cpu; 302 } 303 304 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 305 { 306 int i; 307 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 308 AspeedSoCState *s = ASPEED_SOC(dev); 309 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 310 qemu_irq irq; 311 g_autofree char *name = NULL; 312 MemoryRegion *mmio_alias; 313 MemoryRegion *mmio_mr; 314 315 /* Default boot region (SPI memory or ROMs) */ 316 memory_region_init(&s->spi_boot_container, OBJECT(s), 317 "aspeed.spi_boot_container", 0x10000000); 318 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 319 &s->spi_boot_container); 320 321 /* IO space */ 322 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 323 sc->memmap[ASPEED_DEV_IOMEM], 324 ASPEED_SOC_IOMEM_SIZE); 325 326 /* Video engine stub */ 327 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 328 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 329 330 /* eMMC Boot Controller stub */ 331 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 332 "aspeed.emmc-boot-controller", 333 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 334 335 /* CPU */ 336 for (i = 0; i < sc->num_cpus; i++) { 337 if (sc->num_cpus > 1) { 338 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 339 ASPEED_A7MPCORE_ADDR, &error_abort); 340 } 341 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 342 aspeed_calc_affinity(i), &error_abort); 343 344 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 345 &error_abort); 346 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 347 &error_abort); 348 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 349 &error_abort); 350 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 351 OBJECT(s->memory), &error_abort); 352 353 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 354 return; 355 } 356 } 357 358 /* A7MPCORE */ 359 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 360 &error_abort); 361 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 362 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 363 &error_abort); 364 365 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 366 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 367 368 for (i = 0; i < sc->num_cpus; i++) { 369 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 370 DeviceState *d = DEVICE(&a->cpu[i]); 371 372 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 373 sysbus_connect_irq(sbd, i, irq); 374 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 375 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 376 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 377 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 378 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 379 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 380 } 381 382 /* SRAM */ 383 name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 384 if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, 385 errp)) { 386 return; 387 } 388 memory_region_add_subregion(s->memory, 389 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 390 391 /* DPMCU */ 392 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 393 sc->memmap[ASPEED_DEV_DPMCU], 394 ASPEED_SOC_DPMCU_SIZE); 395 396 /* SCU */ 397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 398 return; 399 } 400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 401 402 /* RTC */ 403 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 404 return; 405 } 406 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 407 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 408 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 409 410 /* Timer */ 411 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 412 &error_abort); 413 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 414 return; 415 } 416 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 417 sc->memmap[ASPEED_DEV_TIMER1]); 418 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 419 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 421 } 422 423 /* ADC */ 424 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 425 return; 426 } 427 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 429 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 430 431 /* UART */ 432 if (!aspeed_soc_uart_realize(s, errp)) { 433 return; 434 } 435 436 /* I2C */ 437 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 438 &error_abort); 439 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 440 return; 441 } 442 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 443 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 444 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 445 sc->irqmap[ASPEED_DEV_I2C] + i); 446 /* The AST2600 I2C controller has one IRQ per bus. */ 447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 448 } 449 450 /* PECI */ 451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 452 return; 453 } 454 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 455 sc->memmap[ASPEED_DEV_PECI]); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 457 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 458 459 /* 460 * PCIe Root Complex (RC) 461 * 462 * H2X register space (single block 0x00-0xFF): 463 * 0x00-0x7F : shared by RC_L (PCIe0) and RC_H (PCIe1) 464 * 0x80-0xBF : RC_L only 465 * 0xC0-0xFF : RC_H only 466 * 467 * Model scope / limitations: 468 * - Firmware supports RC_H only; this QEMU model does not support RC_L. 469 * - RC_H uses PHY1 and the MMIO window [0x70000000, 0x80000000] 470 * (aka MMIO1). 471 * 472 * Indexing convention (this model): 473 * - Expose a single logical instance at index 0. 474 * - pcie[0] -> hardware RC_H (PCIe1) 475 * - phy[0] -> hardware PHY1 476 * - mmio.0 -> guest address range MMIO1: 0x70000000-0x80000000 477 * - RC_L / PCIe0 is not created and mapped. 478 */ 479 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[0]), errp)) { 480 return; 481 } 482 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[0]), 0, 483 sc->memmap[ASPEED_DEV_PCIE_PHY1]); 484 485 object_property_set_int(OBJECT(&s->pcie[0]), "dram-base", 486 sc->memmap[ASPEED_DEV_SDRAM], 487 &error_abort); 488 object_property_set_link(OBJECT(&s->pcie[0]), "dram", OBJECT(s->dram_mr), 489 &error_abort); 490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[0]), errp)) { 491 return; 492 } 493 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie[0]), 0, 494 sc->memmap[ASPEED_DEV_PCIE0]); 495 496 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 497 sc->irqmap[ASPEED_DEV_PCIE0]); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[0].rc), 0, irq); 499 500 name = g_strdup_printf("aspeed.pcie-mmio.0"); 501 502 mmio_alias = g_new0(MemoryRegion, 1); 503 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[0].rc), 1); 504 505 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie[0].rc), name, 506 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1], 507 0x10000000); 508 memory_region_add_subregion(s->memory, 509 sc->memmap[ASPEED_DEV_PCIE_MMIO1], 510 mmio_alias); 511 512 /* FMC, The number of CS is set at the board level */ 513 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 514 &error_abort); 515 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 516 return; 517 } 518 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 519 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 520 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 521 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 522 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 523 524 /* Set up an alias on the FMC CE0 region (boot default) */ 525 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 526 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 527 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 528 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 529 530 /* SPI */ 531 for (i = 0; i < sc->spis_num; i++) { 532 object_property_set_link(OBJECT(&s->spi[i]), "dram", 533 OBJECT(s->dram_mr), &error_abort); 534 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 535 return; 536 } 537 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 538 sc->memmap[ASPEED_DEV_SPI1 + i]); 539 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 540 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 541 } 542 543 /* EHCI */ 544 for (i = 0; i < sc->ehcis_num; i++) { 545 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 546 return; 547 } 548 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 549 sc->memmap[ASPEED_DEV_EHCI1 + i]); 550 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 551 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 552 } 553 554 /* SDMC - SDRAM Memory Controller */ 555 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 556 return; 557 } 558 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 559 sc->memmap[ASPEED_DEV_SDMC]); 560 561 /* Watch dog */ 562 for (i = 0; i < sc->wdts_num; i++) { 563 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 564 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 565 566 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 567 &error_abort); 568 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 569 return; 570 } 571 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 572 } 573 574 /* RAM */ 575 if (!aspeed_soc_dram_init(s, errp)) { 576 return; 577 } 578 579 /* Net */ 580 for (i = 0; i < sc->macs_num; i++) { 581 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 582 &error_abort); 583 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 584 return; 585 } 586 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 587 sc->memmap[ASPEED_DEV_ETH1 + i]); 588 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 589 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 590 591 object_property_set_link(OBJECT(&s->mii[i]), "nic", 592 OBJECT(&s->ftgmac100[i]), &error_abort); 593 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 594 return; 595 } 596 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 598 sc->memmap[ASPEED_DEV_MII1 + i]); 599 } 600 601 /* XDMA */ 602 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 603 return; 604 } 605 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 606 sc->memmap[ASPEED_DEV_XDMA]); 607 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 608 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 609 610 /* GPIO */ 611 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 612 return; 613 } 614 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 615 sc->memmap[ASPEED_DEV_GPIO]); 616 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 617 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 618 619 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 620 return; 621 } 622 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 623 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 624 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 625 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 626 627 /* SDHCI */ 628 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 629 return; 630 } 631 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 632 sc->memmap[ASPEED_DEV_SDHCI]); 633 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 634 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 635 636 /* eMMC */ 637 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 638 return; 639 } 640 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 641 sc->memmap[ASPEED_DEV_EMMC]); 642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 643 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 644 645 /* LPC */ 646 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 647 return; 648 } 649 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 650 651 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 652 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 653 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 654 655 /* 656 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 657 * 658 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 659 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 660 * shared across the subdevices, and the shared IRQ output to the VIC is at 661 * offset 0. 662 */ 663 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 664 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 665 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 666 667 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 668 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 669 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 670 671 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 672 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 673 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 674 675 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 676 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 677 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 678 679 /* iBT */ 680 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) { 681 return; 682 } 683 memory_region_add_subregion(&s->lpc.iomem, 684 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC], 685 &s->ibt.iomem); 686 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ibt), 0, 687 aspeed_soc_get_irq(s, ASPEED_DEV_IBT)); 688 689 /* HACE */ 690 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 691 &error_abort); 692 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 693 return; 694 } 695 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 696 sc->memmap[ASPEED_DEV_HACE]); 697 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 698 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 699 700 /* I3C */ 701 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 702 return; 703 } 704 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 705 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 706 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 707 sc->irqmap[ASPEED_DEV_I3C] + i); 708 /* The AST2600 I3C controller has one IRQ per bus. */ 709 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 710 } 711 712 /* Secure Boot Controller */ 713 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 714 return; 715 } 716 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 717 718 /* FSI */ 719 for (i = 0; i < ASPEED_FSI_NUM; i++) { 720 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 721 return; 722 } 723 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 724 sc->memmap[ASPEED_DEV_FSI1 + i]); 725 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 726 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 727 } 728 729 /* GFX */ 730 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 731 return; 732 } 733 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 734 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 735 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 736 737 /* PWM */ 738 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 739 return; 740 } 741 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 742 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 743 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 744 } 745 746 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 747 { 748 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 749 "hw-strap1", &error_abort); 750 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 751 } 752 753 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data) 754 { 755 static const char * const valid_cpu_types[] = { 756 ARM_CPU_TYPE_NAME("cortex-a7"), 757 NULL 758 }; 759 DeviceClass *dc = DEVICE_CLASS(oc); 760 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 761 762 dc->realize = aspeed_soc_ast2600_realize; 763 /* Reason: The Aspeed SoC can only be instantiated from a board */ 764 dc->user_creatable = false; 765 766 sc->valid_cpu_types = valid_cpu_types; 767 sc->silicon_rev = AST2600_A3_SILICON_REV; 768 sc->sram_size = 0x16400; 769 sc->spis_num = 2; 770 sc->ehcis_num = 2; 771 sc->wdts_num = 4; 772 sc->macs_num = 4; 773 sc->uarts_num = 13; 774 sc->uarts_base = ASPEED_DEV_UART1; 775 sc->irqmap = aspeed_soc_ast2600_irqmap; 776 sc->memmap = aspeed_soc_ast2600_memmap; 777 sc->num_cpus = 2; 778 sc->get_irq = aspeed_soc_ast2600_get_irq; 779 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 780 } 781 782 static const TypeInfo aspeed_soc_ast2600_types[] = { 783 { 784 .name = TYPE_ASPEED2600_SOC, 785 .parent = TYPE_ASPEED_SOC, 786 .instance_size = sizeof(Aspeed2600SoCState), 787 .abstract = true, 788 }, { 789 .name = "ast2600-a3", 790 .parent = TYPE_ASPEED2600_SOC, 791 .instance_init = aspeed_soc_ast2600_init, 792 .class_init = aspeed_soc_ast2600_class_init, 793 }, 794 }; 795 796 DEFINE_TYPES(aspeed_soc_ast2600_types) 797