1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_UHCI] = 0x1E6B0000, 37 [ASPEED_DEV_MII1] = 0x1E650000, 38 [ASPEED_DEV_MII2] = 0x1E650008, 39 [ASPEED_DEV_MII3] = 0x1E650010, 40 [ASPEED_DEV_MII4] = 0x1E650018, 41 [ASPEED_DEV_ETH1] = 0x1E660000, 42 [ASPEED_DEV_ETH3] = 0x1E670000, 43 [ASPEED_DEV_ETH2] = 0x1E680000, 44 [ASPEED_DEV_ETH4] = 0x1E690000, 45 [ASPEED_DEV_VIC] = 0x1E6C0000, 46 [ASPEED_DEV_HACE] = 0x1E6D0000, 47 [ASPEED_DEV_SDMC] = 0x1E6E0000, 48 [ASPEED_DEV_SCU] = 0x1E6E2000, 49 [ASPEED_DEV_GFX] = 0x1E6E6000, 50 [ASPEED_DEV_XDMA] = 0x1E6E7000, 51 [ASPEED_DEV_ADC] = 0x1E6E9000, 52 [ASPEED_DEV_DP] = 0x1E6EB000, 53 [ASPEED_DEV_PCIE_PHY1] = 0x1E6ED000, 54 [ASPEED_DEV_PCIE_PHY2] = 0x1E6ED200, 55 [ASPEED_DEV_SBC] = 0x1E6F2000, 56 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 57 [ASPEED_DEV_VIDEO] = 0x1E700000, 58 [ASPEED_DEV_SDHCI] = 0x1E740000, 59 [ASPEED_DEV_EMMC] = 0x1E750000, 60 [ASPEED_DEV_PCIE] = 0x1E770000, 61 [ASPEED_DEV_GPIO] = 0x1E780000, 62 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 63 [ASPEED_DEV_RTC] = 0x1E781000, 64 [ASPEED_DEV_TIMER1] = 0x1E782000, 65 [ASPEED_DEV_WDT] = 0x1E785000, 66 [ASPEED_DEV_LPC] = 0x1E789000, 67 [ASPEED_DEV_IBT] = 0x1E789140, 68 [ASPEED_DEV_I2C] = 0x1E78A000, 69 [ASPEED_DEV_PECI] = 0x1E78B000, 70 [ASPEED_DEV_UART1] = 0x1E783000, 71 [ASPEED_DEV_UART2] = 0x1E78D000, 72 [ASPEED_DEV_UART3] = 0x1E78E000, 73 [ASPEED_DEV_UART4] = 0x1E78F000, 74 [ASPEED_DEV_UART5] = 0x1E784000, 75 [ASPEED_DEV_UART6] = 0x1E790000, 76 [ASPEED_DEV_UART7] = 0x1E790100, 77 [ASPEED_DEV_UART8] = 0x1E790200, 78 [ASPEED_DEV_UART9] = 0x1E790300, 79 [ASPEED_DEV_UART10] = 0x1E790400, 80 [ASPEED_DEV_UART11] = 0x1E790500, 81 [ASPEED_DEV_UART12] = 0x1E790600, 82 [ASPEED_DEV_UART13] = 0x1E790700, 83 [ASPEED_DEV_VUART] = 0x1E787000, 84 [ASPEED_DEV_FSI1] = 0x1E79B000, 85 [ASPEED_DEV_FSI2] = 0x1E79B100, 86 [ASPEED_DEV_I3C] = 0x1E7A0000, 87 [ASPEED_DEV_PCIE_MMIO1] = 0x60000000, 88 [ASPEED_DEV_PCIE_MMIO2] = 0x70000000, 89 [ASPEED_DEV_SDRAM] = 0x80000000, 90 }; 91 92 #define ASPEED_A7MPCORE_ADDR 0x40460000 93 94 #define AST2600_MAX_IRQ 197 95 96 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 97 static const int aspeed_soc_ast2600_irqmap[] = { 98 [ASPEED_DEV_UART1] = 47, 99 [ASPEED_DEV_UART2] = 48, 100 [ASPEED_DEV_UART3] = 49, 101 [ASPEED_DEV_UART4] = 50, 102 [ASPEED_DEV_UART5] = 8, 103 [ASPEED_DEV_UART6] = 57, 104 [ASPEED_DEV_UART7] = 58, 105 [ASPEED_DEV_UART8] = 59, 106 [ASPEED_DEV_UART9] = 60, 107 [ASPEED_DEV_UART10] = 61, 108 [ASPEED_DEV_UART11] = 62, 109 [ASPEED_DEV_UART12] = 63, 110 [ASPEED_DEV_UART13] = 64, 111 [ASPEED_DEV_VUART] = 8, 112 [ASPEED_DEV_FMC] = 39, 113 [ASPEED_DEV_SDMC] = 0, 114 [ASPEED_DEV_SCU] = 12, 115 [ASPEED_DEV_ADC] = 78, 116 [ASPEED_DEV_GFX] = 14, 117 [ASPEED_DEV_XDMA] = 6, 118 [ASPEED_DEV_SDHCI] = 43, 119 [ASPEED_DEV_EHCI1] = 5, 120 [ASPEED_DEV_EHCI2] = 9, 121 [ASPEED_DEV_UHCI] = 10, 122 [ASPEED_DEV_EMMC] = 15, 123 [ASPEED_DEV_GPIO] = 40, 124 [ASPEED_DEV_GPIO_1_8V] = 11, 125 [ASPEED_DEV_RTC] = 13, 126 [ASPEED_DEV_TIMER1] = 16, 127 [ASPEED_DEV_TIMER2] = 17, 128 [ASPEED_DEV_TIMER3] = 18, 129 [ASPEED_DEV_TIMER4] = 19, 130 [ASPEED_DEV_TIMER5] = 20, 131 [ASPEED_DEV_TIMER6] = 21, 132 [ASPEED_DEV_TIMER7] = 22, 133 [ASPEED_DEV_TIMER8] = 23, 134 [ASPEED_DEV_WDT] = 24, 135 [ASPEED_DEV_PWM] = 44, 136 [ASPEED_DEV_LPC] = 35, 137 [ASPEED_DEV_IBT] = 143, 138 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 139 [ASPEED_DEV_PCIE] = 167, /* 167 -> 168 */ 140 [ASPEED_DEV_PECI] = 38, 141 [ASPEED_DEV_ETH1] = 2, 142 [ASPEED_DEV_ETH2] = 3, 143 [ASPEED_DEV_HACE] = 4, 144 [ASPEED_DEV_ETH3] = 32, 145 [ASPEED_DEV_ETH4] = 33, 146 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 147 [ASPEED_DEV_DP] = 62, 148 [ASPEED_DEV_FSI1] = 100, 149 [ASPEED_DEV_FSI2] = 101, 150 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 151 }; 152 153 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 154 { 155 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 156 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 157 158 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 159 } 160 161 static void aspeed_soc_ast2600_init(Object *obj) 162 { 163 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 164 AspeedSoCState *s = ASPEED_SOC(obj); 165 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 166 int i; 167 char socname[8]; 168 char typename[64]; 169 170 if (sscanf(sc->name, "%7s", socname) != 1) { 171 g_assert_not_reached(); 172 } 173 174 for (i = 0; i < sc->num_cpus; i++) { 175 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 176 aspeed_soc_cpu_type(sc)); 177 } 178 179 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 180 object_initialize_child(obj, "scu", &s->scu, typename); 181 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 182 sc->silicon_rev); 183 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 184 "hw-strap1"); 185 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 186 "hw-strap2"); 187 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 188 "hw-prot-key"); 189 190 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 191 TYPE_A15MPCORE_PRIV); 192 193 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 194 195 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 196 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 197 198 for (i = 0; i < sc->wdts_num; i++) { 199 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 200 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 201 } 202 203 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 204 object_initialize_child(obj, "adc", &s->adc, typename); 205 206 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 207 object_initialize_child(obj, "i2c", &s->i2c, typename); 208 209 object_initialize_child(obj, "pcie-rc", &s->pcie, TYPE_ASPEED_PCIE_CFG); 210 211 for (i = 0; i < ARRAY_SIZE(s->pcie_phy); i++) { 212 object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i], 213 TYPE_ASPEED_PCIE_PHY); 214 } 215 216 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 217 218 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 219 object_initialize_child(obj, "fmc", &s->fmc, typename); 220 221 for (i = 0; i < sc->spis_num; i++) { 222 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 223 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 224 } 225 226 for (i = 0; i < sc->ehcis_num; i++) { 227 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 228 TYPE_PLATFORM_EHCI); 229 } 230 231 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 232 233 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 234 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 235 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 236 "ram-size"); 237 238 for (i = 0; i < sc->macs_num; i++) { 239 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 240 TYPE_FTGMAC100); 241 242 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 243 } 244 245 for (i = 0; i < sc->uarts_num; i++) { 246 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 247 } 248 249 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 250 object_initialize_child(obj, "xdma", &s->xdma, typename); 251 252 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 253 object_initialize_child(obj, "gpio", &s->gpio, typename); 254 255 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 256 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 257 258 object_initialize_child(obj, "sd-controller", &s->sdhci, 259 TYPE_ASPEED_SDHCI); 260 261 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 262 263 /* Init sd card slot class here so that they're under the correct parent */ 264 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 265 object_initialize_child(obj, "sd-controller.sdhci[*]", 266 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 267 } 268 269 object_initialize_child(obj, "emmc-controller", &s->emmc, 270 TYPE_ASPEED_SDHCI); 271 272 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 273 274 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 275 TYPE_SYSBUS_SDHCI); 276 277 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 278 279 object_initialize_child(obj, "ibt", &s->ibt, TYPE_ASPEED_IBT); 280 281 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 282 object_initialize_child(obj, "hace", &s->hace, typename); 283 284 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 285 286 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 287 288 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 289 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 290 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 291 object_initialize_child(obj, "emmc-boot-controller", 292 &s->emmc_boot_controller, 293 TYPE_UNIMPLEMENTED_DEVICE); 294 295 for (i = 0; i < ASPEED_FSI_NUM; i++) { 296 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 297 } 298 299 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 300 301 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 302 } 303 304 /* 305 * ASPEED ast2600 has 0xf as cluster ID 306 * 307 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 308 */ 309 static uint64_t aspeed_calc_affinity(int cpu) 310 { 311 return (0xf << ARM_AFF1_SHIFT) | cpu; 312 } 313 314 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 315 { 316 int i; 317 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 318 AspeedSoCState *s = ASPEED_SOC(dev); 319 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 320 qemu_irq irq; 321 g_autofree char *sram_name = NULL; 322 g_autofree char *usb_bus = g_strdup_printf("usb-bus.%u", sc->ehcis_num - 1); 323 324 /* Default boot region (SPI memory or ROMs) */ 325 memory_region_init(&s->spi_boot_container, OBJECT(s), 326 "aspeed.spi_boot_container", 0x10000000); 327 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 328 &s->spi_boot_container); 329 330 /* IO space */ 331 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 332 sc->memmap[ASPEED_DEV_IOMEM], 333 ASPEED_SOC_IOMEM_SIZE); 334 335 /* Video engine stub */ 336 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 337 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 338 339 /* eMMC Boot Controller stub */ 340 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 341 "aspeed.emmc-boot-controller", 342 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 343 344 /* CPU */ 345 for (i = 0; i < sc->num_cpus; i++) { 346 if (sc->num_cpus > 1) { 347 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 348 ASPEED_A7MPCORE_ADDR, &error_abort); 349 } 350 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 351 aspeed_calc_affinity(i), &error_abort); 352 353 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 354 &error_abort); 355 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 356 &error_abort); 357 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 358 &error_abort); 359 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 360 OBJECT(s->memory), &error_abort); 361 362 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 363 return; 364 } 365 } 366 367 /* A7MPCORE */ 368 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 369 &error_abort); 370 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 371 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 372 &error_abort); 373 374 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 375 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 376 377 for (i = 0; i < sc->num_cpus; i++) { 378 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 379 DeviceState *d = DEVICE(&a->cpu[i]); 380 381 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 382 sysbus_connect_irq(sbd, i, irq); 383 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 384 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 385 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 386 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 387 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 388 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 389 } 390 391 /* SRAM */ 392 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 393 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 394 errp)) { 395 return; 396 } 397 memory_region_add_subregion(s->memory, 398 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 399 400 /* DPMCU */ 401 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 402 sc->memmap[ASPEED_DEV_DPMCU], 403 ASPEED_SOC_DPMCU_SIZE); 404 405 /* SCU */ 406 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 407 return; 408 } 409 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 410 411 /* RTC */ 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 413 return; 414 } 415 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 417 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 418 419 /* Timer */ 420 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 421 &error_abort); 422 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 423 return; 424 } 425 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 426 sc->memmap[ASPEED_DEV_TIMER1]); 427 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 428 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 430 } 431 432 /* Watch dog */ 433 for (i = 0; i < sc->wdts_num; i++) { 434 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 435 436 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 437 &error_abort); 438 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 439 return; 440 } 441 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 442 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 443 } 444 445 /* ADC */ 446 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 447 return; 448 } 449 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 450 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 451 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 452 453 /* UART */ 454 if (!aspeed_soc_uart_realize(s, errp)) { 455 return; 456 } 457 458 /* I2C */ 459 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 460 &error_abort); 461 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 462 return; 463 } 464 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 465 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 466 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 467 sc->irqmap[ASPEED_DEV_I2C] + i); 468 /* The AST2600 I2C controller has one IRQ per bus. */ 469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 470 } 471 472 /* PECI */ 473 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 474 return; 475 } 476 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 477 sc->memmap[ASPEED_DEV_PECI]); 478 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 479 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 480 481 /* PCIe */ 482 for (i = 0; i < ARRAY_SIZE(s->pcie_phy); i++) { 483 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) { 484 return; 485 } 486 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0, 487 sc->memmap[ASPEED_DEV_PCIE_PHY1 + i]); 488 } 489 490 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { 491 return; 492 } 493 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pcie), 0, 494 sc->memmap[ASPEED_DEV_PCIE]); 495 496 for (i = 0; i < ARRAY_SIZE(s->pcie.rcs); i++) { 497 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 498 sc->irqmap[ASPEED_DEV_PCIE] + i); 499 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie.rcs[i]), 0, irq); 500 } 501 502 for (i = 0; i < ARRAY_SIZE(s->pcie.rcs); i++) { 503 g_autofree char *name = g_strdup_printf("pcie-mmio-%d", i); 504 MemoryRegion *mmio_alias; 505 MemoryRegion *mmio_mr; 506 507 mmio_alias = g_new0(MemoryRegion, 1); 508 mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie.rcs[i]), 1); 509 510 memory_region_init_alias(mmio_alias, OBJECT(&s->pcie.rcs[i]), name, 511 mmio_mr, sc->memmap[ASPEED_DEV_PCIE_MMIO1 + i], 512 0x10000000); 513 514 memory_region_add_subregion(s->memory, 515 sc->memmap[ASPEED_DEV_PCIE_MMIO1 + i], 516 mmio_alias); 517 } 518 519 /* FMC, The number of CS is set at the board level */ 520 object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].iomem), 521 &error_abort); 522 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 523 &error_abort); 524 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 525 return; 526 } 527 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 528 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 529 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 530 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 531 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 532 533 /* Set up an alias on the FMC CE0 region (boot default) */ 534 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 535 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 536 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 537 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 538 539 /* SPI */ 540 for (i = 0; i < sc->spis_num; i++) { 541 object_property_set_link(OBJECT(&s->spi[i]), "dram", 542 OBJECT(s->dram_mr), &error_abort); 543 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 544 return; 545 } 546 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 547 sc->memmap[ASPEED_DEV_SPI1 + i]); 548 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 549 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 550 } 551 552 /* EHCI */ 553 for (i = 0; i < sc->ehcis_num; i++) { 554 if (i == sc->ehcis_num - 1) { 555 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 556 true, &error_fatal); 557 } 558 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 559 return; 560 } 561 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 562 sc->memmap[ASPEED_DEV_EHCI1 + i]); 563 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 564 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 565 } 566 567 /* UHCI */ 568 object_property_set_str(OBJECT(&s->uhci), "masterbus", usb_bus, 569 &error_fatal); 570 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 571 return; 572 } 573 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 574 sc->memmap[ASPEED_DEV_UHCI]); 575 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 576 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 577 578 /* SDMC - SDRAM Memory Controller */ 579 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 580 return; 581 } 582 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 583 sc->memmap[ASPEED_DEV_SDMC]); 584 585 /* RAM */ 586 if (!aspeed_soc_dram_init(s, errp)) { 587 return; 588 } 589 590 /* Net */ 591 for (i = 0; i < sc->macs_num; i++) { 592 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 593 &error_abort); 594 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 595 return; 596 } 597 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 598 sc->memmap[ASPEED_DEV_ETH1 + i]); 599 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 600 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 601 602 object_property_set_link(OBJECT(&s->mii[i]), "nic", 603 OBJECT(&s->ftgmac100[i]), &error_abort); 604 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 605 return; 606 } 607 608 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 609 sc->memmap[ASPEED_DEV_MII1 + i]); 610 } 611 612 /* XDMA */ 613 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 614 return; 615 } 616 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 617 sc->memmap[ASPEED_DEV_XDMA]); 618 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 619 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 620 621 /* GPIO */ 622 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 623 return; 624 } 625 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 626 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 627 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 628 629 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 630 return; 631 } 632 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 633 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 635 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 636 637 /* SDHCI */ 638 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 639 return; 640 } 641 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 642 sc->memmap[ASPEED_DEV_SDHCI]); 643 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 644 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 645 646 /* eMMC */ 647 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 648 return; 649 } 650 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 651 sc->memmap[ASPEED_DEV_EMMC]); 652 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 653 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 654 655 /* LPC */ 656 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 657 return; 658 } 659 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 660 661 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 662 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 663 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 664 665 /* 666 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 667 * 668 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 669 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 670 * shared across the subdevices, and the shared IRQ output to the VIC is at 671 * offset 0. 672 */ 673 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 674 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 675 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 676 677 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 678 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 679 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 680 681 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 682 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 683 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 684 685 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 686 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 687 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 688 689 /* iBT */ 690 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ibt), errp)) { 691 return; 692 } 693 memory_region_add_subregion(&s->lpc.iomem, 694 sc->memmap[ASPEED_DEV_IBT] - sc->memmap[ASPEED_DEV_LPC], 695 &s->ibt.iomem); 696 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ibt), 0, 697 aspeed_soc_get_irq(s, ASPEED_DEV_IBT)); 698 699 /* HACE */ 700 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 701 &error_abort); 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 703 return; 704 } 705 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 706 sc->memmap[ASPEED_DEV_HACE]); 707 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 708 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 709 710 /* I3C */ 711 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 712 return; 713 } 714 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 715 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 716 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 717 sc->irqmap[ASPEED_DEV_I3C] + i); 718 /* The AST2600 I3C controller has one IRQ per bus. */ 719 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 720 } 721 722 /* Secure Boot Controller */ 723 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 724 return; 725 } 726 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 727 728 /* FSI */ 729 for (i = 0; i < ASPEED_FSI_NUM; i++) { 730 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 731 return; 732 } 733 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 734 sc->memmap[ASPEED_DEV_FSI1 + i]); 735 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 736 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 737 } 738 739 /* GFX */ 740 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 741 return; 742 } 743 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 744 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 745 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 746 747 /* PWM */ 748 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 749 return; 750 } 751 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 752 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 753 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 754 } 755 756 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 757 { 758 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 759 "hw-strap1", &error_abort); 760 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 761 } 762 763 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 764 { 765 static const char * const valid_cpu_types[] = { 766 ARM_CPU_TYPE_NAME("cortex-a7"), 767 NULL 768 }; 769 DeviceClass *dc = DEVICE_CLASS(oc); 770 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 771 772 dc->realize = aspeed_soc_ast2600_realize; 773 /* Reason: The Aspeed SoC can only be instantiated from a board */ 774 dc->user_creatable = false; 775 776 sc->name = "ast2600-a3"; 777 sc->valid_cpu_types = valid_cpu_types; 778 sc->silicon_rev = AST2600_A3_SILICON_REV; 779 sc->sram_size = 0x16400; 780 sc->spis_num = 2; 781 sc->ehcis_num = 2; 782 sc->wdts_num = 4; 783 sc->macs_num = 4; 784 sc->uarts_num = 13; 785 sc->uarts_base = ASPEED_DEV_UART1; 786 sc->irqmap = aspeed_soc_ast2600_irqmap; 787 sc->memmap = aspeed_soc_ast2600_memmap; 788 sc->num_cpus = 2; 789 sc->get_irq = aspeed_soc_ast2600_get_irq; 790 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 791 } 792 793 static const TypeInfo aspeed_soc_ast2600_types[] = { 794 { 795 .name = TYPE_ASPEED2600_SOC, 796 .parent = TYPE_ASPEED_SOC, 797 .instance_size = sizeof(Aspeed2600SoCState), 798 .abstract = true, 799 }, { 800 .name = "ast2600-a3", 801 .parent = TYPE_ASPEED2600_SOC, 802 .instance_init = aspeed_soc_ast2600_init, 803 .class_init = aspeed_soc_ast2600_class_init, 804 }, 805 }; 806 807 DEFINE_TYPES(aspeed_soc_ast2600_types) 808