1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 object_initialize_child(obj, "scu", &s->scu, typename); 135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 136 sc->silicon_rev); 137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 138 "hw-strap1"); 139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 140 "hw-strap2"); 141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 142 "hw-prot-key"); 143 144 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 145 TYPE_A15MPCORE_PRIV); 146 147 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 148 149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 150 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 151 152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 153 object_initialize_child(obj, "i2c", &s->i2c, typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 156 object_initialize_child(obj, "fmc", &s->fmc, typename); 157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 158 159 for (i = 0; i < sc->spis_num; i++) { 160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 161 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 162 } 163 164 for (i = 0; i < sc->ehcis_num; i++) { 165 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 166 TYPE_PLATFORM_EHCI); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 171 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 172 "ram-size"); 173 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 174 "max-ram-size"); 175 176 for (i = 0; i < sc->wdts_num; i++) { 177 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 178 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 179 } 180 181 for (i = 0; i < sc->macs_num; i++) { 182 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 183 TYPE_FTGMAC100); 184 185 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 186 } 187 188 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 191 object_initialize_child(obj, "gpio", &s->gpio, typename); 192 193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 195 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 TYPE_ASPEED_SDHCI); 198 199 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 200 201 /* Init sd card slot class here so that they're under the correct parent */ 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 203 object_initialize_child(obj, "sd-controller.sdhci[*]", 204 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 205 } 206 207 object_initialize_child(obj, "emmc-controller", &s->emmc, 208 TYPE_ASPEED_SDHCI); 209 210 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 211 212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 213 TYPE_SYSBUS_SDHCI); 214 } 215 216 /* 217 * ASPEED ast2600 has 0xf as cluster ID 218 * 219 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 220 */ 221 static uint64_t aspeed_calc_affinity(int cpu) 222 { 223 return (0xf << ARM_AFF1_SHIFT) | cpu; 224 } 225 226 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 227 { 228 int i; 229 AspeedSoCState *s = ASPEED_SOC(dev); 230 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 231 Error *err = NULL; 232 qemu_irq irq; 233 234 /* IO space */ 235 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 236 ASPEED_SOC_IOMEM_SIZE); 237 238 /* Video engine stub */ 239 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 240 0x1000); 241 242 /* CPU */ 243 for (i = 0; i < sc->num_cpus; i++) { 244 object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit", 245 QEMU_PSCI_CONDUIT_SMC, &error_abort); 246 if (sc->num_cpus > 1) { 247 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 248 ASPEED_A7MPCORE_ADDR, &error_abort); 249 } 250 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 251 aspeed_calc_affinity(i), &error_abort); 252 253 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 254 &error_abort); 255 256 /* 257 * TODO: the secondary CPUs are started and a boot helper 258 * is needed when using -kernel 259 */ 260 261 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, &err)) { 262 error_propagate(errp, err); 263 return; 264 } 265 } 266 267 /* A7MPCORE */ 268 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 269 &error_abort); 270 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 271 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 272 &error_abort); 273 274 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 276 277 for (i = 0; i < sc->num_cpus; i++) { 278 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 279 DeviceState *d = DEVICE(qemu_get_cpu(i)); 280 281 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 282 sysbus_connect_irq(sbd, i, irq); 283 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 284 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 285 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 286 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 287 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 288 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 289 } 290 291 /* SRAM */ 292 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 293 sc->sram_size, &err); 294 if (err) { 295 error_propagate(errp, err); 296 return; 297 } 298 memory_region_add_subregion(get_system_memory(), 299 sc->memmap[ASPEED_SRAM], &s->sram); 300 301 /* SCU */ 302 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err)) { 303 error_propagate(errp, err); 304 return; 305 } 306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 307 308 /* RTC */ 309 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err)) { 310 error_propagate(errp, err); 311 return; 312 } 313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 315 aspeed_soc_get_irq(s, ASPEED_RTC)); 316 317 /* Timer */ 318 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 319 &error_abort); 320 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err)) { 321 error_propagate(errp, err); 322 return; 323 } 324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 325 sc->memmap[ASPEED_TIMER1]); 326 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 327 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 329 } 330 331 /* UART - attach an 8250 to the IO space as our UART5 */ 332 if (serial_hd(0)) { 333 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 334 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 335 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 336 } 337 338 /* I2C */ 339 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 340 &error_abort); 341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err)) { 342 error_propagate(errp, err); 343 return; 344 } 345 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 346 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 347 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 348 sc->irqmap[ASPEED_I2C] + i); 349 /* 350 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 351 * IRQ (AST2400 and AST2500) and connect all bussses. 352 */ 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 354 } 355 356 /* FMC, The number of CS is set at the board level */ 357 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 358 &error_abort); 359 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", 360 sc->memmap[ASPEED_SDRAM], &err)) { 361 error_propagate(errp, err); 362 return; 363 } 364 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err)) { 365 error_propagate(errp, err); 366 return; 367 } 368 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 370 s->fmc.ctrl->flash_window_base); 371 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 372 aspeed_soc_get_irq(s, ASPEED_FMC)); 373 374 /* SPI */ 375 for (i = 0; i < sc->spis_num; i++) { 376 object_property_set_link(OBJECT(&s->spi[i]), "dram", 377 OBJECT(s->dram_mr), &error_abort); 378 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 379 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) { 380 error_propagate(errp, err); 381 return; 382 } 383 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 384 sc->memmap[ASPEED_SPI1 + i]); 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 386 s->spi[i].ctrl->flash_window_base); 387 } 388 389 /* EHCI */ 390 for (i = 0; i < sc->ehcis_num; i++) { 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err)) { 392 error_propagate(errp, err); 393 return; 394 } 395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 396 sc->memmap[ASPEED_EHCI1 + i]); 397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 398 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 399 } 400 401 /* SDMC - SDRAM Memory Controller */ 402 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err)) { 403 error_propagate(errp, err); 404 return; 405 } 406 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 407 408 /* Watch dog */ 409 for (i = 0; i < sc->wdts_num; i++) { 410 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 411 412 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 413 &error_abort); 414 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err)) { 415 error_propagate(errp, err); 416 return; 417 } 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 419 sc->memmap[ASPEED_WDT] + i * awc->offset); 420 } 421 422 /* Net */ 423 for (i = 0; i < sc->macs_num; i++) { 424 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 425 &error_abort); 426 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &err)) { 427 error_propagate(errp, err); 428 return; 429 } 430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 431 sc->memmap[ASPEED_ETH1 + i]); 432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 433 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 434 435 object_property_set_link(OBJECT(&s->mii[i]), "nic", 436 OBJECT(&s->ftgmac100[i]), &error_abort); 437 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err)) { 438 error_propagate(errp, err); 439 return; 440 } 441 442 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 443 sc->memmap[ASPEED_MII1 + i]); 444 } 445 446 /* XDMA */ 447 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err)) { 448 error_propagate(errp, err); 449 return; 450 } 451 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 452 sc->memmap[ASPEED_XDMA]); 453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 454 aspeed_soc_get_irq(s, ASPEED_XDMA)); 455 456 /* GPIO */ 457 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err)) { 458 error_propagate(errp, err); 459 return; 460 } 461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 462 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 463 aspeed_soc_get_irq(s, ASPEED_GPIO)); 464 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err)) { 466 error_propagate(errp, err); 467 return; 468 } 469 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 470 sc->memmap[ASPEED_GPIO_1_8V]); 471 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 472 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 473 474 /* SDHCI */ 475 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err)) { 476 error_propagate(errp, err); 477 return; 478 } 479 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 480 sc->memmap[ASPEED_SDHCI]); 481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 482 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 483 484 /* eMMC */ 485 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err)) { 486 error_propagate(errp, err); 487 return; 488 } 489 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 490 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 491 aspeed_soc_get_irq(s, ASPEED_EMMC)); 492 } 493 494 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 495 { 496 DeviceClass *dc = DEVICE_CLASS(oc); 497 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 498 499 dc->realize = aspeed_soc_ast2600_realize; 500 501 sc->name = "ast2600-a1"; 502 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 503 sc->silicon_rev = AST2600_A1_SILICON_REV; 504 sc->sram_size = 0x10000; 505 sc->spis_num = 2; 506 sc->ehcis_num = 2; 507 sc->wdts_num = 4; 508 sc->macs_num = 4; 509 sc->irqmap = aspeed_soc_ast2600_irqmap; 510 sc->memmap = aspeed_soc_ast2600_memmap; 511 sc->num_cpus = 2; 512 } 513 514 static const TypeInfo aspeed_soc_ast2600_type_info = { 515 .name = "ast2600-a1", 516 .parent = TYPE_ASPEED_SOC, 517 .instance_size = sizeof(AspeedSoCState), 518 .instance_init = aspeed_soc_ast2600_init, 519 .class_init = aspeed_soc_ast2600_class_init, 520 .class_size = sizeof(AspeedSoCClass), 521 }; 522 523 static void aspeed_soc_register_types(void) 524 { 525 type_register_static(&aspeed_soc_ast2600_type_info); 526 }; 527 528 type_init(aspeed_soc_register_types) 529