xref: /openbmc/qemu/hw/arm/aspeed_ast2600.c (revision 6fdc5bc1)
1 /*
2  * ASPEED SoC 2600 family
3  *
4  * Copyright (c) 2016-2019, IBM Corporation.
5  *
6  * This code is licensed under the GPL version 2 or later.  See
7  * the COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/misc/unimp.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "qemu/module.h"
15 #include "qemu/error-report.h"
16 #include "hw/i2c/aspeed_i2c.h"
17 #include "net/net.h"
18 #include "sysemu/sysemu.h"
19 #include "target/arm/cpu-qom.h"
20 
21 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
22 #define ASPEED_SOC_DPMCU_SIZE       0x00040000
23 
24 static const hwaddr aspeed_soc_ast2600_memmap[] = {
25     [ASPEED_DEV_SPI_BOOT]  = 0x00000000,
26     [ASPEED_DEV_SRAM]      = 0x10000000,
27     [ASPEED_DEV_DPMCU]     = 0x18000000,
28     /* 0x16000000     0x17FFFFFF : AHB BUS do LPC Bus bridge */
29     [ASPEED_DEV_IOMEM]     = 0x1E600000,
30     [ASPEED_DEV_PWM]       = 0x1E610000,
31     [ASPEED_DEV_FMC]       = 0x1E620000,
32     [ASPEED_DEV_SPI1]      = 0x1E630000,
33     [ASPEED_DEV_SPI2]      = 0x1E631000,
34     [ASPEED_DEV_EHCI1]     = 0x1E6A1000,
35     [ASPEED_DEV_EHCI2]     = 0x1E6A3000,
36     [ASPEED_DEV_MII1]      = 0x1E650000,
37     [ASPEED_DEV_MII2]      = 0x1E650008,
38     [ASPEED_DEV_MII3]      = 0x1E650010,
39     [ASPEED_DEV_MII4]      = 0x1E650018,
40     [ASPEED_DEV_ETH1]      = 0x1E660000,
41     [ASPEED_DEV_ETH3]      = 0x1E670000,
42     [ASPEED_DEV_ETH2]      = 0x1E680000,
43     [ASPEED_DEV_ETH4]      = 0x1E690000,
44     [ASPEED_DEV_VIC]       = 0x1E6C0000,
45     [ASPEED_DEV_HACE]      = 0x1E6D0000,
46     [ASPEED_DEV_SDMC]      = 0x1E6E0000,
47     [ASPEED_DEV_SCU]       = 0x1E6E2000,
48     [ASPEED_DEV_XDMA]      = 0x1E6E7000,
49     [ASPEED_DEV_ADC]       = 0x1E6E9000,
50     [ASPEED_DEV_DP]        = 0x1E6EB000,
51     [ASPEED_DEV_SBC]       = 0x1E6F2000,
52     [ASPEED_DEV_EMMC_BC]   = 0x1E6f5000,
53     [ASPEED_DEV_VIDEO]     = 0x1E700000,
54     [ASPEED_DEV_SDHCI]     = 0x1E740000,
55     [ASPEED_DEV_EMMC]      = 0x1E750000,
56     [ASPEED_DEV_GPIO]      = 0x1E780000,
57     [ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
58     [ASPEED_DEV_RTC]       = 0x1E781000,
59     [ASPEED_DEV_TIMER1]    = 0x1E782000,
60     [ASPEED_DEV_WDT]       = 0x1E785000,
61     [ASPEED_DEV_LPC]       = 0x1E789000,
62     [ASPEED_DEV_IBT]       = 0x1E789140,
63     [ASPEED_DEV_I2C]       = 0x1E78A000,
64     [ASPEED_DEV_PECI]      = 0x1E78B000,
65     [ASPEED_DEV_UART1]     = 0x1E783000,
66     [ASPEED_DEV_UART2]     = 0x1E78D000,
67     [ASPEED_DEV_UART3]     = 0x1E78E000,
68     [ASPEED_DEV_UART4]     = 0x1E78F000,
69     [ASPEED_DEV_UART5]     = 0x1E784000,
70     [ASPEED_DEV_UART6]     = 0x1E790000,
71     [ASPEED_DEV_UART7]     = 0x1E790100,
72     [ASPEED_DEV_UART8]     = 0x1E790200,
73     [ASPEED_DEV_UART9]     = 0x1E790300,
74     [ASPEED_DEV_UART10]    = 0x1E790400,
75     [ASPEED_DEV_UART11]    = 0x1E790500,
76     [ASPEED_DEV_UART12]    = 0x1E790600,
77     [ASPEED_DEV_UART13]    = 0x1E790700,
78     [ASPEED_DEV_VUART]     = 0x1E787000,
79     [ASPEED_DEV_FSI1]      = 0x1E79B000,
80     [ASPEED_DEV_FSI2]      = 0x1E79B100,
81     [ASPEED_DEV_I3C]       = 0x1E7A0000,
82     [ASPEED_DEV_SDRAM]     = 0x80000000,
83 };
84 
85 #define ASPEED_A7MPCORE_ADDR 0x40460000
86 
87 #define AST2600_MAX_IRQ 197
88 
89 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
90 static const int aspeed_soc_ast2600_irqmap[] = {
91     [ASPEED_DEV_UART1]     = 47,
92     [ASPEED_DEV_UART2]     = 48,
93     [ASPEED_DEV_UART3]     = 49,
94     [ASPEED_DEV_UART4]     = 50,
95     [ASPEED_DEV_UART5]     = 8,
96     [ASPEED_DEV_UART6]     = 57,
97     [ASPEED_DEV_UART7]     = 58,
98     [ASPEED_DEV_UART8]     = 59,
99     [ASPEED_DEV_UART9]     = 60,
100     [ASPEED_DEV_UART10]    = 61,
101     [ASPEED_DEV_UART11]    = 62,
102     [ASPEED_DEV_UART12]    = 63,
103     [ASPEED_DEV_UART13]    = 64,
104     [ASPEED_DEV_VUART]     = 8,
105     [ASPEED_DEV_FMC]       = 39,
106     [ASPEED_DEV_SDMC]      = 0,
107     [ASPEED_DEV_SCU]       = 12,
108     [ASPEED_DEV_ADC]       = 78,
109     [ASPEED_DEV_XDMA]      = 6,
110     [ASPEED_DEV_SDHCI]     = 43,
111     [ASPEED_DEV_EHCI1]     = 5,
112     [ASPEED_DEV_EHCI2]     = 9,
113     [ASPEED_DEV_EMMC]      = 15,
114     [ASPEED_DEV_GPIO]      = 40,
115     [ASPEED_DEV_GPIO_1_8V] = 11,
116     [ASPEED_DEV_RTC]       = 13,
117     [ASPEED_DEV_TIMER1]    = 16,
118     [ASPEED_DEV_TIMER2]    = 17,
119     [ASPEED_DEV_TIMER3]    = 18,
120     [ASPEED_DEV_TIMER4]    = 19,
121     [ASPEED_DEV_TIMER5]    = 20,
122     [ASPEED_DEV_TIMER6]    = 21,
123     [ASPEED_DEV_TIMER7]    = 22,
124     [ASPEED_DEV_TIMER8]    = 23,
125     [ASPEED_DEV_WDT]       = 24,
126     [ASPEED_DEV_PWM]       = 44,
127     [ASPEED_DEV_LPC]       = 35,
128     [ASPEED_DEV_IBT]       = 143,
129     [ASPEED_DEV_I2C]       = 110,   /* 110 -> 125 */
130     [ASPEED_DEV_PECI]      = 38,
131     [ASPEED_DEV_ETH1]      = 2,
132     [ASPEED_DEV_ETH2]      = 3,
133     [ASPEED_DEV_HACE]      = 4,
134     [ASPEED_DEV_ETH3]      = 32,
135     [ASPEED_DEV_ETH4]      = 33,
136     [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
137     [ASPEED_DEV_DP]        = 62,
138     [ASPEED_DEV_FSI1]      = 100,
139     [ASPEED_DEV_FSI2]      = 101,
140     [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
141 };
142 
143 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
144 {
145     Aspeed2600SoCState *a = ASPEED2600_SOC(s);
146     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
147 
148     return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
149 }
150 
151 static void aspeed_soc_ast2600_init(Object *obj)
152 {
153     Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
154     AspeedSoCState *s = ASPEED_SOC(obj);
155     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
156     int i;
157     char socname[8];
158     char typename[64];
159 
160     if (sscanf(sc->name, "%7s", socname) != 1) {
161         g_assert_not_reached();
162     }
163 
164     for (i = 0; i < sc->num_cpus; i++) {
165         object_initialize_child(obj, "cpu[*]", &a->cpu[i],
166                                 aspeed_soc_cpu_type(sc));
167     }
168 
169     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
170     object_initialize_child(obj, "scu", &s->scu, typename);
171     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
172                          sc->silicon_rev);
173     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
174                               "hw-strap1");
175     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
176                               "hw-strap2");
177     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
178                               "hw-prot-key");
179 
180     object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
181                             TYPE_A15MPCORE_PRIV);
182 
183     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
184 
185     snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
186     object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
187 
188     snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
189     object_initialize_child(obj, "adc", &s->adc, typename);
190 
191     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
192     object_initialize_child(obj, "i2c", &s->i2c, typename);
193 
194     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
195 
196     snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
197     object_initialize_child(obj, "fmc", &s->fmc, typename);
198 
199     for (i = 0; i < sc->spis_num; i++) {
200         snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
201         object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
202     }
203 
204     for (i = 0; i < sc->ehcis_num; i++) {
205         object_initialize_child(obj, "ehci[*]", &s->ehci[i],
206                                 TYPE_PLATFORM_EHCI);
207     }
208 
209     snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
210     object_initialize_child(obj, "sdmc", &s->sdmc, typename);
211     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
212                               "ram-size");
213 
214     for (i = 0; i < sc->wdts_num; i++) {
215         snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
216         object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
217     }
218 
219     for (i = 0; i < sc->macs_num; i++) {
220         object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
221                                 TYPE_FTGMAC100);
222 
223         object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
224     }
225 
226     for (i = 0; i < sc->uarts_num; i++) {
227         object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
228     }
229 
230     snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
231     object_initialize_child(obj, "xdma", &s->xdma, typename);
232 
233     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
234     object_initialize_child(obj, "gpio", &s->gpio, typename);
235 
236     snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
237     object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
238 
239     object_initialize_child(obj, "sd-controller", &s->sdhci,
240                             TYPE_ASPEED_SDHCI);
241 
242     object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
243 
244     /* Init sd card slot class here so that they're under the correct parent */
245     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
246         object_initialize_child(obj, "sd-controller.sdhci[*]",
247                                 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
248     }
249 
250     object_initialize_child(obj, "emmc-controller", &s->emmc,
251                             TYPE_ASPEED_SDHCI);
252 
253     object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
254 
255     object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
256                             TYPE_SYSBUS_SDHCI);
257 
258     object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
259 
260     snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
261     object_initialize_child(obj, "hace", &s->hace, typename);
262 
263     object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
264 
265     object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
266 
267     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
268     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
269     object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
270     object_initialize_child(obj, "emmc-boot-controller",
271                             &s->emmc_boot_controller,
272                             TYPE_UNIMPLEMENTED_DEVICE);
273 
274     for (i = 0; i < ASPEED_FSI_NUM; i++) {
275         object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB);
276     }
277 }
278 
279 /*
280  * ASPEED ast2600 has 0xf as cluster ID
281  *
282  * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
283  */
284 static uint64_t aspeed_calc_affinity(int cpu)
285 {
286     return (0xf << ARM_AFF1_SHIFT) | cpu;
287 }
288 
289 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
290 {
291     int i;
292     Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
293     AspeedSoCState *s = ASPEED_SOC(dev);
294     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
295     qemu_irq irq;
296     g_autofree char *sram_name = NULL;
297 
298     /* Default boot region (SPI memory or ROMs) */
299     memory_region_init(&s->spi_boot_container, OBJECT(s),
300                        "aspeed.spi_boot_container", 0x10000000);
301     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
302                                 &s->spi_boot_container);
303 
304     /* IO space */
305     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
306                                   sc->memmap[ASPEED_DEV_IOMEM],
307                                   ASPEED_SOC_IOMEM_SIZE);
308 
309     /* Video engine stub */
310     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
311                                   sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
312 
313     /* eMMC Boot Controller stub */
314     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
315                                   "aspeed.emmc-boot-controller",
316                                   sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
317 
318     /* CPU */
319     for (i = 0; i < sc->num_cpus; i++) {
320         if (sc->num_cpus > 1) {
321             object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
322                                     ASPEED_A7MPCORE_ADDR, &error_abort);
323         }
324         object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
325                                 aspeed_calc_affinity(i), &error_abort);
326 
327         object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
328                                 &error_abort);
329         object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
330                                 &error_abort);
331         object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
332                                 &error_abort);
333         object_property_set_link(OBJECT(&a->cpu[i]), "memory",
334                                  OBJECT(s->memory), &error_abort);
335 
336         if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
337             return;
338         }
339     }
340 
341     /* A7MPCORE */
342     object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
343                             &error_abort);
344     object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
345                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
346                             &error_abort);
347 
348     sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
349     aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
350 
351     for (i = 0; i < sc->num_cpus; i++) {
352         SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
353         DeviceState  *d   = DEVICE(&a->cpu[i]);
354 
355         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
356         sysbus_connect_irq(sbd, i, irq);
357         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
358         sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
359         irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
360         sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
361         irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
362         sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
363     }
364 
365     /* SRAM */
366     sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
367     if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
368                                 errp)) {
369         return;
370     }
371     memory_region_add_subregion(s->memory,
372                                 sc->memmap[ASPEED_DEV_SRAM], &s->sram);
373 
374     /* DPMCU */
375     aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
376                                   sc->memmap[ASPEED_DEV_DPMCU],
377                                   ASPEED_SOC_DPMCU_SIZE);
378 
379     /* SCU */
380     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
381         return;
382     }
383     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
384 
385     /* RTC */
386     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
387         return;
388     }
389     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
390     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
391                        aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
392 
393     /* Timer */
394     object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
395                              &error_abort);
396     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
397         return;
398     }
399     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
400                     sc->memmap[ASPEED_DEV_TIMER1]);
401     for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
402         irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
403         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
404     }
405 
406     /* ADC */
407     if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
408         return;
409     }
410     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
411     sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
412                        aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
413 
414     /* UART */
415     if (!aspeed_soc_uart_realize(s, errp)) {
416         return;
417     }
418 
419     /* I2C */
420     object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
421                              &error_abort);
422     if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
423         return;
424     }
425     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
426     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
427         irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
428                                sc->irqmap[ASPEED_DEV_I2C] + i);
429         /* The AST2600 I2C controller has one IRQ per bus. */
430         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
431     }
432 
433     /* PECI */
434     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
435         return;
436     }
437     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
438                     sc->memmap[ASPEED_DEV_PECI]);
439     sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
440                        aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
441 
442     /* FMC, The number of CS is set at the board level */
443     object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
444                              &error_abort);
445     if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
446         return;
447     }
448     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
449     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
450                     ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
451     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
452                        aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
453 
454     /* Set up an alias on the FMC CE0 region (boot default) */
455     MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
456     memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
457                              fmc0_mmio, 0, memory_region_size(fmc0_mmio));
458     memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
459 
460     /* SPI */
461     for (i = 0; i < sc->spis_num; i++) {
462         object_property_set_link(OBJECT(&s->spi[i]), "dram",
463                                  OBJECT(s->dram_mr), &error_abort);
464         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
465             return;
466         }
467         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
468                         sc->memmap[ASPEED_DEV_SPI1 + i]);
469         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
470                         ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
471     }
472 
473     /* EHCI */
474     for (i = 0; i < sc->ehcis_num; i++) {
475         if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
476             return;
477         }
478         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
479                         sc->memmap[ASPEED_DEV_EHCI1 + i]);
480         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
481                            aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
482     }
483 
484     /* SDMC - SDRAM Memory Controller */
485     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
486         return;
487     }
488     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
489                     sc->memmap[ASPEED_DEV_SDMC]);
490 
491     /* Watch dog */
492     for (i = 0; i < sc->wdts_num; i++) {
493         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
494         hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
495 
496         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
497                                  &error_abort);
498         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
499             return;
500         }
501         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
502     }
503 
504     /* RAM */
505     if (!aspeed_soc_dram_init(s, errp)) {
506         return;
507     }
508 
509     /* Net */
510     for (i = 0; i < sc->macs_num; i++) {
511         object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
512                                  &error_abort);
513         if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
514             return;
515         }
516         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
517                         sc->memmap[ASPEED_DEV_ETH1 + i]);
518         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
519                            aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
520 
521         object_property_set_link(OBJECT(&s->mii[i]), "nic",
522                                  OBJECT(&s->ftgmac100[i]), &error_abort);
523         if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
524             return;
525         }
526 
527         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
528                         sc->memmap[ASPEED_DEV_MII1 + i]);
529     }
530 
531     /* XDMA */
532     if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
533         return;
534     }
535     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
536                     sc->memmap[ASPEED_DEV_XDMA]);
537     sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
538                        aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
539 
540     /* GPIO */
541     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
542         return;
543     }
544     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
545     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
546                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
547 
548     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
549         return;
550     }
551     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
552                     sc->memmap[ASPEED_DEV_GPIO_1_8V]);
553     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
554                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
555 
556     /* SDHCI */
557     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
558         return;
559     }
560     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
561                     sc->memmap[ASPEED_DEV_SDHCI]);
562     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
563                        aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
564 
565     /* eMMC */
566     if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
567         return;
568     }
569     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
570                     sc->memmap[ASPEED_DEV_EMMC]);
571     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
572                        aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
573 
574     /* LPC */
575     if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
576         return;
577     }
578     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
579 
580     /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
581     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
582                        aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
583 
584     /*
585      * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
586      *
587      * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
588      * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
589      * shared across the subdevices, and the shared IRQ output to the VIC is at
590      * offset 0.
591      */
592     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
593                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
594                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
595 
596     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
597                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
598                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
599 
600     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
601                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
602                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
603 
604     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
605                        qdev_get_gpio_in(DEVICE(&a->a7mpcore),
606                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
607 
608     /* HACE */
609     object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
610                              &error_abort);
611     if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
612         return;
613     }
614     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
615                     sc->memmap[ASPEED_DEV_HACE]);
616     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
617                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
618 
619     /* I3C */
620     if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
621         return;
622     }
623     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
624     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
625         irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
626                                sc->irqmap[ASPEED_DEV_I3C] + i);
627         /* The AST2600 I3C controller has one IRQ per bus. */
628         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
629     }
630 
631     /* Secure Boot Controller */
632     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
633         return;
634     }
635     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
636 
637     /* FSI */
638     for (i = 0; i < ASPEED_FSI_NUM; i++) {
639         if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) {
640             return;
641         }
642         aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0,
643                         sc->memmap[ASPEED_DEV_FSI1 + i]);
644         sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0,
645                            aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i));
646     }
647 }
648 
649 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s)
650 {
651     uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu),
652                                                   "hw-strap1", &error_abort);
653     return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
654 }
655 
656 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
657 {
658     static const char * const valid_cpu_types[] = {
659         ARM_CPU_TYPE_NAME("cortex-a7"),
660         NULL
661     };
662     DeviceClass *dc = DEVICE_CLASS(oc);
663     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
664 
665     dc->realize      = aspeed_soc_ast2600_realize;
666     /* Reason: The Aspeed SoC can only be instantiated from a board */
667     dc->user_creatable = false;
668 
669     sc->name         = "ast2600-a3";
670     sc->valid_cpu_types = valid_cpu_types;
671     sc->silicon_rev  = AST2600_A3_SILICON_REV;
672     sc->sram_size    = 0x16400;
673     sc->spis_num     = 2;
674     sc->ehcis_num    = 2;
675     sc->wdts_num     = 4;
676     sc->macs_num     = 4;
677     sc->uarts_num    = 13;
678     sc->uarts_base   = ASPEED_DEV_UART1;
679     sc->irqmap       = aspeed_soc_ast2600_irqmap;
680     sc->memmap       = aspeed_soc_ast2600_memmap;
681     sc->num_cpus     = 2;
682     sc->get_irq      = aspeed_soc_ast2600_get_irq;
683     sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc;
684 }
685 
686 static const TypeInfo aspeed_soc_ast2600_types[] = {
687     {
688         .name           = TYPE_ASPEED2600_SOC,
689         .parent         = TYPE_ASPEED_SOC,
690         .instance_size  = sizeof(Aspeed2600SoCState),
691         .abstract       = true,
692     }, {
693         .name           = "ast2600-a3",
694         .parent         = TYPE_ASPEED2600_SOC,
695         .instance_init  = aspeed_soc_ast2600_init,
696         .class_init     = aspeed_soc_ast2600_class_init,
697     },
698 };
699 
700 DEFINE_TYPES(aspeed_soc_ast2600_types)
701