1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_DEV_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E641000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_MII1] = 0x1E650000, 37 [ASPEED_DEV_MII2] = 0x1E650008, 38 [ASPEED_DEV_MII3] = 0x1E650010, 39 [ASPEED_DEV_MII4] = 0x1E650018, 40 [ASPEED_DEV_ETH1] = 0x1E660000, 41 [ASPEED_DEV_ETH3] = 0x1E670000, 42 [ASPEED_DEV_ETH2] = 0x1E680000, 43 [ASPEED_DEV_ETH4] = 0x1E690000, 44 [ASPEED_DEV_VIC] = 0x1E6C0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_VIDEO] = 0x1E700000, 50 [ASPEED_DEV_SDHCI] = 0x1E740000, 51 [ASPEED_DEV_EMMC] = 0x1E750000, 52 [ASPEED_DEV_GPIO] = 0x1E780000, 53 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_DEV_RTC] = 0x1E781000, 55 [ASPEED_DEV_TIMER1] = 0x1E782000, 56 [ASPEED_DEV_WDT] = 0x1E785000, 57 [ASPEED_DEV_LPC] = 0x1E789000, 58 [ASPEED_DEV_IBT] = 0x1E789140, 59 [ASPEED_DEV_I2C] = 0x1E78A000, 60 [ASPEED_DEV_UART1] = 0x1E783000, 61 [ASPEED_DEV_UART5] = 0x1E784000, 62 [ASPEED_DEV_VUART] = 0x1E787000, 63 [ASPEED_DEV_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_DEV_UART1] = 47, 73 [ASPEED_DEV_UART2] = 48, 74 [ASPEED_DEV_UART3] = 49, 75 [ASPEED_DEV_UART4] = 50, 76 [ASPEED_DEV_UART5] = 8, 77 [ASPEED_DEV_VUART] = 8, 78 [ASPEED_DEV_FMC] = 39, 79 [ASPEED_DEV_SDMC] = 0, 80 [ASPEED_DEV_SCU] = 12, 81 [ASPEED_DEV_ADC] = 78, 82 [ASPEED_DEV_XDMA] = 6, 83 [ASPEED_DEV_SDHCI] = 43, 84 [ASPEED_DEV_EHCI1] = 5, 85 [ASPEED_DEV_EHCI2] = 9, 86 [ASPEED_DEV_EMMC] = 15, 87 [ASPEED_DEV_GPIO] = 40, 88 [ASPEED_DEV_GPIO_1_8V] = 11, 89 [ASPEED_DEV_RTC] = 13, 90 [ASPEED_DEV_TIMER1] = 16, 91 [ASPEED_DEV_TIMER2] = 17, 92 [ASPEED_DEV_TIMER3] = 18, 93 [ASPEED_DEV_TIMER4] = 19, 94 [ASPEED_DEV_TIMER5] = 20, 95 [ASPEED_DEV_TIMER6] = 21, 96 [ASPEED_DEV_TIMER7] = 22, 97 [ASPEED_DEV_TIMER8] = 23, 98 [ASPEED_DEV_WDT] = 24, 99 [ASPEED_DEV_PWM] = 44, 100 [ASPEED_DEV_LPC] = 35, 101 [ASPEED_DEV_IBT] = 35, /* LPC */ 102 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_DEV_ETH1] = 2, 104 [ASPEED_DEV_ETH2] = 3, 105 [ASPEED_DEV_ETH3] = 32, 106 [ASPEED_DEV_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 object_initialize_child(obj, "scu", &s->scu, typename); 135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 136 sc->silicon_rev); 137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 138 "hw-strap1"); 139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 140 "hw-strap2"); 141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 142 "hw-prot-key"); 143 144 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 145 TYPE_A15MPCORE_PRIV); 146 147 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 148 149 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 150 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 151 152 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 153 object_initialize_child(obj, "i2c", &s->i2c, typename); 154 155 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 156 object_initialize_child(obj, "fmc", &s->fmc, typename); 157 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 158 159 for (i = 0; i < sc->spis_num; i++) { 160 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 161 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 162 } 163 164 for (i = 0; i < sc->ehcis_num; i++) { 165 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 166 TYPE_PLATFORM_EHCI); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 170 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 171 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 172 "ram-size"); 173 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 174 "max-ram-size"); 175 176 for (i = 0; i < sc->wdts_num; i++) { 177 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 178 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 179 } 180 181 for (i = 0; i < sc->macs_num; i++) { 182 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 183 TYPE_FTGMAC100); 184 185 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 186 } 187 188 object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); 189 190 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 191 object_initialize_child(obj, "gpio", &s->gpio, typename); 192 193 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 194 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 195 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 TYPE_ASPEED_SDHCI); 198 199 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 200 201 /* Init sd card slot class here so that they're under the correct parent */ 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 203 object_initialize_child(obj, "sd-controller.sdhci[*]", 204 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 205 } 206 207 object_initialize_child(obj, "emmc-controller", &s->emmc, 208 TYPE_ASPEED_SDHCI); 209 210 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 211 212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 213 TYPE_SYSBUS_SDHCI); 214 } 215 216 /* 217 * ASPEED ast2600 has 0xf as cluster ID 218 * 219 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 220 */ 221 static uint64_t aspeed_calc_affinity(int cpu) 222 { 223 return (0xf << ARM_AFF1_SHIFT) | cpu; 224 } 225 226 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 227 { 228 int i; 229 AspeedSoCState *s = ASPEED_SOC(dev); 230 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 231 Error *err = NULL; 232 qemu_irq irq; 233 234 /* IO space */ 235 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 236 ASPEED_SOC_IOMEM_SIZE); 237 238 /* Video engine stub */ 239 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 240 0x1000); 241 242 /* CPU */ 243 for (i = 0; i < sc->num_cpus; i++) { 244 object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit", 245 QEMU_PSCI_CONDUIT_SMC, &error_abort); 246 if (sc->num_cpus > 1) { 247 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 248 ASPEED_A7MPCORE_ADDR, &error_abort); 249 } 250 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 251 aspeed_calc_affinity(i), &error_abort); 252 253 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 254 &error_abort); 255 256 /* 257 * TODO: the secondary CPUs are started and a boot helper 258 * is needed when using -kernel 259 */ 260 261 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 262 return; 263 } 264 } 265 266 /* A7MPCORE */ 267 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 268 &error_abort); 269 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 270 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 271 &error_abort); 272 273 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 274 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 275 276 for (i = 0; i < sc->num_cpus; i++) { 277 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 278 DeviceState *d = DEVICE(qemu_get_cpu(i)); 279 280 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 281 sysbus_connect_irq(sbd, i, irq); 282 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 283 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 284 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 285 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 286 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 287 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 288 } 289 290 /* SRAM */ 291 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 292 sc->sram_size, &err); 293 if (err) { 294 error_propagate(errp, err); 295 return; 296 } 297 memory_region_add_subregion(get_system_memory(), 298 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 299 300 /* SCU */ 301 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 302 return; 303 } 304 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 305 306 /* RTC */ 307 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 308 return; 309 } 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 312 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 313 314 /* Timer */ 315 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 316 &error_abort); 317 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 318 return; 319 } 320 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 321 sc->memmap[ASPEED_DEV_TIMER1]); 322 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 323 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 325 } 326 327 /* UART - attach an 8250 to the IO space as our UART5 */ 328 if (serial_hd(0)) { 329 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_DEV_UART5); 330 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, 331 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 332 } 333 334 /* I2C */ 335 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 336 &error_abort); 337 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 338 return; 339 } 340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 341 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 342 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 343 sc->irqmap[ASPEED_DEV_I2C] + i); 344 /* 345 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 346 * IRQ (AST2400 and AST2500) and connect all bussses. 347 */ 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 349 } 350 351 /* FMC, The number of CS is set at the board level */ 352 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 353 &error_abort); 354 if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", 355 sc->memmap[ASPEED_DEV_SDRAM], errp)) { 356 return; 357 } 358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 359 return; 360 } 361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 363 s->fmc.ctrl->flash_window_base); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 365 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 366 367 /* SPI */ 368 for (i = 0; i < sc->spis_num; i++) { 369 object_property_set_link(OBJECT(&s->spi[i]), "dram", 370 OBJECT(s->dram_mr), &error_abort); 371 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 373 return; 374 } 375 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 376 sc->memmap[ASPEED_DEV_SPI1 + i]); 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 378 s->spi[i].ctrl->flash_window_base); 379 } 380 381 /* EHCI */ 382 for (i = 0; i < sc->ehcis_num; i++) { 383 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 384 return; 385 } 386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 387 sc->memmap[ASPEED_DEV_EHCI1 + i]); 388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 389 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 390 } 391 392 /* SDMC - SDRAM Memory Controller */ 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 394 return; 395 } 396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 397 398 /* Watch dog */ 399 for (i = 0; i < sc->wdts_num; i++) { 400 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 401 402 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 403 &error_abort); 404 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 405 return; 406 } 407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 408 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 409 } 410 411 /* Net */ 412 for (i = 0; i < sc->macs_num; i++) { 413 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 414 &error_abort); 415 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 416 return; 417 } 418 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 419 sc->memmap[ASPEED_DEV_ETH1 + i]); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 421 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 422 423 object_property_set_link(OBJECT(&s->mii[i]), "nic", 424 OBJECT(&s->ftgmac100[i]), &error_abort); 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 426 return; 427 } 428 429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 430 sc->memmap[ASPEED_DEV_MII1 + i]); 431 } 432 433 /* XDMA */ 434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 435 return; 436 } 437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 438 sc->memmap[ASPEED_DEV_XDMA]); 439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 440 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 441 442 /* GPIO */ 443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 444 return; 445 } 446 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 448 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 449 450 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 451 return; 452 } 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 454 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 456 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 457 458 /* SDHCI */ 459 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 460 return; 461 } 462 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 463 sc->memmap[ASPEED_DEV_SDHCI]); 464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 465 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 466 467 /* eMMC */ 468 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 469 return; 470 } 471 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 473 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 474 } 475 476 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 477 { 478 DeviceClass *dc = DEVICE_CLASS(oc); 479 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 480 481 dc->realize = aspeed_soc_ast2600_realize; 482 483 sc->name = "ast2600-a1"; 484 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 485 sc->silicon_rev = AST2600_A1_SILICON_REV; 486 sc->sram_size = 0x10000; 487 sc->spis_num = 2; 488 sc->ehcis_num = 2; 489 sc->wdts_num = 4; 490 sc->macs_num = 4; 491 sc->irqmap = aspeed_soc_ast2600_irqmap; 492 sc->memmap = aspeed_soc_ast2600_memmap; 493 sc->num_cpus = 2; 494 } 495 496 static const TypeInfo aspeed_soc_ast2600_type_info = { 497 .name = "ast2600-a1", 498 .parent = TYPE_ASPEED_SOC, 499 .instance_size = sizeof(AspeedSoCState), 500 .instance_init = aspeed_soc_ast2600_init, 501 .class_init = aspeed_soc_ast2600_class_init, 502 .class_size = sizeof(AspeedSoCClass), 503 }; 504 505 static void aspeed_soc_register_types(void) 506 { 507 type_register_static(&aspeed_soc_ast2600_type_info); 508 }; 509 510 type_init(aspeed_soc_register_types) 511