1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 [ASPEED_DEV_DPMCU] = 0x18000000, 27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 28 [ASPEED_DEV_IOMEM] = 0x1E600000, 29 [ASPEED_DEV_PWM] = 0x1E610000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_SPI2] = 0x1E631000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 35 [ASPEED_DEV_MII1] = 0x1E650000, 36 [ASPEED_DEV_MII2] = 0x1E650008, 37 [ASPEED_DEV_MII3] = 0x1E650010, 38 [ASPEED_DEV_MII4] = 0x1E650018, 39 [ASPEED_DEV_ETH1] = 0x1E660000, 40 [ASPEED_DEV_ETH3] = 0x1E670000, 41 [ASPEED_DEV_ETH2] = 0x1E680000, 42 [ASPEED_DEV_ETH4] = 0x1E690000, 43 [ASPEED_DEV_VIC] = 0x1E6C0000, 44 [ASPEED_DEV_HACE] = 0x1E6D0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_DP] = 0x1E6EB000, 50 [ASPEED_DEV_VIDEO] = 0x1E700000, 51 [ASPEED_DEV_SDHCI] = 0x1E740000, 52 [ASPEED_DEV_EMMC] = 0x1E750000, 53 [ASPEED_DEV_GPIO] = 0x1E780000, 54 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 55 [ASPEED_DEV_RTC] = 0x1E781000, 56 [ASPEED_DEV_TIMER1] = 0x1E782000, 57 [ASPEED_DEV_WDT] = 0x1E785000, 58 [ASPEED_DEV_LPC] = 0x1E789000, 59 [ASPEED_DEV_IBT] = 0x1E789140, 60 [ASPEED_DEV_I2C] = 0x1E78A000, 61 [ASPEED_DEV_UART1] = 0x1E783000, 62 [ASPEED_DEV_UART5] = 0x1E784000, 63 [ASPEED_DEV_VUART] = 0x1E787000, 64 [ASPEED_DEV_I3C] = 0x1E7A0000, 65 [ASPEED_DEV_SDRAM] = 0x80000000, 66 }; 67 68 #define ASPEED_A7MPCORE_ADDR 0x40460000 69 70 #define AST2600_MAX_IRQ 197 71 72 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 73 static const int aspeed_soc_ast2600_irqmap[] = { 74 [ASPEED_DEV_UART1] = 47, 75 [ASPEED_DEV_UART2] = 48, 76 [ASPEED_DEV_UART3] = 49, 77 [ASPEED_DEV_UART4] = 50, 78 [ASPEED_DEV_UART5] = 8, 79 [ASPEED_DEV_VUART] = 8, 80 [ASPEED_DEV_FMC] = 39, 81 [ASPEED_DEV_SDMC] = 0, 82 [ASPEED_DEV_SCU] = 12, 83 [ASPEED_DEV_ADC] = 78, 84 [ASPEED_DEV_XDMA] = 6, 85 [ASPEED_DEV_SDHCI] = 43, 86 [ASPEED_DEV_EHCI1] = 5, 87 [ASPEED_DEV_EHCI2] = 9, 88 [ASPEED_DEV_EMMC] = 15, 89 [ASPEED_DEV_GPIO] = 40, 90 [ASPEED_DEV_GPIO_1_8V] = 11, 91 [ASPEED_DEV_RTC] = 13, 92 [ASPEED_DEV_TIMER1] = 16, 93 [ASPEED_DEV_TIMER2] = 17, 94 [ASPEED_DEV_TIMER3] = 18, 95 [ASPEED_DEV_TIMER4] = 19, 96 [ASPEED_DEV_TIMER5] = 20, 97 [ASPEED_DEV_TIMER6] = 21, 98 [ASPEED_DEV_TIMER7] = 22, 99 [ASPEED_DEV_TIMER8] = 23, 100 [ASPEED_DEV_WDT] = 24, 101 [ASPEED_DEV_PWM] = 44, 102 [ASPEED_DEV_LPC] = 35, 103 [ASPEED_DEV_IBT] = 143, 104 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 105 [ASPEED_DEV_ETH1] = 2, 106 [ASPEED_DEV_ETH2] = 3, 107 [ASPEED_DEV_HACE] = 4, 108 [ASPEED_DEV_ETH3] = 32, 109 [ASPEED_DEV_ETH4] = 33, 110 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 111 [ASPEED_DEV_DP] = 62, 112 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 113 }; 114 115 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 116 { 117 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 118 119 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 120 } 121 122 static void aspeed_soc_ast2600_init(Object *obj) 123 { 124 AspeedSoCState *s = ASPEED_SOC(obj); 125 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 126 int i; 127 char socname[8]; 128 char typename[64]; 129 130 if (sscanf(sc->name, "%7s", socname) != 1) { 131 g_assert_not_reached(); 132 } 133 134 for (i = 0; i < sc->num_cpus; i++) { 135 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 136 } 137 138 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 139 object_initialize_child(obj, "scu", &s->scu, typename); 140 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 141 sc->silicon_rev); 142 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 143 "hw-strap1"); 144 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 145 "hw-strap2"); 146 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 147 "hw-prot-key"); 148 149 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 150 TYPE_A15MPCORE_PRIV); 151 152 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 153 154 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 155 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 156 157 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 158 object_initialize_child(obj, "adc", &s->adc, typename); 159 160 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 161 object_initialize_child(obj, "i2c", &s->i2c, typename); 162 163 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 164 object_initialize_child(obj, "fmc", &s->fmc, typename); 165 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 166 167 for (i = 0; i < sc->spis_num; i++) { 168 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 169 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 170 } 171 172 for (i = 0; i < sc->ehcis_num; i++) { 173 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 174 TYPE_PLATFORM_EHCI); 175 } 176 177 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 178 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 179 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 180 "ram-size"); 181 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 182 "max-ram-size"); 183 184 for (i = 0; i < sc->wdts_num; i++) { 185 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 186 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 187 } 188 189 for (i = 0; i < sc->macs_num; i++) { 190 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 191 TYPE_FTGMAC100); 192 193 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 194 } 195 196 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 197 object_initialize_child(obj, "xdma", &s->xdma, typename); 198 199 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 200 object_initialize_child(obj, "gpio", &s->gpio, typename); 201 202 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 203 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 204 205 object_initialize_child(obj, "sd-controller", &s->sdhci, 206 TYPE_ASPEED_SDHCI); 207 208 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 209 210 /* Init sd card slot class here so that they're under the correct parent */ 211 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 212 object_initialize_child(obj, "sd-controller.sdhci[*]", 213 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 214 } 215 216 object_initialize_child(obj, "emmc-controller", &s->emmc, 217 TYPE_ASPEED_SDHCI); 218 219 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 220 221 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 222 TYPE_SYSBUS_SDHCI); 223 224 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 225 226 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 227 object_initialize_child(obj, "hace", &s->hace, typename); 228 229 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 230 } 231 232 /* 233 * ASPEED ast2600 has 0xf as cluster ID 234 * 235 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 236 */ 237 static uint64_t aspeed_calc_affinity(int cpu) 238 { 239 return (0xf << ARM_AFF1_SHIFT) | cpu; 240 } 241 242 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 243 { 244 int i; 245 AspeedSoCState *s = ASPEED_SOC(dev); 246 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 247 Error *err = NULL; 248 qemu_irq irq; 249 250 /* IO space */ 251 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 252 ASPEED_SOC_IOMEM_SIZE); 253 254 /* Video engine stub */ 255 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 256 0x1000); 257 258 /* CPU */ 259 for (i = 0; i < sc->num_cpus; i++) { 260 if (sc->num_cpus > 1) { 261 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 262 ASPEED_A7MPCORE_ADDR, &error_abort); 263 } 264 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 265 aspeed_calc_affinity(i), &error_abort); 266 267 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 268 &error_abort); 269 270 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 271 return; 272 } 273 } 274 275 /* A7MPCORE */ 276 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 277 &error_abort); 278 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 279 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 280 &error_abort); 281 282 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 283 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 284 285 for (i = 0; i < sc->num_cpus; i++) { 286 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 287 DeviceState *d = DEVICE(qemu_get_cpu(i)); 288 289 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 290 sysbus_connect_irq(sbd, i, irq); 291 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 292 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 293 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 294 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 295 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 296 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 297 } 298 299 /* SRAM */ 300 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 301 sc->sram_size, &err); 302 if (err) { 303 error_propagate(errp, err); 304 return; 305 } 306 memory_region_add_subregion(get_system_memory(), 307 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 308 309 /* DPMCU */ 310 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 311 ASPEED_SOC_DPMCU_SIZE); 312 313 /* SCU */ 314 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 315 return; 316 } 317 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 318 319 /* RTC */ 320 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 321 return; 322 } 323 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 325 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 326 327 /* Timer */ 328 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 329 &error_abort); 330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 331 return; 332 } 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 334 sc->memmap[ASPEED_DEV_TIMER1]); 335 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 336 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 338 } 339 340 /* ADC */ 341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 342 return; 343 } 344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 346 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 347 348 /* UART - attach an 8250 to the IO space as our UART */ 349 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 350 aspeed_soc_get_irq(s, s->uart_default), 38400, 351 serial_hd(0), DEVICE_LITTLE_ENDIAN); 352 353 /* I2C */ 354 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 355 &error_abort); 356 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 357 return; 358 } 359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 360 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 361 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 362 sc->irqmap[ASPEED_DEV_I2C] + i); 363 /* The AST2600 I2C controller has one IRQ per bus. */ 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 365 } 366 367 /* FMC, The number of CS is set at the board level */ 368 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 369 &error_abort); 370 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 371 return; 372 } 373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 374 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 375 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 376 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 377 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 378 379 /* SPI */ 380 for (i = 0; i < sc->spis_num; i++) { 381 object_property_set_link(OBJECT(&s->spi[i]), "dram", 382 OBJECT(s->dram_mr), &error_abort); 383 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 385 return; 386 } 387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 388 sc->memmap[ASPEED_DEV_SPI1 + i]); 389 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 390 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 391 } 392 393 /* EHCI */ 394 for (i = 0; i < sc->ehcis_num; i++) { 395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 396 return; 397 } 398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 399 sc->memmap[ASPEED_DEV_EHCI1 + i]); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 401 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 402 } 403 404 /* SDMC - SDRAM Memory Controller */ 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 406 return; 407 } 408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 409 410 /* Watch dog */ 411 for (i = 0; i < sc->wdts_num; i++) { 412 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 413 414 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 415 &error_abort); 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 417 return; 418 } 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 420 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 421 } 422 423 /* Net */ 424 for (i = 0; i < sc->macs_num; i++) { 425 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 426 &error_abort); 427 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 428 return; 429 } 430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 431 sc->memmap[ASPEED_DEV_ETH1 + i]); 432 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 433 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 434 435 object_property_set_link(OBJECT(&s->mii[i]), "nic", 436 OBJECT(&s->ftgmac100[i]), &error_abort); 437 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 438 return; 439 } 440 441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 442 sc->memmap[ASPEED_DEV_MII1 + i]); 443 } 444 445 /* XDMA */ 446 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 447 return; 448 } 449 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 450 sc->memmap[ASPEED_DEV_XDMA]); 451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 452 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 453 454 /* GPIO */ 455 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 456 return; 457 } 458 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 459 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 460 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 461 462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 463 return; 464 } 465 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 466 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 468 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 469 470 /* SDHCI */ 471 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 472 return; 473 } 474 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 475 sc->memmap[ASPEED_DEV_SDHCI]); 476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 477 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 478 479 /* eMMC */ 480 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 481 return; 482 } 483 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 485 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 486 487 /* LPC */ 488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 489 return; 490 } 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 492 493 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 495 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 496 497 /* 498 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 499 * 500 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 501 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 502 * shared across the subdevices, and the shared IRQ output to the VIC is at 503 * offset 0. 504 */ 505 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 506 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 507 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 508 509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 510 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 511 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 512 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 514 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 515 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 516 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 518 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 519 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 520 521 /* HACE */ 522 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 523 &error_abort); 524 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 525 return; 526 } 527 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 528 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 529 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 530 531 /* I3C */ 532 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 533 return; 534 } 535 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 536 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 537 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 538 sc->irqmap[ASPEED_DEV_I3C] + i); 539 /* The AST2600 I3C controller has one IRQ per bus. */ 540 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 541 } 542 } 543 544 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 545 { 546 DeviceClass *dc = DEVICE_CLASS(oc); 547 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 548 549 dc->realize = aspeed_soc_ast2600_realize; 550 551 sc->name = "ast2600-a3"; 552 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 553 sc->silicon_rev = AST2600_A3_SILICON_REV; 554 sc->sram_size = 0x16400; 555 sc->spis_num = 2; 556 sc->ehcis_num = 2; 557 sc->wdts_num = 4; 558 sc->macs_num = 4; 559 sc->irqmap = aspeed_soc_ast2600_irqmap; 560 sc->memmap = aspeed_soc_ast2600_memmap; 561 sc->num_cpus = 2; 562 } 563 564 static const TypeInfo aspeed_soc_ast2600_type_info = { 565 .name = "ast2600-a3", 566 .parent = TYPE_ASPEED_SOC, 567 .instance_size = sizeof(AspeedSoCState), 568 .instance_init = aspeed_soc_ast2600_init, 569 .class_init = aspeed_soc_ast2600_class_init, 570 .class_size = sizeof(AspeedSoCClass), 571 }; 572 573 static void aspeed_soc_register_types(void) 574 { 575 type_register_static(&aspeed_soc_ast2600_type_info); 576 }; 577 578 type_init(aspeed_soc_register_types) 579