1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 [ASPEED_DEV_DPMCU] = 0x18000000, 27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 28 [ASPEED_DEV_IOMEM] = 0x1E600000, 29 [ASPEED_DEV_PWM] = 0x1E610000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_SPI2] = 0x1E631000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 35 [ASPEED_DEV_MII1] = 0x1E650000, 36 [ASPEED_DEV_MII2] = 0x1E650008, 37 [ASPEED_DEV_MII3] = 0x1E650010, 38 [ASPEED_DEV_MII4] = 0x1E650018, 39 [ASPEED_DEV_ETH1] = 0x1E660000, 40 [ASPEED_DEV_ETH3] = 0x1E670000, 41 [ASPEED_DEV_ETH2] = 0x1E680000, 42 [ASPEED_DEV_ETH4] = 0x1E690000, 43 [ASPEED_DEV_VIC] = 0x1E6C0000, 44 [ASPEED_DEV_HACE] = 0x1E6D0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_DP] = 0x1E6EB000, 50 [ASPEED_DEV_SBC] = 0x1E6F2000, 51 [ASPEED_DEV_VIDEO] = 0x1E700000, 52 [ASPEED_DEV_SDHCI] = 0x1E740000, 53 [ASPEED_DEV_EMMC] = 0x1E750000, 54 [ASPEED_DEV_GPIO] = 0x1E780000, 55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 56 [ASPEED_DEV_RTC] = 0x1E781000, 57 [ASPEED_DEV_TIMER1] = 0x1E782000, 58 [ASPEED_DEV_WDT] = 0x1E785000, 59 [ASPEED_DEV_LPC] = 0x1E789000, 60 [ASPEED_DEV_IBT] = 0x1E789140, 61 [ASPEED_DEV_I2C] = 0x1E78A000, 62 [ASPEED_DEV_UART1] = 0x1E783000, 63 [ASPEED_DEV_UART5] = 0x1E784000, 64 [ASPEED_DEV_VUART] = 0x1E787000, 65 [ASPEED_DEV_I3C] = 0x1E7A0000, 66 [ASPEED_DEV_SDRAM] = 0x80000000, 67 }; 68 69 #define ASPEED_A7MPCORE_ADDR 0x40460000 70 71 #define AST2600_MAX_IRQ 197 72 73 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 74 static const int aspeed_soc_ast2600_irqmap[] = { 75 [ASPEED_DEV_UART1] = 47, 76 [ASPEED_DEV_UART2] = 48, 77 [ASPEED_DEV_UART3] = 49, 78 [ASPEED_DEV_UART4] = 50, 79 [ASPEED_DEV_UART5] = 8, 80 [ASPEED_DEV_VUART] = 8, 81 [ASPEED_DEV_FMC] = 39, 82 [ASPEED_DEV_SDMC] = 0, 83 [ASPEED_DEV_SCU] = 12, 84 [ASPEED_DEV_ADC] = 78, 85 [ASPEED_DEV_XDMA] = 6, 86 [ASPEED_DEV_SDHCI] = 43, 87 [ASPEED_DEV_EHCI1] = 5, 88 [ASPEED_DEV_EHCI2] = 9, 89 [ASPEED_DEV_EMMC] = 15, 90 [ASPEED_DEV_GPIO] = 40, 91 [ASPEED_DEV_GPIO_1_8V] = 11, 92 [ASPEED_DEV_RTC] = 13, 93 [ASPEED_DEV_TIMER1] = 16, 94 [ASPEED_DEV_TIMER2] = 17, 95 [ASPEED_DEV_TIMER3] = 18, 96 [ASPEED_DEV_TIMER4] = 19, 97 [ASPEED_DEV_TIMER5] = 20, 98 [ASPEED_DEV_TIMER6] = 21, 99 [ASPEED_DEV_TIMER7] = 22, 100 [ASPEED_DEV_TIMER8] = 23, 101 [ASPEED_DEV_WDT] = 24, 102 [ASPEED_DEV_PWM] = 44, 103 [ASPEED_DEV_LPC] = 35, 104 [ASPEED_DEV_IBT] = 143, 105 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 106 [ASPEED_DEV_ETH1] = 2, 107 [ASPEED_DEV_ETH2] = 3, 108 [ASPEED_DEV_HACE] = 4, 109 [ASPEED_DEV_ETH3] = 32, 110 [ASPEED_DEV_ETH4] = 33, 111 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 112 [ASPEED_DEV_DP] = 62, 113 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 114 }; 115 116 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 117 { 118 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 119 120 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 121 } 122 123 static void aspeed_soc_ast2600_init(Object *obj) 124 { 125 AspeedSoCState *s = ASPEED_SOC(obj); 126 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 127 int i; 128 char socname[8]; 129 char typename[64]; 130 131 if (sscanf(sc->name, "%7s", socname) != 1) { 132 g_assert_not_reached(); 133 } 134 135 for (i = 0; i < sc->num_cpus; i++) { 136 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 137 } 138 139 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 140 object_initialize_child(obj, "scu", &s->scu, typename); 141 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 142 sc->silicon_rev); 143 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 144 "hw-strap1"); 145 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 146 "hw-strap2"); 147 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 148 "hw-prot-key"); 149 150 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 151 TYPE_A15MPCORE_PRIV); 152 153 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 154 155 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 156 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 157 158 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 159 object_initialize_child(obj, "adc", &s->adc, typename); 160 161 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 162 object_initialize_child(obj, "i2c", &s->i2c, typename); 163 164 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 165 object_initialize_child(obj, "fmc", &s->fmc, typename); 166 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 167 168 for (i = 0; i < sc->spis_num; i++) { 169 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 170 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 171 } 172 173 for (i = 0; i < sc->ehcis_num; i++) { 174 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 175 TYPE_PLATFORM_EHCI); 176 } 177 178 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 179 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 180 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 181 "ram-size"); 182 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 183 "max-ram-size"); 184 185 for (i = 0; i < sc->wdts_num; i++) { 186 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 187 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 188 } 189 190 for (i = 0; i < sc->macs_num; i++) { 191 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 192 TYPE_FTGMAC100); 193 194 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 195 } 196 197 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 198 object_initialize_child(obj, "xdma", &s->xdma, typename); 199 200 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 201 object_initialize_child(obj, "gpio", &s->gpio, typename); 202 203 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 204 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 205 206 object_initialize_child(obj, "sd-controller", &s->sdhci, 207 TYPE_ASPEED_SDHCI); 208 209 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 210 211 /* Init sd card slot class here so that they're under the correct parent */ 212 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 213 object_initialize_child(obj, "sd-controller.sdhci[*]", 214 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 215 } 216 217 object_initialize_child(obj, "emmc-controller", &s->emmc, 218 TYPE_ASPEED_SDHCI); 219 220 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 221 222 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 223 TYPE_SYSBUS_SDHCI); 224 225 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 226 227 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 228 object_initialize_child(obj, "hace", &s->hace, typename); 229 230 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 231 232 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 233 } 234 235 /* 236 * ASPEED ast2600 has 0xf as cluster ID 237 * 238 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 239 */ 240 static uint64_t aspeed_calc_affinity(int cpu) 241 { 242 return (0xf << ARM_AFF1_SHIFT) | cpu; 243 } 244 245 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 246 { 247 int i; 248 AspeedSoCState *s = ASPEED_SOC(dev); 249 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 250 Error *err = NULL; 251 qemu_irq irq; 252 253 /* IO space */ 254 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 255 ASPEED_SOC_IOMEM_SIZE); 256 257 /* Video engine stub */ 258 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 259 0x1000); 260 261 /* CPU */ 262 for (i = 0; i < sc->num_cpus; i++) { 263 if (sc->num_cpus > 1) { 264 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 265 ASPEED_A7MPCORE_ADDR, &error_abort); 266 } 267 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 268 aspeed_calc_affinity(i), &error_abort); 269 270 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 271 &error_abort); 272 273 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 274 return; 275 } 276 } 277 278 /* A7MPCORE */ 279 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 280 &error_abort); 281 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 282 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 283 &error_abort); 284 285 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 286 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 287 288 for (i = 0; i < sc->num_cpus; i++) { 289 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 290 DeviceState *d = DEVICE(qemu_get_cpu(i)); 291 292 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 293 sysbus_connect_irq(sbd, i, irq); 294 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 295 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 296 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 297 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 298 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 299 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 300 } 301 302 /* SRAM */ 303 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 304 sc->sram_size, &err); 305 if (err) { 306 error_propagate(errp, err); 307 return; 308 } 309 memory_region_add_subregion(get_system_memory(), 310 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 311 312 /* DPMCU */ 313 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 314 ASPEED_SOC_DPMCU_SIZE); 315 316 /* SCU */ 317 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 318 return; 319 } 320 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 321 322 /* RTC */ 323 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 324 return; 325 } 326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 328 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 329 330 /* Timer */ 331 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 332 &error_abort); 333 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 334 return; 335 } 336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 337 sc->memmap[ASPEED_DEV_TIMER1]); 338 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 339 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 340 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 341 } 342 343 /* ADC */ 344 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 345 return; 346 } 347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 348 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 349 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 350 351 /* UART - attach an 8250 to the IO space as our UART */ 352 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 353 aspeed_soc_get_irq(s, s->uart_default), 38400, 354 serial_hd(0), DEVICE_LITTLE_ENDIAN); 355 356 /* I2C */ 357 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 358 &error_abort); 359 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 360 return; 361 } 362 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 363 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 364 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 365 sc->irqmap[ASPEED_DEV_I2C] + i); 366 /* The AST2600 I2C controller has one IRQ per bus. */ 367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 368 } 369 370 /* FMC, The number of CS is set at the board level */ 371 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 372 &error_abort); 373 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 374 return; 375 } 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 378 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 380 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 381 382 /* SPI */ 383 for (i = 0; i < sc->spis_num; i++) { 384 object_property_set_link(OBJECT(&s->spi[i]), "dram", 385 OBJECT(s->dram_mr), &error_abort); 386 object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 388 return; 389 } 390 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 391 sc->memmap[ASPEED_DEV_SPI1 + i]); 392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 393 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 394 } 395 396 /* EHCI */ 397 for (i = 0; i < sc->ehcis_num; i++) { 398 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 399 return; 400 } 401 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 402 sc->memmap[ASPEED_DEV_EHCI1 + i]); 403 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 404 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 405 } 406 407 /* SDMC - SDRAM Memory Controller */ 408 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 409 return; 410 } 411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 412 413 /* Watch dog */ 414 for (i = 0; i < sc->wdts_num; i++) { 415 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 416 417 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 418 &error_abort); 419 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 420 return; 421 } 422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 423 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 424 } 425 426 /* Net */ 427 for (i = 0; i < sc->macs_num; i++) { 428 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 429 &error_abort); 430 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 431 return; 432 } 433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 434 sc->memmap[ASPEED_DEV_ETH1 + i]); 435 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 436 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 437 438 object_property_set_link(OBJECT(&s->mii[i]), "nic", 439 OBJECT(&s->ftgmac100[i]), &error_abort); 440 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 441 return; 442 } 443 444 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 445 sc->memmap[ASPEED_DEV_MII1 + i]); 446 } 447 448 /* XDMA */ 449 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 450 return; 451 } 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 453 sc->memmap[ASPEED_DEV_XDMA]); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 455 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 456 457 /* GPIO */ 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 459 return; 460 } 461 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 462 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 463 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 464 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 466 return; 467 } 468 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 469 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 470 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 471 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 472 473 /* SDHCI */ 474 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 475 return; 476 } 477 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 478 sc->memmap[ASPEED_DEV_SDHCI]); 479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 480 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 481 482 /* eMMC */ 483 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 484 return; 485 } 486 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 488 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 489 490 /* LPC */ 491 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 492 return; 493 } 494 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 495 496 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 498 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 499 500 /* 501 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 502 * 503 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 504 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 505 * shared across the subdevices, and the shared IRQ output to the VIC is at 506 * offset 0. 507 */ 508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 509 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 510 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 511 512 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 513 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 514 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 515 516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 517 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 518 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 519 520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 521 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 522 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 523 524 /* HACE */ 525 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 526 &error_abort); 527 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 528 return; 529 } 530 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 531 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 532 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 533 534 /* I3C */ 535 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 536 return; 537 } 538 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 539 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 540 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 541 sc->irqmap[ASPEED_DEV_I3C] + i); 542 /* The AST2600 I3C controller has one IRQ per bus. */ 543 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 544 } 545 546 /* Secure Boot Controller */ 547 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 548 return; 549 } 550 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 551 } 552 553 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 554 { 555 DeviceClass *dc = DEVICE_CLASS(oc); 556 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 557 558 dc->realize = aspeed_soc_ast2600_realize; 559 560 sc->name = "ast2600-a3"; 561 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 562 sc->silicon_rev = AST2600_A3_SILICON_REV; 563 sc->sram_size = 0x16400; 564 sc->spis_num = 2; 565 sc->ehcis_num = 2; 566 sc->wdts_num = 4; 567 sc->macs_num = 4; 568 sc->irqmap = aspeed_soc_ast2600_irqmap; 569 sc->memmap = aspeed_soc_ast2600_memmap; 570 sc->num_cpus = 2; 571 } 572 573 static const TypeInfo aspeed_soc_ast2600_type_info = { 574 .name = "ast2600-a3", 575 .parent = TYPE_ASPEED_SOC, 576 .instance_size = sizeof(AspeedSoCState), 577 .instance_init = aspeed_soc_ast2600_init, 578 .class_init = aspeed_soc_ast2600_class_init, 579 .class_size = sizeof(AspeedSoCClass), 580 }; 581 582 static void aspeed_soc_register_types(void) 583 { 584 type_register_static(&aspeed_soc_ast2600_type_info); 585 }; 586 587 type_init(aspeed_soc_register_types) 588