1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "qemu/module.h" 15 #include "qemu/error-report.h" 16 #include "hw/i2c/aspeed_i2c.h" 17 #include "net/net.h" 18 #include "sysemu/sysemu.h" 19 #include "target/arm/cpu-qom.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 26 [ASPEED_DEV_SRAM] = 0x10000000, 27 [ASPEED_DEV_DPMCU] = 0x18000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_PWM] = 0x1E610000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_SPI2] = 0x1E631000, 34 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 35 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 36 [ASPEED_DEV_UHCI] = 0x1E6B0000, 37 [ASPEED_DEV_MII1] = 0x1E650000, 38 [ASPEED_DEV_MII2] = 0x1E650008, 39 [ASPEED_DEV_MII3] = 0x1E650010, 40 [ASPEED_DEV_MII4] = 0x1E650018, 41 [ASPEED_DEV_ETH1] = 0x1E660000, 42 [ASPEED_DEV_ETH3] = 0x1E670000, 43 [ASPEED_DEV_ETH2] = 0x1E680000, 44 [ASPEED_DEV_ETH4] = 0x1E690000, 45 [ASPEED_DEV_VIC] = 0x1E6C0000, 46 [ASPEED_DEV_HACE] = 0x1E6D0000, 47 [ASPEED_DEV_SDMC] = 0x1E6E0000, 48 [ASPEED_DEV_SCU] = 0x1E6E2000, 49 [ASPEED_DEV_XDMA] = 0x1E6E7000, 50 [ASPEED_DEV_ADC] = 0x1E6E9000, 51 [ASPEED_DEV_DP] = 0x1E6EB000, 52 [ASPEED_DEV_SBC] = 0x1E6F2000, 53 [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, 54 [ASPEED_DEV_VIDEO] = 0x1E700000, 55 [ASPEED_DEV_SDHCI] = 0x1E740000, 56 [ASPEED_DEV_EMMC] = 0x1E750000, 57 [ASPEED_DEV_GPIO] = 0x1E780000, 58 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 59 [ASPEED_DEV_RTC] = 0x1E781000, 60 [ASPEED_DEV_TIMER1] = 0x1E782000, 61 [ASPEED_DEV_WDT] = 0x1E785000, 62 [ASPEED_DEV_LPC] = 0x1E789000, 63 [ASPEED_DEV_IBT] = 0x1E789140, 64 [ASPEED_DEV_I2C] = 0x1E78A000, 65 [ASPEED_DEV_PECI] = 0x1E78B000, 66 [ASPEED_DEV_UART1] = 0x1E783000, 67 [ASPEED_DEV_UART2] = 0x1E78D000, 68 [ASPEED_DEV_UART3] = 0x1E78E000, 69 [ASPEED_DEV_UART4] = 0x1E78F000, 70 [ASPEED_DEV_UART5] = 0x1E784000, 71 [ASPEED_DEV_UART6] = 0x1E790000, 72 [ASPEED_DEV_UART7] = 0x1E790100, 73 [ASPEED_DEV_UART8] = 0x1E790200, 74 [ASPEED_DEV_UART9] = 0x1E790300, 75 [ASPEED_DEV_UART10] = 0x1E790400, 76 [ASPEED_DEV_UART11] = 0x1E790500, 77 [ASPEED_DEV_UART12] = 0x1E790600, 78 [ASPEED_DEV_UART13] = 0x1E790700, 79 [ASPEED_DEV_VUART] = 0x1E787000, 80 [ASPEED_DEV_FSI1] = 0x1E79B000, 81 [ASPEED_DEV_FSI2] = 0x1E79B100, 82 [ASPEED_DEV_I3C] = 0x1E7A0000, 83 [ASPEED_DEV_SDRAM] = 0x80000000, 84 }; 85 86 #define ASPEED_A7MPCORE_ADDR 0x40460000 87 88 #define AST2600_MAX_IRQ 197 89 90 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 91 static const int aspeed_soc_ast2600_irqmap[] = { 92 [ASPEED_DEV_UART1] = 47, 93 [ASPEED_DEV_UART2] = 48, 94 [ASPEED_DEV_UART3] = 49, 95 [ASPEED_DEV_UART4] = 50, 96 [ASPEED_DEV_UART5] = 8, 97 [ASPEED_DEV_UART6] = 57, 98 [ASPEED_DEV_UART7] = 58, 99 [ASPEED_DEV_UART8] = 59, 100 [ASPEED_DEV_UART9] = 60, 101 [ASPEED_DEV_UART10] = 61, 102 [ASPEED_DEV_UART11] = 62, 103 [ASPEED_DEV_UART12] = 63, 104 [ASPEED_DEV_UART13] = 64, 105 [ASPEED_DEV_VUART] = 8, 106 [ASPEED_DEV_FMC] = 39, 107 [ASPEED_DEV_SDMC] = 0, 108 [ASPEED_DEV_SCU] = 12, 109 [ASPEED_DEV_ADC] = 78, 110 [ASPEED_DEV_XDMA] = 6, 111 [ASPEED_DEV_SDHCI] = 43, 112 [ASPEED_DEV_EHCI1] = 5, 113 [ASPEED_DEV_EHCI2] = 9, 114 [ASPEED_DEV_UHCI] = 10, 115 [ASPEED_DEV_EMMC] = 15, 116 [ASPEED_DEV_GPIO] = 40, 117 [ASPEED_DEV_GPIO_1_8V] = 11, 118 [ASPEED_DEV_RTC] = 13, 119 [ASPEED_DEV_TIMER1] = 16, 120 [ASPEED_DEV_TIMER2] = 17, 121 [ASPEED_DEV_TIMER3] = 18, 122 [ASPEED_DEV_TIMER4] = 19, 123 [ASPEED_DEV_TIMER5] = 20, 124 [ASPEED_DEV_TIMER6] = 21, 125 [ASPEED_DEV_TIMER7] = 22, 126 [ASPEED_DEV_TIMER8] = 23, 127 [ASPEED_DEV_WDT] = 24, 128 [ASPEED_DEV_PWM] = 44, 129 [ASPEED_DEV_LPC] = 35, 130 [ASPEED_DEV_IBT] = 143, 131 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 132 [ASPEED_DEV_PECI] = 38, 133 [ASPEED_DEV_ETH1] = 2, 134 [ASPEED_DEV_ETH2] = 3, 135 [ASPEED_DEV_HACE] = 4, 136 [ASPEED_DEV_ETH3] = 32, 137 [ASPEED_DEV_ETH4] = 33, 138 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 139 [ASPEED_DEV_DP] = 62, 140 [ASPEED_DEV_FSI1] = 100, 141 [ASPEED_DEV_FSI2] = 101, 142 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 143 }; 144 145 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) 146 { 147 Aspeed2600SoCState *a = ASPEED2600_SOC(s); 148 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 149 150 return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); 151 } 152 153 static void aspeed_soc_ast2600_init(Object *obj) 154 { 155 Aspeed2600SoCState *a = ASPEED2600_SOC(obj); 156 AspeedSoCState *s = ASPEED_SOC(obj); 157 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 158 int i; 159 char socname[8]; 160 char typename[64]; 161 162 if (sscanf(sc->name, "%7s", socname) != 1) { 163 g_assert_not_reached(); 164 } 165 166 for (i = 0; i < sc->num_cpus; i++) { 167 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 168 aspeed_soc_cpu_type(sc)); 169 } 170 171 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 172 object_initialize_child(obj, "scu", &s->scu, typename); 173 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 174 sc->silicon_rev); 175 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 176 "hw-strap1"); 177 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 178 "hw-strap2"); 179 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 180 "hw-prot-key"); 181 182 object_initialize_child(obj, "a7mpcore", &a->a7mpcore, 183 TYPE_A15MPCORE_PRIV); 184 185 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 186 187 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 188 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 189 190 for (i = 0; i < sc->wdts_num; i++) { 191 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 192 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 193 } 194 195 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 196 object_initialize_child(obj, "adc", &s->adc, typename); 197 198 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 199 object_initialize_child(obj, "i2c", &s->i2c, typename); 200 201 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 202 203 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 204 object_initialize_child(obj, "fmc", &s->fmc, typename); 205 206 for (i = 0; i < sc->spis_num; i++) { 207 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 208 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 209 } 210 211 for (i = 0; i < sc->ehcis_num; i++) { 212 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 213 TYPE_PLATFORM_EHCI); 214 } 215 216 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 217 218 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 219 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 220 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 221 "ram-size"); 222 223 for (i = 0; i < sc->macs_num; i++) { 224 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 225 TYPE_FTGMAC100); 226 227 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 228 } 229 230 for (i = 0; i < sc->uarts_num; i++) { 231 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 232 } 233 234 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 235 object_initialize_child(obj, "xdma", &s->xdma, typename); 236 237 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 238 object_initialize_child(obj, "gpio", &s->gpio, typename); 239 240 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 241 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 242 243 object_initialize_child(obj, "sd-controller", &s->sdhci, 244 TYPE_ASPEED_SDHCI); 245 246 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 247 248 /* Init sd card slot class here so that they're under the correct parent */ 249 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 250 object_initialize_child(obj, "sd-controller.sdhci[*]", 251 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 252 } 253 254 object_initialize_child(obj, "emmc-controller", &s->emmc, 255 TYPE_ASPEED_SDHCI); 256 257 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 258 259 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 260 TYPE_SYSBUS_SDHCI); 261 262 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 263 264 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 265 object_initialize_child(obj, "hace", &s->hace, typename); 266 267 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 268 269 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 270 271 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 272 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 273 object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); 274 object_initialize_child(obj, "emmc-boot-controller", 275 &s->emmc_boot_controller, 276 TYPE_UNIMPLEMENTED_DEVICE); 277 278 for (i = 0; i < ASPEED_FSI_NUM; i++) { 279 object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); 280 } 281 } 282 283 /* 284 * ASPEED ast2600 has 0xf as cluster ID 285 * 286 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 287 */ 288 static uint64_t aspeed_calc_affinity(int cpu) 289 { 290 return (0xf << ARM_AFF1_SHIFT) | cpu; 291 } 292 293 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 294 { 295 int i; 296 Aspeed2600SoCState *a = ASPEED2600_SOC(dev); 297 AspeedSoCState *s = ASPEED_SOC(dev); 298 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 299 qemu_irq irq; 300 g_autofree char *sram_name = NULL; 301 g_autofree char *usb_bus = g_strdup_printf("usb-bus.%u", sc->ehcis_num - 1); 302 303 /* Default boot region (SPI memory or ROMs) */ 304 memory_region_init(&s->spi_boot_container, OBJECT(s), 305 "aspeed.spi_boot_container", 0x10000000); 306 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 307 &s->spi_boot_container); 308 309 /* IO space */ 310 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 311 sc->memmap[ASPEED_DEV_IOMEM], 312 ASPEED_SOC_IOMEM_SIZE); 313 314 /* Video engine stub */ 315 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 316 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 317 318 /* eMMC Boot Controller stub */ 319 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), 320 "aspeed.emmc-boot-controller", 321 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); 322 323 /* CPU */ 324 for (i = 0; i < sc->num_cpus; i++) { 325 if (sc->num_cpus > 1) { 326 object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", 327 ASPEED_A7MPCORE_ADDR, &error_abort); 328 } 329 object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", 330 aspeed_calc_affinity(i), &error_abort); 331 332 object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, 333 &error_abort); 334 object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, 335 &error_abort); 336 object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, 337 &error_abort); 338 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 339 OBJECT(s->memory), &error_abort); 340 341 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 342 return; 343 } 344 } 345 346 /* A7MPCORE */ 347 object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, 348 &error_abort); 349 object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", 350 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 351 &error_abort); 352 353 sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); 354 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 355 356 for (i = 0; i < sc->num_cpus; i++) { 357 SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); 358 DeviceState *d = DEVICE(&a->cpu[i]); 359 360 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 361 sysbus_connect_irq(sbd, i, irq); 362 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 363 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 364 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 365 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 366 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 367 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 368 } 369 370 /* SRAM */ 371 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 372 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 373 errp)) { 374 return; 375 } 376 memory_region_add_subregion(s->memory, 377 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 378 379 /* DPMCU */ 380 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", 381 sc->memmap[ASPEED_DEV_DPMCU], 382 ASPEED_SOC_DPMCU_SIZE); 383 384 /* SCU */ 385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 386 return; 387 } 388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 389 390 /* RTC */ 391 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 392 return; 393 } 394 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 395 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 396 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 397 398 /* Timer */ 399 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 400 &error_abort); 401 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 402 return; 403 } 404 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 405 sc->memmap[ASPEED_DEV_TIMER1]); 406 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 407 irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 408 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 409 } 410 411 /* Watch dog */ 412 for (i = 0; i < sc->wdts_num; i++) { 413 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 414 415 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 416 &error_abort); 417 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 418 return; 419 } 420 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 421 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 422 } 423 424 /* ADC */ 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 426 return; 427 } 428 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 430 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 431 432 /* UART */ 433 if (!aspeed_soc_uart_realize(s, errp)) { 434 return; 435 } 436 437 /* I2C */ 438 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 439 &error_abort); 440 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 441 return; 442 } 443 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 444 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 445 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 446 sc->irqmap[ASPEED_DEV_I2C] + i); 447 /* The AST2600 I2C controller has one IRQ per bus. */ 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 449 } 450 451 /* PECI */ 452 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 453 return; 454 } 455 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 456 sc->memmap[ASPEED_DEV_PECI]); 457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 458 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 459 460 /* FMC, The number of CS is set at the board level */ 461 object_property_set_link(OBJECT(&s->fmc), "wdt2", OBJECT(&s->wdt[2].iomem), 462 &error_abort); 463 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 464 &error_abort); 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 466 return; 467 } 468 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 469 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 470 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 471 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 472 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 473 474 /* Set up an alias on the FMC CE0 region (boot default) */ 475 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 476 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 477 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 478 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 479 480 /* SPI */ 481 for (i = 0; i < sc->spis_num; i++) { 482 object_property_set_link(OBJECT(&s->spi[i]), "dram", 483 OBJECT(s->dram_mr), &error_abort); 484 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 485 return; 486 } 487 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 488 sc->memmap[ASPEED_DEV_SPI1 + i]); 489 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 490 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 491 } 492 493 /* EHCI */ 494 for (i = 0; i < sc->ehcis_num; i++) { 495 if (i == sc->ehcis_num - 1) { 496 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 497 true, &error_fatal); 498 } 499 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 500 return; 501 } 502 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 503 sc->memmap[ASPEED_DEV_EHCI1 + i]); 504 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 505 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 506 } 507 508 /* UHCI */ 509 object_property_set_str(OBJECT(&s->uhci), "masterbus", usb_bus, 510 &error_fatal); 511 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 512 return; 513 } 514 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 515 sc->memmap[ASPEED_DEV_UHCI]); 516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 517 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 518 519 /* SDMC - SDRAM Memory Controller */ 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 521 return; 522 } 523 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 524 sc->memmap[ASPEED_DEV_SDMC]); 525 526 /* RAM */ 527 if (!aspeed_soc_dram_init(s, errp)) { 528 return; 529 } 530 531 /* Net */ 532 for (i = 0; i < sc->macs_num; i++) { 533 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 534 &error_abort); 535 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 536 return; 537 } 538 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 539 sc->memmap[ASPEED_DEV_ETH1 + i]); 540 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 541 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 542 543 object_property_set_link(OBJECT(&s->mii[i]), "nic", 544 OBJECT(&s->ftgmac100[i]), &error_abort); 545 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 546 return; 547 } 548 549 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, 550 sc->memmap[ASPEED_DEV_MII1 + i]); 551 } 552 553 /* XDMA */ 554 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 555 return; 556 } 557 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 558 sc->memmap[ASPEED_DEV_XDMA]); 559 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 560 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 561 562 /* GPIO */ 563 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 564 return; 565 } 566 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 567 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 568 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 569 570 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 571 return; 572 } 573 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 574 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 575 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 576 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 577 578 /* SDHCI */ 579 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 580 return; 581 } 582 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 583 sc->memmap[ASPEED_DEV_SDHCI]); 584 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 585 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 586 587 /* eMMC */ 588 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 589 return; 590 } 591 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, 592 sc->memmap[ASPEED_DEV_EMMC]); 593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 594 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 595 596 /* LPC */ 597 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 598 return; 599 } 600 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 601 602 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 603 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 604 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 605 606 /* 607 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 608 * 609 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 610 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 611 * shared across the subdevices, and the shared IRQ output to the VIC is at 612 * offset 0. 613 */ 614 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 615 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 616 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 617 618 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 619 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 620 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 621 622 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 623 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 624 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 625 626 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 627 qdev_get_gpio_in(DEVICE(&a->a7mpcore), 628 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 629 630 /* HACE */ 631 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 632 &error_abort); 633 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 634 return; 635 } 636 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 637 sc->memmap[ASPEED_DEV_HACE]); 638 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 639 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 640 641 /* I3C */ 642 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 643 return; 644 } 645 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 646 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 647 irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), 648 sc->irqmap[ASPEED_DEV_I3C] + i); 649 /* The AST2600 I3C controller has one IRQ per bus. */ 650 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 651 } 652 653 /* Secure Boot Controller */ 654 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 655 return; 656 } 657 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 658 659 /* FSI */ 660 for (i = 0; i < ASPEED_FSI_NUM; i++) { 661 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { 662 return; 663 } 664 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, 665 sc->memmap[ASPEED_DEV_FSI1 + i]); 666 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, 667 aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); 668 } 669 } 670 671 static bool aspeed_soc_ast2600_boot_from_emmc(AspeedSoCState *s) 672 { 673 uint32_t hw_strap1 = object_property_get_uint(OBJECT(&s->scu), 674 "hw-strap1", &error_abort); 675 return !!(hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 676 } 677 678 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 679 { 680 static const char * const valid_cpu_types[] = { 681 ARM_CPU_TYPE_NAME("cortex-a7"), 682 NULL 683 }; 684 DeviceClass *dc = DEVICE_CLASS(oc); 685 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 686 687 dc->realize = aspeed_soc_ast2600_realize; 688 /* Reason: The Aspeed SoC can only be instantiated from a board */ 689 dc->user_creatable = false; 690 691 sc->name = "ast2600-a3"; 692 sc->valid_cpu_types = valid_cpu_types; 693 sc->silicon_rev = AST2600_A3_SILICON_REV; 694 sc->sram_size = 0x16400; 695 sc->spis_num = 2; 696 sc->ehcis_num = 2; 697 sc->wdts_num = 4; 698 sc->macs_num = 4; 699 sc->uarts_num = 13; 700 sc->uarts_base = ASPEED_DEV_UART1; 701 sc->irqmap = aspeed_soc_ast2600_irqmap; 702 sc->memmap = aspeed_soc_ast2600_memmap; 703 sc->num_cpus = 2; 704 sc->get_irq = aspeed_soc_ast2600_get_irq; 705 sc->boot_from_emmc = aspeed_soc_ast2600_boot_from_emmc; 706 } 707 708 static const TypeInfo aspeed_soc_ast2600_types[] = { 709 { 710 .name = TYPE_ASPEED2600_SOC, 711 .parent = TYPE_ASPEED_SOC, 712 .instance_size = sizeof(Aspeed2600SoCState), 713 .abstract = true, 714 }, { 715 .name = "ast2600-a3", 716 .parent = TYPE_ASPEED2600_SOC, 717 .instance_init = aspeed_soc_ast2600_init, 718 .class_init = aspeed_soc_ast2600_class_init, 719 }, 720 }; 721 722 DEFINE_TYPES(aspeed_soc_ast2600_types) 723