1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "hw/misc/unimp.h" 13 #include "hw/arm/aspeed_soc.h" 14 #include "hw/char/serial.h" 15 #include "qemu/module.h" 16 #include "qemu/error-report.h" 17 #include "hw/i2c/aspeed_i2c.h" 18 #include "net/net.h" 19 #include "sysemu/sysemu.h" 20 21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 22 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 23 24 static const hwaddr aspeed_soc_ast2600_memmap[] = { 25 [ASPEED_DEV_SRAM] = 0x10000000, 26 [ASPEED_DEV_DPMCU] = 0x18000000, 27 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 28 [ASPEED_DEV_IOMEM] = 0x1E600000, 29 [ASPEED_DEV_PWM] = 0x1E610000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_SPI2] = 0x1E631000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 35 [ASPEED_DEV_MII1] = 0x1E650000, 36 [ASPEED_DEV_MII2] = 0x1E650008, 37 [ASPEED_DEV_MII3] = 0x1E650010, 38 [ASPEED_DEV_MII4] = 0x1E650018, 39 [ASPEED_DEV_ETH1] = 0x1E660000, 40 [ASPEED_DEV_ETH3] = 0x1E670000, 41 [ASPEED_DEV_ETH2] = 0x1E680000, 42 [ASPEED_DEV_ETH4] = 0x1E690000, 43 [ASPEED_DEV_VIC] = 0x1E6C0000, 44 [ASPEED_DEV_HACE] = 0x1E6D0000, 45 [ASPEED_DEV_SDMC] = 0x1E6E0000, 46 [ASPEED_DEV_SCU] = 0x1E6E2000, 47 [ASPEED_DEV_XDMA] = 0x1E6E7000, 48 [ASPEED_DEV_ADC] = 0x1E6E9000, 49 [ASPEED_DEV_DP] = 0x1E6EB000, 50 [ASPEED_DEV_SBC] = 0x1E6F2000, 51 [ASPEED_DEV_VIDEO] = 0x1E700000, 52 [ASPEED_DEV_SDHCI] = 0x1E740000, 53 [ASPEED_DEV_EMMC] = 0x1E750000, 54 [ASPEED_DEV_GPIO] = 0x1E780000, 55 [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, 56 [ASPEED_DEV_RTC] = 0x1E781000, 57 [ASPEED_DEV_TIMER1] = 0x1E782000, 58 [ASPEED_DEV_WDT] = 0x1E785000, 59 [ASPEED_DEV_LPC] = 0x1E789000, 60 [ASPEED_DEV_IBT] = 0x1E789140, 61 [ASPEED_DEV_I2C] = 0x1E78A000, 62 [ASPEED_DEV_UART1] = 0x1E783000, 63 [ASPEED_DEV_UART5] = 0x1E784000, 64 [ASPEED_DEV_VUART] = 0x1E787000, 65 [ASPEED_DEV_I3C] = 0x1E7A0000, 66 [ASPEED_DEV_SDRAM] = 0x80000000, 67 }; 68 69 #define ASPEED_A7MPCORE_ADDR 0x40460000 70 71 #define AST2600_MAX_IRQ 197 72 73 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 74 static const int aspeed_soc_ast2600_irqmap[] = { 75 [ASPEED_DEV_UART1] = 47, 76 [ASPEED_DEV_UART2] = 48, 77 [ASPEED_DEV_UART3] = 49, 78 [ASPEED_DEV_UART4] = 50, 79 [ASPEED_DEV_UART5] = 8, 80 [ASPEED_DEV_VUART] = 8, 81 [ASPEED_DEV_FMC] = 39, 82 [ASPEED_DEV_SDMC] = 0, 83 [ASPEED_DEV_SCU] = 12, 84 [ASPEED_DEV_ADC] = 78, 85 [ASPEED_DEV_XDMA] = 6, 86 [ASPEED_DEV_SDHCI] = 43, 87 [ASPEED_DEV_EHCI1] = 5, 88 [ASPEED_DEV_EHCI2] = 9, 89 [ASPEED_DEV_EMMC] = 15, 90 [ASPEED_DEV_GPIO] = 40, 91 [ASPEED_DEV_GPIO_1_8V] = 11, 92 [ASPEED_DEV_RTC] = 13, 93 [ASPEED_DEV_TIMER1] = 16, 94 [ASPEED_DEV_TIMER2] = 17, 95 [ASPEED_DEV_TIMER3] = 18, 96 [ASPEED_DEV_TIMER4] = 19, 97 [ASPEED_DEV_TIMER5] = 20, 98 [ASPEED_DEV_TIMER6] = 21, 99 [ASPEED_DEV_TIMER7] = 22, 100 [ASPEED_DEV_TIMER8] = 23, 101 [ASPEED_DEV_WDT] = 24, 102 [ASPEED_DEV_PWM] = 44, 103 [ASPEED_DEV_LPC] = 35, 104 [ASPEED_DEV_IBT] = 143, 105 [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ 106 [ASPEED_DEV_ETH1] = 2, 107 [ASPEED_DEV_ETH2] = 3, 108 [ASPEED_DEV_HACE] = 4, 109 [ASPEED_DEV_ETH3] = 32, 110 [ASPEED_DEV_ETH4] = 33, 111 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 112 [ASPEED_DEV_DP] = 62, 113 [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ 114 }; 115 116 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 117 { 118 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 119 120 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 121 } 122 123 static void aspeed_soc_ast2600_init(Object *obj) 124 { 125 AspeedSoCState *s = ASPEED_SOC(obj); 126 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 127 int i; 128 char socname[8]; 129 char typename[64]; 130 131 if (sscanf(sc->name, "%7s", socname) != 1) { 132 g_assert_not_reached(); 133 } 134 135 for (i = 0; i < sc->num_cpus; i++) { 136 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 137 } 138 139 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 140 object_initialize_child(obj, "scu", &s->scu, typename); 141 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 142 sc->silicon_rev); 143 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 144 "hw-strap1"); 145 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 146 "hw-strap2"); 147 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 148 "hw-prot-key"); 149 150 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 151 TYPE_A15MPCORE_PRIV); 152 153 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 154 155 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 156 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 157 158 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 159 object_initialize_child(obj, "adc", &s->adc, typename); 160 161 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 162 object_initialize_child(obj, "i2c", &s->i2c, typename); 163 164 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 165 object_initialize_child(obj, "fmc", &s->fmc, typename); 166 167 for (i = 0; i < sc->spis_num; i++) { 168 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 169 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 170 } 171 172 for (i = 0; i < sc->ehcis_num; i++) { 173 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 174 TYPE_PLATFORM_EHCI); 175 } 176 177 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 178 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 179 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 180 "ram-size"); 181 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 182 "max-ram-size"); 183 184 for (i = 0; i < sc->wdts_num; i++) { 185 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 186 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 187 } 188 189 for (i = 0; i < sc->macs_num; i++) { 190 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 191 TYPE_FTGMAC100); 192 193 object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); 194 } 195 196 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 197 object_initialize_child(obj, "xdma", &s->xdma, typename); 198 199 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 200 object_initialize_child(obj, "gpio", &s->gpio, typename); 201 202 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 203 object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); 204 205 object_initialize_child(obj, "sd-controller", &s->sdhci, 206 TYPE_ASPEED_SDHCI); 207 208 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 209 210 /* Init sd card slot class here so that they're under the correct parent */ 211 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 212 object_initialize_child(obj, "sd-controller.sdhci[*]", 213 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); 214 } 215 216 object_initialize_child(obj, "emmc-controller", &s->emmc, 217 TYPE_ASPEED_SDHCI); 218 219 object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 220 221 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 222 TYPE_SYSBUS_SDHCI); 223 224 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 225 226 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 227 object_initialize_child(obj, "hace", &s->hace, typename); 228 229 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); 230 231 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 232 } 233 234 /* 235 * ASPEED ast2600 has 0xf as cluster ID 236 * 237 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register 238 */ 239 static uint64_t aspeed_calc_affinity(int cpu) 240 { 241 return (0xf << ARM_AFF1_SHIFT) | cpu; 242 } 243 244 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 245 { 246 int i; 247 AspeedSoCState *s = ASPEED_SOC(dev); 248 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 249 Error *err = NULL; 250 qemu_irq irq; 251 252 /* IO space */ 253 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], 254 ASPEED_SOC_IOMEM_SIZE); 255 256 /* Video engine stub */ 257 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], 258 0x1000); 259 260 /* CPU */ 261 for (i = 0; i < sc->num_cpus; i++) { 262 if (sc->num_cpus > 1) { 263 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 264 ASPEED_A7MPCORE_ADDR, &error_abort); 265 } 266 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 267 aspeed_calc_affinity(i), &error_abort); 268 269 object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 270 &error_abort); 271 272 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { 273 return; 274 } 275 } 276 277 /* A7MPCORE */ 278 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 279 &error_abort); 280 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 281 ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), 282 &error_abort); 283 284 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 285 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 286 287 for (i = 0; i < sc->num_cpus; i++) { 288 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 289 DeviceState *d = DEVICE(qemu_get_cpu(i)); 290 291 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 292 sysbus_connect_irq(sbd, i, irq); 293 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 294 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 295 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 296 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 297 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 298 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 299 } 300 301 /* SRAM */ 302 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 303 sc->sram_size, &err); 304 if (err) { 305 error_propagate(errp, err); 306 return; 307 } 308 memory_region_add_subregion(get_system_memory(), 309 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 310 311 /* DPMCU */ 312 create_unimplemented_device("aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], 313 ASPEED_SOC_DPMCU_SIZE); 314 315 /* SCU */ 316 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 317 return; 318 } 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 320 321 /* RTC */ 322 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 323 return; 324 } 325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 327 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 328 329 /* Timer */ 330 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 331 &error_abort); 332 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 333 return; 334 } 335 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 336 sc->memmap[ASPEED_DEV_TIMER1]); 337 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 338 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 340 } 341 342 /* ADC */ 343 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 344 return; 345 } 346 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 348 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 349 350 /* UART - attach an 8250 to the IO space as our UART */ 351 serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, 352 aspeed_soc_get_irq(s, s->uart_default), 38400, 353 serial_hd(0), DEVICE_LITTLE_ENDIAN); 354 355 /* I2C */ 356 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 357 &error_abort); 358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 359 return; 360 } 361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 362 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 363 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 364 sc->irqmap[ASPEED_DEV_I2C] + i); 365 /* The AST2600 I2C controller has one IRQ per bus. */ 366 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 367 } 368 369 /* FMC, The number of CS is set at the board level */ 370 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 371 &error_abort); 372 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 373 return; 374 } 375 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 377 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 379 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 380 381 /* SPI */ 382 for (i = 0; i < sc->spis_num; i++) { 383 object_property_set_link(OBJECT(&s->spi[i]), "dram", 384 OBJECT(s->dram_mr), &error_abort); 385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 386 return; 387 } 388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 389 sc->memmap[ASPEED_DEV_SPI1 + i]); 390 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 391 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 392 } 393 394 /* EHCI */ 395 for (i = 0; i < sc->ehcis_num; i++) { 396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 397 return; 398 } 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 400 sc->memmap[ASPEED_DEV_EHCI1 + i]); 401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 402 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 403 } 404 405 /* SDMC - SDRAM Memory Controller */ 406 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 407 return; 408 } 409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); 410 411 /* Watch dog */ 412 for (i = 0; i < sc->wdts_num; i++) { 413 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 414 415 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 416 &error_abort); 417 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 418 return; 419 } 420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 421 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 422 } 423 424 /* Net */ 425 for (i = 0; i < sc->macs_num; i++) { 426 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 427 &error_abort); 428 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 429 return; 430 } 431 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 432 sc->memmap[ASPEED_DEV_ETH1 + i]); 433 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 434 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 435 436 object_property_set_link(OBJECT(&s->mii[i]), "nic", 437 OBJECT(&s->ftgmac100[i]), &error_abort); 438 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { 439 return; 440 } 441 442 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 443 sc->memmap[ASPEED_DEV_MII1 + i]); 444 } 445 446 /* XDMA */ 447 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 448 return; 449 } 450 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 451 sc->memmap[ASPEED_DEV_XDMA]); 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 453 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 454 455 /* GPIO */ 456 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 457 return; 458 } 459 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); 460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 461 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 462 463 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { 464 return; 465 } 466 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 467 sc->memmap[ASPEED_DEV_GPIO_1_8V]); 468 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 469 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); 470 471 /* SDHCI */ 472 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 473 return; 474 } 475 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 476 sc->memmap[ASPEED_DEV_SDHCI]); 477 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 478 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 479 480 /* eMMC */ 481 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { 482 return; 483 } 484 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); 485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 486 aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); 487 488 /* LPC */ 489 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 490 return; 491 } 492 sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 493 494 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 495 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 496 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 497 498 /* 499 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. 500 * 501 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters 502 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ 503 * shared across the subdevices, and the shared IRQ output to the VIC is at 504 * offset 0. 505 */ 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 507 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 508 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 509 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 511 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 512 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 513 514 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 515 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 516 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 517 518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 519 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 520 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 521 522 /* HACE */ 523 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 524 &error_abort); 525 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 526 return; 527 } 528 sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); 529 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 530 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 531 532 /* I3C */ 533 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { 534 return; 535 } 536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); 537 for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { 538 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 539 sc->irqmap[ASPEED_DEV_I3C] + i); 540 /* The AST2600 I3C controller has one IRQ per bus. */ 541 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); 542 } 543 544 /* Secure Boot Controller */ 545 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 546 return; 547 } 548 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 549 } 550 551 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 552 { 553 DeviceClass *dc = DEVICE_CLASS(oc); 554 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 555 556 dc->realize = aspeed_soc_ast2600_realize; 557 558 sc->name = "ast2600-a3"; 559 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 560 sc->silicon_rev = AST2600_A3_SILICON_REV; 561 sc->sram_size = 0x16400; 562 sc->spis_num = 2; 563 sc->ehcis_num = 2; 564 sc->wdts_num = 4; 565 sc->macs_num = 4; 566 sc->irqmap = aspeed_soc_ast2600_irqmap; 567 sc->memmap = aspeed_soc_ast2600_memmap; 568 sc->num_cpus = 2; 569 } 570 571 static const TypeInfo aspeed_soc_ast2600_type_info = { 572 .name = "ast2600-a3", 573 .parent = TYPE_ASPEED_SOC, 574 .instance_size = sizeof(AspeedSoCState), 575 .instance_init = aspeed_soc_ast2600_init, 576 .class_init = aspeed_soc_ast2600_class_init, 577 .class_size = sizeof(AspeedSoCClass), 578 }; 579 580 static void aspeed_soc_register_types(void) 581 { 582 type_register_static(&aspeed_soc_ast2600_type_info); 583 }; 584 585 type_init(aspeed_soc_register_types) 586