1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); 131 } 132 133 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 134 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), typename); 135 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 136 sc->silicon_rev); 137 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 138 "hw-strap1"); 139 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 140 "hw-strap2"); 141 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 142 "hw-prot-key"); 143 144 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 145 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 146 147 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc), 148 TYPE_ASPEED_RTC); 149 150 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 151 sysbus_init_child_obj(obj, "timerctrl", &s->timerctrl, 152 sizeof(s->timerctrl), typename); 153 154 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 155 sysbus_init_child_obj(obj, "i2c", &s->i2c, sizeof(s->i2c), typename); 156 157 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 158 sysbus_init_child_obj(obj, "fmc", &s->fmc, sizeof(s->fmc), typename); 159 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 160 161 for (i = 0; i < sc->spis_num; i++) { 162 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 163 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], 164 sizeof(s->spi[i]), typename); 165 } 166 167 for (i = 0; i < sc->ehcis_num; i++) { 168 sysbus_init_child_obj(obj, "ehci[*]", &s->ehci[i], 169 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 170 } 171 172 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 173 sysbus_init_child_obj(obj, "sdmc", &s->sdmc, sizeof(s->sdmc), typename); 174 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 175 "ram-size"); 176 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 177 "max-ram-size"); 178 179 for (i = 0; i < sc->wdts_num; i++) { 180 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 181 sysbus_init_child_obj(obj, "wdt[*]", &s->wdt[i], 182 sizeof(s->wdt[i]), typename); 183 } 184 185 for (i = 0; i < sc->macs_num; i++) { 186 sysbus_init_child_obj(obj, "ftgmac100[*]", &s->ftgmac100[i], 187 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 188 189 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 190 TYPE_ASPEED_MII); 191 } 192 193 sysbus_init_child_obj(obj, "xdma", &s->xdma, sizeof(s->xdma), 194 TYPE_ASPEED_XDMA); 195 196 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 197 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), typename); 198 199 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 200 sysbus_init_child_obj(obj, "gpio_1_8v", &s->gpio_1_8v, 201 sizeof(s->gpio_1_8v), typename); 202 203 sysbus_init_child_obj(obj, "sd-controller", &s->sdhci, 204 sizeof(s->sdhci), TYPE_ASPEED_SDHCI); 205 206 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 207 208 /* Init sd card slot class here so that they're under the correct parent */ 209 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 210 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 211 &s->sdhci.slots[i], 212 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 213 } 214 215 sysbus_init_child_obj(obj, "emmc-controller", &s->emmc, 216 sizeof(s->emmc), TYPE_ASPEED_SDHCI); 217 218 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 219 220 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 221 &s->emmc.slots[0], sizeof(s->emmc.slots[0]), 222 TYPE_SYSBUS_SDHCI); 223 } 224 225 /* 226 * ASPEED ast2600 has 0xf as cluster ID 227 * 228 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 229 */ 230 static uint64_t aspeed_calc_affinity(int cpu) 231 { 232 return (0xf << ARM_AFF1_SHIFT) | cpu; 233 } 234 235 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 236 { 237 int i; 238 AspeedSoCState *s = ASPEED_SOC(dev); 239 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 240 Error *err = NULL, *local_err = NULL; 241 qemu_irq irq; 242 243 /* IO space */ 244 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 245 ASPEED_SOC_IOMEM_SIZE); 246 247 /* Video engine stub */ 248 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 249 0x1000); 250 251 /* CPU */ 252 for (i = 0; i < sc->num_cpus; i++) { 253 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 254 "psci-conduit", &error_abort); 255 if (sc->num_cpus > 1) { 256 object_property_set_int(OBJECT(&s->cpu[i]), 257 ASPEED_A7MPCORE_ADDR, 258 "reset-cbar", &error_abort); 259 } 260 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 261 "mp-affinity", &error_abort); 262 263 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 264 &error_abort); 265 266 /* 267 * TODO: the secondary CPUs are started and a boot helper 268 * is needed when using -kernel 269 */ 270 271 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 272 if (err) { 273 error_propagate(errp, err); 274 return; 275 } 276 } 277 278 /* A7MPCORE */ 279 object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu", 280 &error_abort); 281 object_property_set_int(OBJECT(&s->a7mpcore), 282 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 283 "num-irq", &error_abort); 284 285 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 286 &error_abort); 287 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 288 289 for (i = 0; i < sc->num_cpus; i++) { 290 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 291 DeviceState *d = DEVICE(qemu_get_cpu(i)); 292 293 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 294 sysbus_connect_irq(sbd, i, irq); 295 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 296 sysbus_connect_irq(sbd, i + sc->num_cpus, irq); 297 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 298 sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); 299 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 300 sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); 301 } 302 303 /* SRAM */ 304 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 305 sc->sram_size, &err); 306 if (err) { 307 error_propagate(errp, err); 308 return; 309 } 310 memory_region_add_subregion(get_system_memory(), 311 sc->memmap[ASPEED_SRAM], &s->sram); 312 313 /* SCU */ 314 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 315 if (err) { 316 error_propagate(errp, err); 317 return; 318 } 319 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 320 321 /* RTC */ 322 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 323 if (err) { 324 error_propagate(errp, err); 325 return; 326 } 327 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 329 aspeed_soc_get_irq(s, ASPEED_RTC)); 330 331 /* Timer */ 332 object_property_set_link(OBJECT(&s->timerctrl), 333 OBJECT(&s->scu), "scu", &error_abort); 334 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 335 if (err) { 336 error_propagate(errp, err); 337 return; 338 } 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 340 sc->memmap[ASPEED_TIMER1]); 341 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 342 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 344 } 345 346 /* UART - attach an 8250 to the IO space as our UART5 */ 347 if (serial_hd(0)) { 348 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 349 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 350 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 351 } 352 353 /* I2C */ 354 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 355 if (err) { 356 error_propagate(errp, err); 357 return; 358 } 359 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 360 if (err) { 361 error_propagate(errp, err); 362 return; 363 } 364 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 365 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 366 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 367 sc->irqmap[ASPEED_I2C] + i); 368 /* 369 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 370 * IRQ (AST2400 and AST2500) and connect all bussses. 371 */ 372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 373 } 374 375 /* FMC, The number of CS is set at the board level */ 376 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 377 if (err) { 378 error_propagate(errp, err); 379 return; 380 } 381 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 382 "sdram-base", &err); 383 if (err) { 384 error_propagate(errp, err); 385 return; 386 } 387 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 393 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 394 s->fmc.ctrl->flash_window_base); 395 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 396 aspeed_soc_get_irq(s, ASPEED_FMC)); 397 398 /* SPI */ 399 for (i = 0; i < sc->spis_num; i++) { 400 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 401 "dram", &err); 402 if (err) { 403 error_propagate(errp, err); 404 return; 405 } 406 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 407 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 408 &local_err); 409 error_propagate(&err, local_err); 410 if (err) { 411 error_propagate(errp, err); 412 return; 413 } 414 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 415 sc->memmap[ASPEED_SPI1 + i]); 416 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 417 s->spi[i].ctrl->flash_window_base); 418 } 419 420 /* EHCI */ 421 for (i = 0; i < sc->ehcis_num; i++) { 422 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); 423 if (err) { 424 error_propagate(errp, err); 425 return; 426 } 427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 428 sc->memmap[ASPEED_EHCI1 + i]); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 430 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 431 } 432 433 /* SDMC - SDRAM Memory Controller */ 434 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 435 if (err) { 436 error_propagate(errp, err); 437 return; 438 } 439 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 440 441 /* Watch dog */ 442 for (i = 0; i < sc->wdts_num; i++) { 443 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 444 445 object_property_set_link(OBJECT(&s->wdt[i]), 446 OBJECT(&s->scu), "scu", &error_abort); 447 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 448 if (err) { 449 error_propagate(errp, err); 450 return; 451 } 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 453 sc->memmap[ASPEED_WDT] + i * awc->offset); 454 } 455 456 /* Net */ 457 for (i = 0; i < sc->macs_num; i++) { 458 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 459 &err); 460 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 461 &local_err); 462 error_propagate(&err, local_err); 463 if (err) { 464 error_propagate(errp, err); 465 return; 466 } 467 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 468 sc->memmap[ASPEED_ETH1 + i]); 469 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 470 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 471 472 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 473 "nic", &error_abort); 474 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 475 &err); 476 if (err) { 477 error_propagate(errp, err); 478 return; 479 } 480 481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 482 sc->memmap[ASPEED_MII1 + i]); 483 } 484 485 /* XDMA */ 486 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 487 if (err) { 488 error_propagate(errp, err); 489 return; 490 } 491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 492 sc->memmap[ASPEED_XDMA]); 493 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 494 aspeed_soc_get_irq(s, ASPEED_XDMA)); 495 496 /* GPIO */ 497 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 498 if (err) { 499 error_propagate(errp, err); 500 return; 501 } 502 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 504 aspeed_soc_get_irq(s, ASPEED_GPIO)); 505 506 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 507 if (err) { 508 error_propagate(errp, err); 509 return; 510 } 511 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 512 sc->memmap[ASPEED_GPIO_1_8V]); 513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 514 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 515 516 /* SDHCI */ 517 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 518 if (err) { 519 error_propagate(errp, err); 520 return; 521 } 522 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 523 sc->memmap[ASPEED_SDHCI]); 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 525 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 526 527 /* eMMC */ 528 object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); 529 if (err) { 530 error_propagate(errp, err); 531 return; 532 } 533 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 534 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 535 aspeed_soc_get_irq(s, ASPEED_EMMC)); 536 } 537 538 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(oc); 541 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 542 543 dc->realize = aspeed_soc_ast2600_realize; 544 545 sc->name = "ast2600-a1"; 546 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 547 sc->silicon_rev = AST2600_A1_SILICON_REV; 548 sc->sram_size = 0x10000; 549 sc->spis_num = 2; 550 sc->ehcis_num = 2; 551 sc->wdts_num = 4; 552 sc->macs_num = 4; 553 sc->irqmap = aspeed_soc_ast2600_irqmap; 554 sc->memmap = aspeed_soc_ast2600_memmap; 555 sc->num_cpus = 2; 556 } 557 558 static const TypeInfo aspeed_soc_ast2600_type_info = { 559 .name = "ast2600-a1", 560 .parent = TYPE_ASPEED_SOC, 561 .instance_size = sizeof(AspeedSoCState), 562 .instance_init = aspeed_soc_ast2600_init, 563 .class_init = aspeed_soc_ast2600_class_init, 564 .class_size = sizeof(AspeedSoCClass), 565 }; 566 567 static void aspeed_soc_register_types(void) 568 { 569 type_register_static(&aspeed_soc_ast2600_type_info); 570 }; 571 572 type_init(aspeed_soc_register_types) 573