1 /* 2 * ASPEED SoC 2600 family 3 * 4 * Copyright (c) 2016-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/misc/unimp.h" 15 #include "hw/arm/aspeed_soc.h" 16 #include "hw/char/serial.h" 17 #include "qemu/log.h" 18 #include "qemu/module.h" 19 #include "qemu/error-report.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "net/net.h" 22 #include "sysemu/sysemu.h" 23 24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 25 26 static const hwaddr aspeed_soc_ast2600_memmap[] = { 27 [ASPEED_SRAM] = 0x10000000, 28 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ 29 [ASPEED_IOMEM] = 0x1E600000, 30 [ASPEED_PWM] = 0x1E610000, 31 [ASPEED_FMC] = 0x1E620000, 32 [ASPEED_SPI1] = 0x1E630000, 33 [ASPEED_SPI2] = 0x1E641000, 34 [ASPEED_EHCI1] = 0x1E6A1000, 35 [ASPEED_EHCI2] = 0x1E6A3000, 36 [ASPEED_MII1] = 0x1E650000, 37 [ASPEED_MII2] = 0x1E650008, 38 [ASPEED_MII3] = 0x1E650010, 39 [ASPEED_MII4] = 0x1E650018, 40 [ASPEED_ETH1] = 0x1E660000, 41 [ASPEED_ETH3] = 0x1E670000, 42 [ASPEED_ETH2] = 0x1E680000, 43 [ASPEED_ETH4] = 0x1E690000, 44 [ASPEED_VIC] = 0x1E6C0000, 45 [ASPEED_SDMC] = 0x1E6E0000, 46 [ASPEED_SCU] = 0x1E6E2000, 47 [ASPEED_XDMA] = 0x1E6E7000, 48 [ASPEED_ADC] = 0x1E6E9000, 49 [ASPEED_VIDEO] = 0x1E700000, 50 [ASPEED_SDHCI] = 0x1E740000, 51 [ASPEED_EMMC] = 0x1E750000, 52 [ASPEED_GPIO] = 0x1E780000, 53 [ASPEED_GPIO_1_8V] = 0x1E780800, 54 [ASPEED_RTC] = 0x1E781000, 55 [ASPEED_TIMER1] = 0x1E782000, 56 [ASPEED_WDT] = 0x1E785000, 57 [ASPEED_LPC] = 0x1E789000, 58 [ASPEED_IBT] = 0x1E789140, 59 [ASPEED_I2C] = 0x1E78A000, 60 [ASPEED_UART1] = 0x1E783000, 61 [ASPEED_UART5] = 0x1E784000, 62 [ASPEED_VUART] = 0x1E787000, 63 [ASPEED_SDRAM] = 0x80000000, 64 }; 65 66 #define ASPEED_A7MPCORE_ADDR 0x40460000 67 68 #define ASPEED_SOC_AST2600_MAX_IRQ 128 69 70 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ 71 static const int aspeed_soc_ast2600_irqmap[] = { 72 [ASPEED_UART1] = 47, 73 [ASPEED_UART2] = 48, 74 [ASPEED_UART3] = 49, 75 [ASPEED_UART4] = 50, 76 [ASPEED_UART5] = 8, 77 [ASPEED_VUART] = 8, 78 [ASPEED_FMC] = 39, 79 [ASPEED_SDMC] = 0, 80 [ASPEED_SCU] = 12, 81 [ASPEED_ADC] = 78, 82 [ASPEED_XDMA] = 6, 83 [ASPEED_SDHCI] = 43, 84 [ASPEED_EHCI1] = 5, 85 [ASPEED_EHCI2] = 9, 86 [ASPEED_EMMC] = 15, 87 [ASPEED_GPIO] = 40, 88 [ASPEED_GPIO_1_8V] = 11, 89 [ASPEED_RTC] = 13, 90 [ASPEED_TIMER1] = 16, 91 [ASPEED_TIMER2] = 17, 92 [ASPEED_TIMER3] = 18, 93 [ASPEED_TIMER4] = 19, 94 [ASPEED_TIMER5] = 20, 95 [ASPEED_TIMER6] = 21, 96 [ASPEED_TIMER7] = 22, 97 [ASPEED_TIMER8] = 23, 98 [ASPEED_WDT] = 24, 99 [ASPEED_PWM] = 44, 100 [ASPEED_LPC] = 35, 101 [ASPEED_IBT] = 35, /* LPC */ 102 [ASPEED_I2C] = 110, /* 110 -> 125 */ 103 [ASPEED_ETH1] = 2, 104 [ASPEED_ETH2] = 3, 105 [ASPEED_ETH3] = 32, 106 [ASPEED_ETH4] = 33, 107 108 }; 109 110 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) 111 { 112 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 113 114 return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); 115 } 116 117 static void aspeed_soc_ast2600_init(Object *obj) 118 { 119 AspeedSoCState *s = ASPEED_SOC(obj); 120 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 121 int i; 122 char socname[8]; 123 char typename[64]; 124 125 if (sscanf(sc->name, "%7s", socname) != 1) { 126 g_assert_not_reached(); 127 } 128 129 for (i = 0; i < sc->num_cpus; i++) { 130 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), 131 sizeof(s->cpu[i]), sc->cpu_type, 132 &error_abort, NULL); 133 } 134 135 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 136 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), 137 typename); 138 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 139 sc->silicon_rev); 140 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 141 "hw-strap1"); 142 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 143 "hw-strap2"); 144 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 145 "hw-prot-key"); 146 147 sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, 148 sizeof(s->a7mpcore), TYPE_A15MPCORE_PRIV); 149 150 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc), 151 TYPE_ASPEED_RTC); 152 153 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 154 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl), 155 sizeof(s->timerctrl), typename); 156 157 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 158 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), 159 typename); 160 161 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 162 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), 163 typename); 164 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); 165 166 for (i = 0; i < sc->spis_num; i++) { 167 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 168 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), 169 sizeof(s->spi[i]), typename); 170 } 171 172 for (i = 0; i < sc->ehcis_num; i++) { 173 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), 174 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); 175 } 176 177 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 178 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), 179 typename); 180 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 181 "ram-size"); 182 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), 183 "max-ram-size"); 184 185 for (i = 0; i < sc->wdts_num; i++) { 186 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 187 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]), 188 sizeof(s->wdt[i]), typename); 189 } 190 191 for (i = 0; i < sc->macs_num; i++) { 192 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), 193 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); 194 195 sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]), 196 TYPE_ASPEED_MII); 197 } 198 199 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), 200 TYPE_ASPEED_XDMA); 201 202 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 203 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), 204 typename); 205 206 snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); 207 sysbus_init_child_obj(obj, "gpio_1_8v", OBJECT(&s->gpio_1_8v), 208 sizeof(s->gpio_1_8v), typename); 209 210 sysbus_init_child_obj(obj, "sd-controller", OBJECT(&s->sdhci), 211 sizeof(s->sdhci), TYPE_ASPEED_SDHCI); 212 213 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 214 215 /* Init sd card slot class here so that they're under the correct parent */ 216 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 217 sysbus_init_child_obj(obj, "sd-controller.sdhci[*]", 218 OBJECT(&s->sdhci.slots[i]), 219 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI); 220 } 221 222 sysbus_init_child_obj(obj, "emmc-controller", OBJECT(&s->emmc), 223 sizeof(s->emmc), TYPE_ASPEED_SDHCI); 224 225 object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 226 227 sysbus_init_child_obj(obj, "emmc-controller.sdhci", 228 OBJECT(&s->emmc.slots[0]), sizeof(s->emmc.slots[0]), 229 TYPE_SYSBUS_SDHCI); 230 } 231 232 /* 233 * ASPEED ast2600 has 0xf as cluster ID 234 * 235 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html 236 */ 237 static uint64_t aspeed_calc_affinity(int cpu) 238 { 239 return (0xf << ARM_AFF1_SHIFT) | cpu; 240 } 241 242 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) 243 { 244 int i; 245 AspeedSoCState *s = ASPEED_SOC(dev); 246 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 247 Error *err = NULL, *local_err = NULL; 248 qemu_irq irq; 249 250 /* IO space */ 251 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], 252 ASPEED_SOC_IOMEM_SIZE); 253 254 /* Video engine stub */ 255 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], 256 0x1000); 257 258 if (s->num_cpus > sc->num_cpus) { 259 warn_report("%s: invalid number of CPUs %d, using default %d", 260 sc->name, s->num_cpus, sc->num_cpus); 261 s->num_cpus = sc->num_cpus; 262 } 263 264 /* CPU */ 265 for (i = 0; i < s->num_cpus; i++) { 266 object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 267 "psci-conduit", &error_abort); 268 if (s->num_cpus > 1) { 269 object_property_set_int(OBJECT(&s->cpu[i]), 270 ASPEED_A7MPCORE_ADDR, 271 "reset-cbar", &error_abort); 272 } 273 object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 274 "mp-affinity", &error_abort); 275 276 object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 277 &error_abort); 278 279 /* 280 * TODO: the secondary CPUs are started and a boot helper 281 * is needed when using -kernel 282 */ 283 284 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 285 if (err) { 286 error_propagate(errp, err); 287 return; 288 } 289 } 290 291 /* A7MPCORE */ 292 object_property_set_int(OBJECT(&s->a7mpcore), s->num_cpus, "num-cpu", 293 &error_abort); 294 object_property_set_int(OBJECT(&s->a7mpcore), 295 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 296 "num-irq", &error_abort); 297 298 object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", 299 &error_abort); 300 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); 301 302 for (i = 0; i < s->num_cpus; i++) { 303 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); 304 DeviceState *d = DEVICE(qemu_get_cpu(i)); 305 306 irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); 307 sysbus_connect_irq(sbd, i, irq); 308 irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); 309 sysbus_connect_irq(sbd, i + s->num_cpus, irq); 310 irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); 311 sysbus_connect_irq(sbd, i + 2 * s->num_cpus, irq); 312 irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); 313 sysbus_connect_irq(sbd, i + 3 * s->num_cpus, irq); 314 } 315 316 /* SRAM */ 317 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", 318 sc->sram_size, &err); 319 if (err) { 320 error_propagate(errp, err); 321 return; 322 } 323 memory_region_add_subregion(get_system_memory(), 324 sc->memmap[ASPEED_SRAM], &s->sram); 325 326 /* SCU */ 327 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); 328 if (err) { 329 error_propagate(errp, err); 330 return; 331 } 332 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); 333 334 /* RTC */ 335 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); 336 if (err) { 337 error_propagate(errp, err); 338 return; 339 } 340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 342 aspeed_soc_get_irq(s, ASPEED_RTC)); 343 344 /* Timer */ 345 object_property_set_link(OBJECT(&s->timerctrl), 346 OBJECT(&s->scu), "scu", &error_abort); 347 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err); 348 if (err) { 349 error_propagate(errp, err); 350 return; 351 } 352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, 353 sc->memmap[ASPEED_TIMER1]); 354 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 355 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); 356 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 357 } 358 359 /* UART - attach an 8250 to the IO space as our UART5 */ 360 if (serial_hd(0)) { 361 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); 362 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, 363 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); 364 } 365 366 /* I2C */ 367 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err); 368 if (err) { 369 error_propagate(errp, err); 370 return; 371 } 372 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err); 373 if (err) { 374 error_propagate(errp, err); 375 return; 376 } 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); 378 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 379 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), 380 sc->irqmap[ASPEED_I2C] + i); 381 /* 382 * The AST2600 SoC has one IRQ per I2C bus. Skip the common 383 * IRQ (AST2400 and AST2500) and connect all bussses. 384 */ 385 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); 386 } 387 388 /* FMC, The number of CS is set at the board level */ 389 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err); 390 if (err) { 391 error_propagate(errp, err); 392 return; 393 } 394 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 395 "sdram-base", &err); 396 if (err) { 397 error_propagate(errp, err); 398 return; 399 } 400 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); 401 if (err) { 402 error_propagate(errp, err); 403 return; 404 } 405 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); 406 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, 407 s->fmc.ctrl->flash_window_base); 408 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 409 aspeed_soc_get_irq(s, ASPEED_FMC)); 410 411 /* SPI */ 412 for (i = 0; i < sc->spis_num; i++) { 413 object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 414 "dram", &err); 415 if (err) { 416 error_propagate(errp, err); 417 return; 418 } 419 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err); 420 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", 421 &local_err); 422 error_propagate(&err, local_err); 423 if (err) { 424 error_propagate(errp, err); 425 return; 426 } 427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 428 sc->memmap[ASPEED_SPI1 + i]); 429 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, 430 s->spi[i].ctrl->flash_window_base); 431 } 432 433 /* EHCI */ 434 for (i = 0; i < sc->ehcis_num; i++) { 435 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); 436 if (err) { 437 error_propagate(errp, err); 438 return; 439 } 440 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 441 sc->memmap[ASPEED_EHCI1 + i]); 442 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 443 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); 444 } 445 446 /* SDMC - SDRAM Memory Controller */ 447 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); 448 if (err) { 449 error_propagate(errp, err); 450 return; 451 } 452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); 453 454 /* Watch dog */ 455 for (i = 0; i < sc->wdts_num; i++) { 456 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 457 458 object_property_set_link(OBJECT(&s->wdt[i]), 459 OBJECT(&s->scu), "scu", &error_abort); 460 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err); 461 if (err) { 462 error_propagate(errp, err); 463 return; 464 } 465 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 466 sc->memmap[ASPEED_WDT] + i * awc->offset); 467 } 468 469 /* Net */ 470 for (i = 0; i < nb_nics && i < sc->macs_num; i++) { 471 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]); 472 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 473 &err); 474 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized", 475 &local_err); 476 error_propagate(&err, local_err); 477 if (err) { 478 error_propagate(errp, err); 479 return; 480 } 481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 482 sc->memmap[ASPEED_ETH1 + i]); 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 484 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 485 486 object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 487 "nic", &error_abort); 488 object_property_set_bool(OBJECT(&s->mii[i]), true, "realized", 489 &err); 490 if (err) { 491 error_propagate(errp, err); 492 return; 493 } 494 495 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, 496 sc->memmap[ASPEED_MII1 + i]); 497 } 498 499 /* XDMA */ 500 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err); 501 if (err) { 502 error_propagate(errp, err); 503 return; 504 } 505 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, 506 sc->memmap[ASPEED_XDMA]); 507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 508 aspeed_soc_get_irq(s, ASPEED_XDMA)); 509 510 /* GPIO */ 511 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 512 if (err) { 513 error_propagate(errp, err); 514 return; 515 } 516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); 517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 518 aspeed_soc_get_irq(s, ASPEED_GPIO)); 519 520 object_property_set_bool(OBJECT(&s->gpio_1_8v), true, "realized", &err); 521 if (err) { 522 error_propagate(errp, err); 523 return; 524 } 525 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 526 sc->memmap[ASPEED_GPIO_1_8V]); 527 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, 528 aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); 529 530 /* SDHCI */ 531 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err); 532 if (err) { 533 error_propagate(errp, err); 534 return; 535 } 536 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 537 sc->memmap[ASPEED_SDHCI]); 538 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 539 aspeed_soc_get_irq(s, ASPEED_SDHCI)); 540 541 /* eMMC */ 542 object_property_set_bool(OBJECT(&s->emmc), true, "realized", &err); 543 if (err) { 544 error_propagate(errp, err); 545 return; 546 } 547 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); 548 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, 549 aspeed_soc_get_irq(s, ASPEED_EMMC)); 550 } 551 552 static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) 553 { 554 DeviceClass *dc = DEVICE_CLASS(oc); 555 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 556 557 dc->realize = aspeed_soc_ast2600_realize; 558 559 sc->name = "ast2600-a1"; 560 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); 561 sc->silicon_rev = AST2600_A1_SILICON_REV; 562 sc->sram_size = 0x10000; 563 sc->spis_num = 2; 564 sc->ehcis_num = 2; 565 sc->wdts_num = 4; 566 sc->macs_num = 4; 567 sc->irqmap = aspeed_soc_ast2600_irqmap; 568 sc->memmap = aspeed_soc_ast2600_memmap; 569 sc->num_cpus = 2; 570 } 571 572 static const TypeInfo aspeed_soc_ast2600_type_info = { 573 .name = "ast2600-a1", 574 .parent = TYPE_ASPEED_SOC, 575 .instance_size = sizeof(AspeedSoCState), 576 .instance_init = aspeed_soc_ast2600_init, 577 .class_init = aspeed_soc_ast2600_class_init, 578 .class_size = sizeof(AspeedSoCClass), 579 }; 580 581 static void aspeed_soc_register_types(void) 582 { 583 type_register_static(&aspeed_soc_ast2600_type_info); 584 }; 585 586 type_init(aspeed_soc_register_types) 587