1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "sysemu/sysemu.h" 24 25 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 26 27 static const hwaddr aspeed_soc_ast2400_memmap[] = { 28 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 29 [ASPEED_DEV_IOMEM] = 0x1E600000, 30 [ASPEED_DEV_FMC] = 0x1E620000, 31 [ASPEED_DEV_SPI1] = 0x1E630000, 32 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 33 [ASPEED_DEV_VIC] = 0x1E6C0000, 34 [ASPEED_DEV_SDMC] = 0x1E6E0000, 35 [ASPEED_DEV_SCU] = 0x1E6E2000, 36 [ASPEED_DEV_HACE] = 0x1E6E3000, 37 [ASPEED_DEV_XDMA] = 0x1E6E7000, 38 [ASPEED_DEV_VIDEO] = 0x1E700000, 39 [ASPEED_DEV_ADC] = 0x1E6E9000, 40 [ASPEED_DEV_SRAM] = 0x1E720000, 41 [ASPEED_DEV_SDHCI] = 0x1E740000, 42 [ASPEED_DEV_GPIO] = 0x1E780000, 43 [ASPEED_DEV_RTC] = 0x1E781000, 44 [ASPEED_DEV_TIMER1] = 0x1E782000, 45 [ASPEED_DEV_WDT] = 0x1E785000, 46 [ASPEED_DEV_PWM] = 0x1E786000, 47 [ASPEED_DEV_LPC] = 0x1E789000, 48 [ASPEED_DEV_IBT] = 0x1E789140, 49 [ASPEED_DEV_I2C] = 0x1E78A000, 50 [ASPEED_DEV_PECI] = 0x1E78B000, 51 [ASPEED_DEV_ETH1] = 0x1E660000, 52 [ASPEED_DEV_ETH2] = 0x1E680000, 53 [ASPEED_DEV_UART1] = 0x1E783000, 54 [ASPEED_DEV_UART2] = 0x1E78D000, 55 [ASPEED_DEV_UART3] = 0x1E78E000, 56 [ASPEED_DEV_UART4] = 0x1E78F000, 57 [ASPEED_DEV_UART5] = 0x1E784000, 58 [ASPEED_DEV_VUART] = 0x1E787000, 59 [ASPEED_DEV_SDRAM] = 0x40000000, 60 }; 61 62 static const hwaddr aspeed_soc_ast2500_memmap[] = { 63 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 64 [ASPEED_DEV_IOMEM] = 0x1E600000, 65 [ASPEED_DEV_FMC] = 0x1E620000, 66 [ASPEED_DEV_SPI1] = 0x1E630000, 67 [ASPEED_DEV_SPI2] = 0x1E631000, 68 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 69 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 70 [ASPEED_DEV_VIC] = 0x1E6C0000, 71 [ASPEED_DEV_SDMC] = 0x1E6E0000, 72 [ASPEED_DEV_SCU] = 0x1E6E2000, 73 [ASPEED_DEV_HACE] = 0x1E6E3000, 74 [ASPEED_DEV_XDMA] = 0x1E6E7000, 75 [ASPEED_DEV_ADC] = 0x1E6E9000, 76 [ASPEED_DEV_VIDEO] = 0x1E700000, 77 [ASPEED_DEV_SRAM] = 0x1E720000, 78 [ASPEED_DEV_SDHCI] = 0x1E740000, 79 [ASPEED_DEV_GPIO] = 0x1E780000, 80 [ASPEED_DEV_RTC] = 0x1E781000, 81 [ASPEED_DEV_TIMER1] = 0x1E782000, 82 [ASPEED_DEV_WDT] = 0x1E785000, 83 [ASPEED_DEV_PWM] = 0x1E786000, 84 [ASPEED_DEV_LPC] = 0x1E789000, 85 [ASPEED_DEV_IBT] = 0x1E789140, 86 [ASPEED_DEV_I2C] = 0x1E78A000, 87 [ASPEED_DEV_PECI] = 0x1E78B000, 88 [ASPEED_DEV_ETH1] = 0x1E660000, 89 [ASPEED_DEV_ETH2] = 0x1E680000, 90 [ASPEED_DEV_UART1] = 0x1E783000, 91 [ASPEED_DEV_UART2] = 0x1E78D000, 92 [ASPEED_DEV_UART3] = 0x1E78E000, 93 [ASPEED_DEV_UART4] = 0x1E78F000, 94 [ASPEED_DEV_UART5] = 0x1E784000, 95 [ASPEED_DEV_VUART] = 0x1E787000, 96 [ASPEED_DEV_SDRAM] = 0x80000000, 97 }; 98 99 static const int aspeed_soc_ast2400_irqmap[] = { 100 [ASPEED_DEV_UART1] = 9, 101 [ASPEED_DEV_UART2] = 32, 102 [ASPEED_DEV_UART3] = 33, 103 [ASPEED_DEV_UART4] = 34, 104 [ASPEED_DEV_UART5] = 10, 105 [ASPEED_DEV_VUART] = 8, 106 [ASPEED_DEV_FMC] = 19, 107 [ASPEED_DEV_EHCI1] = 5, 108 [ASPEED_DEV_EHCI2] = 13, 109 [ASPEED_DEV_SDMC] = 0, 110 [ASPEED_DEV_SCU] = 21, 111 [ASPEED_DEV_ADC] = 31, 112 [ASPEED_DEV_GPIO] = 20, 113 [ASPEED_DEV_RTC] = 22, 114 [ASPEED_DEV_TIMER1] = 16, 115 [ASPEED_DEV_TIMER2] = 17, 116 [ASPEED_DEV_TIMER3] = 18, 117 [ASPEED_DEV_TIMER4] = 35, 118 [ASPEED_DEV_TIMER5] = 36, 119 [ASPEED_DEV_TIMER6] = 37, 120 [ASPEED_DEV_TIMER7] = 38, 121 [ASPEED_DEV_TIMER8] = 39, 122 [ASPEED_DEV_WDT] = 27, 123 [ASPEED_DEV_PWM] = 28, 124 [ASPEED_DEV_LPC] = 8, 125 [ASPEED_DEV_I2C] = 12, 126 [ASPEED_DEV_PECI] = 15, 127 [ASPEED_DEV_ETH1] = 2, 128 [ASPEED_DEV_ETH2] = 3, 129 [ASPEED_DEV_XDMA] = 6, 130 [ASPEED_DEV_SDHCI] = 26, 131 [ASPEED_DEV_HACE] = 4, 132 }; 133 134 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 135 136 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 137 { 138 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 139 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 140 141 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 142 } 143 144 static void aspeed_ast2400_soc_init(Object *obj) 145 { 146 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 147 AspeedSoCState *s = ASPEED_SOC(obj); 148 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 149 int i; 150 char socname[8]; 151 char typename[64]; 152 153 if (sscanf(sc->name, "%7s", socname) != 1) { 154 g_assert_not_reached(); 155 } 156 157 for (i = 0; i < sc->num_cpus; i++) { 158 object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); 159 } 160 161 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 162 object_initialize_child(obj, "scu", &s->scu, typename); 163 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 164 sc->silicon_rev); 165 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 166 "hw-strap1"); 167 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 168 "hw-strap2"); 169 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 170 "hw-prot-key"); 171 172 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 173 174 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 175 176 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 177 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 178 179 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 180 object_initialize_child(obj, "adc", &s->adc, typename); 181 182 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 183 object_initialize_child(obj, "i2c", &s->i2c, typename); 184 185 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 186 187 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 188 object_initialize_child(obj, "fmc", &s->fmc, typename); 189 190 for (i = 0; i < sc->spis_num; i++) { 191 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 192 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 193 } 194 195 for (i = 0; i < sc->ehcis_num; i++) { 196 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 197 TYPE_PLATFORM_EHCI); 198 } 199 200 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 201 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 202 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 203 "ram-size"); 204 205 for (i = 0; i < sc->wdts_num; i++) { 206 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 207 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 208 } 209 210 for (i = 0; i < sc->macs_num; i++) { 211 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 212 TYPE_FTGMAC100); 213 } 214 215 for (i = 0; i < sc->uarts_num; i++) { 216 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 217 } 218 219 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 220 object_initialize_child(obj, "xdma", &s->xdma, typename); 221 222 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 223 object_initialize_child(obj, "gpio", &s->gpio, typename); 224 225 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 226 227 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 228 229 /* Init sd card slot class here so that they're under the correct parent */ 230 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 231 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 232 TYPE_SYSBUS_SDHCI); 233 } 234 235 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 236 237 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 238 object_initialize_child(obj, "hace", &s->hace, typename); 239 240 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 241 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 242 } 243 244 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 245 { 246 int i; 247 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 248 AspeedSoCState *s = ASPEED_SOC(dev); 249 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 250 g_autofree char *sram_name = NULL; 251 252 /* Default boot region (SPI memory or ROMs) */ 253 memory_region_init(&s->spi_boot_container, OBJECT(s), 254 "aspeed.spi_boot_container", 0x10000000); 255 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 256 &s->spi_boot_container); 257 258 /* IO space */ 259 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 260 sc->memmap[ASPEED_DEV_IOMEM], 261 ASPEED_SOC_IOMEM_SIZE); 262 263 /* Video engine stub */ 264 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 265 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 266 267 /* CPU */ 268 for (i = 0; i < sc->num_cpus; i++) { 269 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 270 OBJECT(s->memory), &error_abort); 271 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 272 return; 273 } 274 } 275 276 /* SRAM */ 277 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 278 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 279 errp)) { 280 return; 281 } 282 memory_region_add_subregion(s->memory, 283 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 284 285 /* SCU */ 286 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 287 return; 288 } 289 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 290 291 /* VIC */ 292 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 293 return; 294 } 295 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 296 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 297 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 298 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 299 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 300 301 /* RTC */ 302 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 303 return; 304 } 305 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 306 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 307 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 308 309 /* Timer */ 310 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 311 &error_abort); 312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 313 return; 314 } 315 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 316 sc->memmap[ASPEED_DEV_TIMER1]); 317 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 318 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 320 } 321 322 /* ADC */ 323 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 324 return; 325 } 326 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 328 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 329 330 /* UART */ 331 if (!aspeed_soc_uart_realize(s, errp)) { 332 return; 333 } 334 335 /* I2C */ 336 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 337 &error_abort); 338 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 339 return; 340 } 341 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 342 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 343 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 344 345 /* PECI */ 346 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 347 return; 348 } 349 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 350 sc->memmap[ASPEED_DEV_PECI]); 351 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 352 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 353 354 /* FMC, The number of CS is set at the board level */ 355 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 356 &error_abort); 357 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 358 return; 359 } 360 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 361 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 362 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 364 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 365 366 /* Set up an alias on the FMC CE0 region (boot default) */ 367 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 368 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 369 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 370 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 371 372 /* SPI */ 373 for (i = 0; i < sc->spis_num; i++) { 374 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 375 return; 376 } 377 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 378 sc->memmap[ASPEED_DEV_SPI1 + i]); 379 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 380 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 381 } 382 383 /* EHCI */ 384 for (i = 0; i < sc->ehcis_num; i++) { 385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 386 return; 387 } 388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 389 sc->memmap[ASPEED_DEV_EHCI1 + i]); 390 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 391 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 392 } 393 394 /* SDMC - SDRAM Memory Controller */ 395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 396 return; 397 } 398 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 399 sc->memmap[ASPEED_DEV_SDMC]); 400 401 /* Watch dog */ 402 for (i = 0; i < sc->wdts_num; i++) { 403 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 404 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 405 406 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 407 &error_abort); 408 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 409 return; 410 } 411 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 412 } 413 414 /* RAM */ 415 if (!aspeed_soc_dram_init(s, errp)) { 416 return; 417 } 418 419 /* Net */ 420 for (i = 0; i < sc->macs_num; i++) { 421 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 422 &error_abort); 423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 424 return; 425 } 426 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 427 sc->memmap[ASPEED_DEV_ETH1 + i]); 428 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 429 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 430 } 431 432 /* XDMA */ 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 434 return; 435 } 436 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 437 sc->memmap[ASPEED_DEV_XDMA]); 438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 439 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 440 441 /* GPIO */ 442 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 443 return; 444 } 445 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 446 sc->memmap[ASPEED_DEV_GPIO]); 447 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 448 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 449 450 /* SDHCI */ 451 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 452 return; 453 } 454 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 455 sc->memmap[ASPEED_DEV_SDHCI]); 456 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 457 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 458 459 /* LPC */ 460 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 461 return; 462 } 463 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 464 465 /* Connect the LPC IRQ to the VIC */ 466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 467 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 468 469 /* 470 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 471 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 472 * contrast, on the AST2600, the subdevice IRQs are connected straight to 473 * the GIC). 474 * 475 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 476 * to the VIC is at offset 0. 477 */ 478 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 479 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 480 481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 482 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 483 484 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 485 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 486 487 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 488 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 489 490 /* HACE */ 491 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 492 &error_abort); 493 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 494 return; 495 } 496 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 497 sc->memmap[ASPEED_DEV_HACE]); 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 499 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 500 } 501 502 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 503 { 504 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 505 DeviceClass *dc = DEVICE_CLASS(oc); 506 507 dc->realize = aspeed_ast2400_soc_realize; 508 /* Reason: Uses serial_hds and nd_table in realize() directly */ 509 dc->user_creatable = false; 510 511 sc->name = "ast2400-a1"; 512 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); 513 sc->silicon_rev = AST2400_A1_SILICON_REV; 514 sc->sram_size = 0x8000; 515 sc->spis_num = 1; 516 sc->ehcis_num = 1; 517 sc->wdts_num = 2; 518 sc->macs_num = 2; 519 sc->uarts_num = 5; 520 sc->irqmap = aspeed_soc_ast2400_irqmap; 521 sc->memmap = aspeed_soc_ast2400_memmap; 522 sc->num_cpus = 1; 523 sc->get_irq = aspeed_soc_ast2400_get_irq; 524 } 525 526 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 527 { 528 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 529 DeviceClass *dc = DEVICE_CLASS(oc); 530 531 dc->realize = aspeed_ast2400_soc_realize; 532 /* Reason: Uses serial_hds and nd_table in realize() directly */ 533 dc->user_creatable = false; 534 535 sc->name = "ast2500-a1"; 536 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 537 sc->silicon_rev = AST2500_A1_SILICON_REV; 538 sc->sram_size = 0x9000; 539 sc->spis_num = 2; 540 sc->ehcis_num = 2; 541 sc->wdts_num = 3; 542 sc->macs_num = 2; 543 sc->uarts_num = 5; 544 sc->irqmap = aspeed_soc_ast2500_irqmap; 545 sc->memmap = aspeed_soc_ast2500_memmap; 546 sc->num_cpus = 1; 547 sc->get_irq = aspeed_soc_ast2400_get_irq; 548 } 549 550 static const TypeInfo aspeed_soc_ast2400_types[] = { 551 { 552 .name = TYPE_ASPEED2400_SOC, 553 .parent = TYPE_ASPEED_SOC, 554 .instance_init = aspeed_ast2400_soc_init, 555 .instance_size = sizeof(Aspeed2400SoCState), 556 .abstract = true, 557 }, { 558 .name = "ast2400-a1", 559 .parent = TYPE_ASPEED2400_SOC, 560 .class_init = aspeed_soc_ast2400_class_init, 561 }, { 562 .name = "ast2500-a1", 563 .parent = TYPE_ASPEED2400_SOC, 564 .class_init = aspeed_soc_ast2500_class_init, 565 }, 566 }; 567 568 DEFINE_TYPES(aspeed_soc_ast2400_types) 569