1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "sysemu/sysemu.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_VIC] = 0x1E6C0000, 35 [ASPEED_DEV_SDMC] = 0x1E6E0000, 36 [ASPEED_DEV_SCU] = 0x1E6E2000, 37 [ASPEED_DEV_HACE] = 0x1E6E3000, 38 [ASPEED_DEV_XDMA] = 0x1E6E7000, 39 [ASPEED_DEV_VIDEO] = 0x1E700000, 40 [ASPEED_DEV_ADC] = 0x1E6E9000, 41 [ASPEED_DEV_SRAM] = 0x1E720000, 42 [ASPEED_DEV_SDHCI] = 0x1E740000, 43 [ASPEED_DEV_GPIO] = 0x1E780000, 44 [ASPEED_DEV_RTC] = 0x1E781000, 45 [ASPEED_DEV_TIMER1] = 0x1E782000, 46 [ASPEED_DEV_WDT] = 0x1E785000, 47 [ASPEED_DEV_PWM] = 0x1E786000, 48 [ASPEED_DEV_LPC] = 0x1E789000, 49 [ASPEED_DEV_IBT] = 0x1E789140, 50 [ASPEED_DEV_I2C] = 0x1E78A000, 51 [ASPEED_DEV_PECI] = 0x1E78B000, 52 [ASPEED_DEV_ETH1] = 0x1E660000, 53 [ASPEED_DEV_ETH2] = 0x1E680000, 54 [ASPEED_DEV_UART1] = 0x1E783000, 55 [ASPEED_DEV_UART2] = 0x1E78D000, 56 [ASPEED_DEV_UART3] = 0x1E78E000, 57 [ASPEED_DEV_UART4] = 0x1E78F000, 58 [ASPEED_DEV_UART5] = 0x1E784000, 59 [ASPEED_DEV_VUART] = 0x1E787000, 60 [ASPEED_DEV_SDRAM] = 0x40000000, 61 }; 62 63 static const hwaddr aspeed_soc_ast2500_memmap[] = { 64 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 65 [ASPEED_DEV_IOMEM] = 0x1E600000, 66 [ASPEED_DEV_FMC] = 0x1E620000, 67 [ASPEED_DEV_SPI1] = 0x1E630000, 68 [ASPEED_DEV_SPI2] = 0x1E631000, 69 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 70 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 71 [ASPEED_DEV_VIC] = 0x1E6C0000, 72 [ASPEED_DEV_SDMC] = 0x1E6E0000, 73 [ASPEED_DEV_SCU] = 0x1E6E2000, 74 [ASPEED_DEV_HACE] = 0x1E6E3000, 75 [ASPEED_DEV_XDMA] = 0x1E6E7000, 76 [ASPEED_DEV_ADC] = 0x1E6E9000, 77 [ASPEED_DEV_VIDEO] = 0x1E700000, 78 [ASPEED_DEV_SRAM] = 0x1E720000, 79 [ASPEED_DEV_SDHCI] = 0x1E740000, 80 [ASPEED_DEV_GPIO] = 0x1E780000, 81 [ASPEED_DEV_RTC] = 0x1E781000, 82 [ASPEED_DEV_TIMER1] = 0x1E782000, 83 [ASPEED_DEV_WDT] = 0x1E785000, 84 [ASPEED_DEV_PWM] = 0x1E786000, 85 [ASPEED_DEV_LPC] = 0x1E789000, 86 [ASPEED_DEV_IBT] = 0x1E789140, 87 [ASPEED_DEV_I2C] = 0x1E78A000, 88 [ASPEED_DEV_PECI] = 0x1E78B000, 89 [ASPEED_DEV_ETH1] = 0x1E660000, 90 [ASPEED_DEV_ETH2] = 0x1E680000, 91 [ASPEED_DEV_UART1] = 0x1E783000, 92 [ASPEED_DEV_UART2] = 0x1E78D000, 93 [ASPEED_DEV_UART3] = 0x1E78E000, 94 [ASPEED_DEV_UART4] = 0x1E78F000, 95 [ASPEED_DEV_UART5] = 0x1E784000, 96 [ASPEED_DEV_VUART] = 0x1E787000, 97 [ASPEED_DEV_SDRAM] = 0x80000000, 98 }; 99 100 static const int aspeed_soc_ast2400_irqmap[] = { 101 [ASPEED_DEV_UART1] = 9, 102 [ASPEED_DEV_UART2] = 32, 103 [ASPEED_DEV_UART3] = 33, 104 [ASPEED_DEV_UART4] = 34, 105 [ASPEED_DEV_UART5] = 10, 106 [ASPEED_DEV_VUART] = 8, 107 [ASPEED_DEV_FMC] = 19, 108 [ASPEED_DEV_EHCI1] = 5, 109 [ASPEED_DEV_EHCI2] = 13, 110 [ASPEED_DEV_SDMC] = 0, 111 [ASPEED_DEV_SCU] = 21, 112 [ASPEED_DEV_ADC] = 31, 113 [ASPEED_DEV_GPIO] = 20, 114 [ASPEED_DEV_RTC] = 22, 115 [ASPEED_DEV_TIMER1] = 16, 116 [ASPEED_DEV_TIMER2] = 17, 117 [ASPEED_DEV_TIMER3] = 18, 118 [ASPEED_DEV_TIMER4] = 35, 119 [ASPEED_DEV_TIMER5] = 36, 120 [ASPEED_DEV_TIMER6] = 37, 121 [ASPEED_DEV_TIMER7] = 38, 122 [ASPEED_DEV_TIMER8] = 39, 123 [ASPEED_DEV_WDT] = 27, 124 [ASPEED_DEV_PWM] = 28, 125 [ASPEED_DEV_LPC] = 8, 126 [ASPEED_DEV_I2C] = 12, 127 [ASPEED_DEV_PECI] = 15, 128 [ASPEED_DEV_ETH1] = 2, 129 [ASPEED_DEV_ETH2] = 3, 130 [ASPEED_DEV_XDMA] = 6, 131 [ASPEED_DEV_SDHCI] = 26, 132 [ASPEED_DEV_HACE] = 4, 133 }; 134 135 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 136 137 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 138 { 139 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 141 142 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 143 } 144 145 static void aspeed_ast2400_soc_init(Object *obj) 146 { 147 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 148 AspeedSoCState *s = ASPEED_SOC(obj); 149 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 150 int i; 151 char socname[8]; 152 char typename[64]; 153 154 if (sscanf(sc->name, "%7s", socname) != 1) { 155 g_assert_not_reached(); 156 } 157 158 for (i = 0; i < sc->num_cpus; i++) { 159 object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); 160 } 161 162 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 163 object_initialize_child(obj, "scu", &s->scu, typename); 164 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 165 sc->silicon_rev); 166 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 167 "hw-strap1"); 168 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 169 "hw-strap2"); 170 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 171 "hw-prot-key"); 172 173 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 174 175 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 176 177 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 178 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 179 180 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 181 object_initialize_child(obj, "adc", &s->adc, typename); 182 183 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 184 object_initialize_child(obj, "i2c", &s->i2c, typename); 185 186 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 187 188 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 189 object_initialize_child(obj, "fmc", &s->fmc, typename); 190 191 for (i = 0; i < sc->spis_num; i++) { 192 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 193 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 194 } 195 196 for (i = 0; i < sc->ehcis_num; i++) { 197 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 198 TYPE_PLATFORM_EHCI); 199 } 200 201 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 202 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 203 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 204 "ram-size"); 205 206 for (i = 0; i < sc->wdts_num; i++) { 207 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 208 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 209 } 210 211 for (i = 0; i < sc->macs_num; i++) { 212 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 213 TYPE_FTGMAC100); 214 } 215 216 for (i = 0; i < sc->uarts_num; i++) { 217 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 218 } 219 220 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 221 object_initialize_child(obj, "xdma", &s->xdma, typename); 222 223 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 224 object_initialize_child(obj, "gpio", &s->gpio, typename); 225 226 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 227 228 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 229 230 /* Init sd card slot class here so that they're under the correct parent */ 231 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 232 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 233 TYPE_SYSBUS_SDHCI); 234 } 235 236 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 237 238 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 239 object_initialize_child(obj, "hace", &s->hace, typename); 240 241 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 242 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 243 } 244 245 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 246 { 247 int i; 248 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 249 AspeedSoCState *s = ASPEED_SOC(dev); 250 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 251 g_autofree char *sram_name = NULL; 252 253 /* Default boot region (SPI memory or ROMs) */ 254 memory_region_init(&s->spi_boot_container, OBJECT(s), 255 "aspeed.spi_boot_container", 0x10000000); 256 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 257 &s->spi_boot_container); 258 259 /* IO space */ 260 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 261 sc->memmap[ASPEED_DEV_IOMEM], 262 ASPEED_SOC_IOMEM_SIZE); 263 264 /* Video engine stub */ 265 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 266 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 267 268 /* CPU */ 269 for (i = 0; i < sc->num_cpus; i++) { 270 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 271 OBJECT(s->memory), &error_abort); 272 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 273 return; 274 } 275 } 276 277 /* SRAM */ 278 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 279 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 280 errp)) { 281 return; 282 } 283 memory_region_add_subregion(s->memory, 284 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 285 286 /* SCU */ 287 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 288 return; 289 } 290 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 291 292 /* VIC */ 293 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 294 return; 295 } 296 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 297 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 298 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 299 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 300 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 301 302 /* RTC */ 303 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 304 return; 305 } 306 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 308 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 309 310 /* Timer */ 311 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 312 &error_abort); 313 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 314 return; 315 } 316 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 317 sc->memmap[ASPEED_DEV_TIMER1]); 318 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 319 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 321 } 322 323 /* ADC */ 324 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 325 return; 326 } 327 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 329 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 330 331 /* UART */ 332 if (!aspeed_soc_uart_realize(s, errp)) { 333 return; 334 } 335 336 /* I2C */ 337 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 338 &error_abort); 339 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 340 return; 341 } 342 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 343 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 344 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 345 346 /* PECI */ 347 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 348 return; 349 } 350 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 351 sc->memmap[ASPEED_DEV_PECI]); 352 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 353 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 354 355 /* FMC, The number of CS is set at the board level */ 356 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 357 &error_abort); 358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 359 return; 360 } 361 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 363 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 364 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 365 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 366 367 /* Set up an alias on the FMC CE0 region (boot default) */ 368 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 369 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 370 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 371 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 372 373 /* SPI */ 374 for (i = 0; i < sc->spis_num; i++) { 375 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 376 return; 377 } 378 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 379 sc->memmap[ASPEED_DEV_SPI1 + i]); 380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 381 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 382 } 383 384 /* EHCI */ 385 for (i = 0; i < sc->ehcis_num; i++) { 386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 387 return; 388 } 389 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 390 sc->memmap[ASPEED_DEV_EHCI1 + i]); 391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 392 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 393 } 394 395 /* SDMC - SDRAM Memory Controller */ 396 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 397 return; 398 } 399 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 400 sc->memmap[ASPEED_DEV_SDMC]); 401 402 /* Watch dog */ 403 for (i = 0; i < sc->wdts_num; i++) { 404 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 405 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 406 407 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 408 &error_abort); 409 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 410 return; 411 } 412 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 413 } 414 415 /* RAM */ 416 if (!aspeed_soc_dram_init(s, errp)) { 417 return; 418 } 419 420 /* Net */ 421 for (i = 0; i < sc->macs_num; i++) { 422 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 423 &error_abort); 424 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 425 return; 426 } 427 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 428 sc->memmap[ASPEED_DEV_ETH1 + i]); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 430 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 431 } 432 433 /* XDMA */ 434 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 435 return; 436 } 437 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 438 sc->memmap[ASPEED_DEV_XDMA]); 439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 440 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 441 442 /* GPIO */ 443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 444 return; 445 } 446 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 447 sc->memmap[ASPEED_DEV_GPIO]); 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 449 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 450 451 /* SDHCI */ 452 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 453 return; 454 } 455 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 456 sc->memmap[ASPEED_DEV_SDHCI]); 457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 458 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 459 460 /* LPC */ 461 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 462 return; 463 } 464 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 465 466 /* Connect the LPC IRQ to the VIC */ 467 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 468 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 469 470 /* 471 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 472 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 473 * contrast, on the AST2600, the subdevice IRQs are connected straight to 474 * the GIC). 475 * 476 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 477 * to the VIC is at offset 0. 478 */ 479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 480 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 481 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 483 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 484 485 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 486 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 487 488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 489 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 490 491 /* HACE */ 492 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 493 &error_abort); 494 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 495 return; 496 } 497 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 498 sc->memmap[ASPEED_DEV_HACE]); 499 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 500 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 501 } 502 503 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 504 { 505 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 506 DeviceClass *dc = DEVICE_CLASS(oc); 507 508 dc->realize = aspeed_ast2400_soc_realize; 509 /* Reason: Uses serial_hds and nd_table in realize() directly */ 510 dc->user_creatable = false; 511 512 sc->name = "ast2400-a1"; 513 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); 514 sc->silicon_rev = AST2400_A1_SILICON_REV; 515 sc->sram_size = 0x8000; 516 sc->spis_num = 1; 517 sc->ehcis_num = 1; 518 sc->wdts_num = 2; 519 sc->macs_num = 2; 520 sc->uarts_num = 5; 521 sc->irqmap = aspeed_soc_ast2400_irqmap; 522 sc->memmap = aspeed_soc_ast2400_memmap; 523 sc->num_cpus = 1; 524 sc->get_irq = aspeed_soc_ast2400_get_irq; 525 } 526 527 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 528 { 529 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 530 DeviceClass *dc = DEVICE_CLASS(oc); 531 532 dc->realize = aspeed_ast2400_soc_realize; 533 /* Reason: Uses serial_hds and nd_table in realize() directly */ 534 dc->user_creatable = false; 535 536 sc->name = "ast2500-a1"; 537 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); 538 sc->silicon_rev = AST2500_A1_SILICON_REV; 539 sc->sram_size = 0x9000; 540 sc->spis_num = 2; 541 sc->ehcis_num = 2; 542 sc->wdts_num = 3; 543 sc->macs_num = 2; 544 sc->uarts_num = 5; 545 sc->irqmap = aspeed_soc_ast2500_irqmap; 546 sc->memmap = aspeed_soc_ast2500_memmap; 547 sc->num_cpus = 1; 548 sc->get_irq = aspeed_soc_ast2400_get_irq; 549 } 550 551 static const TypeInfo aspeed_soc_ast2400_types[] = { 552 { 553 .name = TYPE_ASPEED2400_SOC, 554 .parent = TYPE_ASPEED_SOC, 555 .instance_init = aspeed_ast2400_soc_init, 556 .instance_size = sizeof(Aspeed2400SoCState), 557 .abstract = true, 558 }, { 559 .name = "ast2400-a1", 560 .parent = TYPE_ASPEED2400_SOC, 561 .class_init = aspeed_soc_ast2400_class_init, 562 }, { 563 .name = "ast2500-a1", 564 .parent = TYPE_ASPEED2400_SOC, 565 .class_init = aspeed_soc_ast2500_class_init, 566 }, 567 }; 568 569 DEFINE_TYPES(aspeed_soc_ast2400_types) 570