1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial-mm.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "system/system.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_VIC] = 0x1E6C0000, 35 [ASPEED_DEV_SDMC] = 0x1E6E0000, 36 [ASPEED_DEV_SCU] = 0x1E6E2000, 37 [ASPEED_DEV_HACE] = 0x1E6E3000, 38 [ASPEED_DEV_GFX] = 0x1E6E6000, 39 [ASPEED_DEV_XDMA] = 0x1E6E7000, 40 [ASPEED_DEV_VIDEO] = 0x1E700000, 41 [ASPEED_DEV_ADC] = 0x1E6E9000, 42 [ASPEED_DEV_SRAM] = 0x1E720000, 43 [ASPEED_DEV_SDHCI] = 0x1E740000, 44 [ASPEED_DEV_GPIO] = 0x1E780000, 45 [ASPEED_DEV_RTC] = 0x1E781000, 46 [ASPEED_DEV_TIMER1] = 0x1E782000, 47 [ASPEED_DEV_WDT] = 0x1E785000, 48 [ASPEED_DEV_PWM] = 0x1E786000, 49 [ASPEED_DEV_LPC] = 0x1E789000, 50 [ASPEED_DEV_IBT] = 0x1E789140, 51 [ASPEED_DEV_I2C] = 0x1E78A000, 52 [ASPEED_DEV_PECI] = 0x1E78B000, 53 [ASPEED_DEV_ETH1] = 0x1E660000, 54 [ASPEED_DEV_ETH2] = 0x1E680000, 55 [ASPEED_DEV_UART1] = 0x1E783000, 56 [ASPEED_DEV_UART2] = 0x1E78D000, 57 [ASPEED_DEV_UART3] = 0x1E78E000, 58 [ASPEED_DEV_UART4] = 0x1E78F000, 59 [ASPEED_DEV_UART5] = 0x1E784000, 60 [ASPEED_DEV_VUART] = 0x1E787000, 61 [ASPEED_DEV_SDRAM] = 0x40000000, 62 }; 63 64 static const hwaddr aspeed_soc_ast2500_memmap[] = { 65 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 66 [ASPEED_DEV_IOMEM] = 0x1E600000, 67 [ASPEED_DEV_FMC] = 0x1E620000, 68 [ASPEED_DEV_SPI1] = 0x1E630000, 69 [ASPEED_DEV_SPI2] = 0x1E631000, 70 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 71 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 72 [ASPEED_DEV_VIC] = 0x1E6C0000, 73 [ASPEED_DEV_SDMC] = 0x1E6E0000, 74 [ASPEED_DEV_SCU] = 0x1E6E2000, 75 [ASPEED_DEV_HACE] = 0x1E6E3000, 76 [ASPEED_DEV_GFX] = 0x1E6E6000, 77 [ASPEED_DEV_XDMA] = 0x1E6E7000, 78 [ASPEED_DEV_ADC] = 0x1E6E9000, 79 [ASPEED_DEV_VIDEO] = 0x1E700000, 80 [ASPEED_DEV_SRAM] = 0x1E720000, 81 [ASPEED_DEV_SDHCI] = 0x1E740000, 82 [ASPEED_DEV_GPIO] = 0x1E780000, 83 [ASPEED_DEV_RTC] = 0x1E781000, 84 [ASPEED_DEV_TIMER1] = 0x1E782000, 85 [ASPEED_DEV_WDT] = 0x1E785000, 86 [ASPEED_DEV_PWM] = 0x1E786000, 87 [ASPEED_DEV_LPC] = 0x1E789000, 88 [ASPEED_DEV_IBT] = 0x1E789140, 89 [ASPEED_DEV_I2C] = 0x1E78A000, 90 [ASPEED_DEV_PECI] = 0x1E78B000, 91 [ASPEED_DEV_ETH1] = 0x1E660000, 92 [ASPEED_DEV_ETH2] = 0x1E680000, 93 [ASPEED_DEV_UART1] = 0x1E783000, 94 [ASPEED_DEV_UART2] = 0x1E78D000, 95 [ASPEED_DEV_UART3] = 0x1E78E000, 96 [ASPEED_DEV_UART4] = 0x1E78F000, 97 [ASPEED_DEV_UART5] = 0x1E784000, 98 [ASPEED_DEV_VUART] = 0x1E787000, 99 [ASPEED_DEV_SDRAM] = 0x80000000, 100 }; 101 102 static const int aspeed_soc_ast2400_irqmap[] = { 103 [ASPEED_DEV_UART1] = 9, 104 [ASPEED_DEV_UART2] = 32, 105 [ASPEED_DEV_UART3] = 33, 106 [ASPEED_DEV_UART4] = 34, 107 [ASPEED_DEV_UART5] = 10, 108 [ASPEED_DEV_VUART] = 8, 109 [ASPEED_DEV_FMC] = 19, 110 [ASPEED_DEV_EHCI1] = 5, 111 [ASPEED_DEV_EHCI2] = 13, 112 [ASPEED_DEV_SDMC] = 0, 113 [ASPEED_DEV_SCU] = 21, 114 [ASPEED_DEV_ADC] = 31, 115 [ASPEED_DEV_GFX] = 25, 116 [ASPEED_DEV_GPIO] = 20, 117 [ASPEED_DEV_RTC] = 22, 118 [ASPEED_DEV_TIMER1] = 16, 119 [ASPEED_DEV_TIMER2] = 17, 120 [ASPEED_DEV_TIMER3] = 18, 121 [ASPEED_DEV_TIMER4] = 35, 122 [ASPEED_DEV_TIMER5] = 36, 123 [ASPEED_DEV_TIMER6] = 37, 124 [ASPEED_DEV_TIMER7] = 38, 125 [ASPEED_DEV_TIMER8] = 39, 126 [ASPEED_DEV_WDT] = 27, 127 [ASPEED_DEV_PWM] = 28, 128 [ASPEED_DEV_LPC] = 8, 129 [ASPEED_DEV_I2C] = 12, 130 [ASPEED_DEV_PECI] = 15, 131 [ASPEED_DEV_ETH1] = 2, 132 [ASPEED_DEV_ETH2] = 3, 133 [ASPEED_DEV_XDMA] = 6, 134 [ASPEED_DEV_SDHCI] = 26, 135 [ASPEED_DEV_HACE] = 4, 136 }; 137 138 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 139 140 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 141 { 142 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 143 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 144 145 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 146 } 147 148 static void aspeed_ast2400_soc_init(Object *obj) 149 { 150 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 151 AspeedSoCState *s = ASPEED_SOC(obj); 152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 153 int i; 154 char socname[8]; 155 char typename[64]; 156 157 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 158 g_assert_not_reached(); 159 } 160 161 for (i = 0; i < sc->num_cpus; i++) { 162 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 163 aspeed_soc_cpu_type(sc)); 164 } 165 166 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 167 object_initialize_child(obj, "scu", &s->scu, typename); 168 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 169 sc->silicon_rev); 170 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 171 "hw-strap1"); 172 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 173 "hw-strap2"); 174 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 175 "hw-prot-key"); 176 177 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 178 179 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 180 181 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 182 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 183 184 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 185 object_initialize_child(obj, "adc", &s->adc, typename); 186 187 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 188 object_initialize_child(obj, "i2c", &s->i2c, typename); 189 190 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 191 192 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 193 object_initialize_child(obj, "fmc", &s->fmc, typename); 194 195 for (i = 0; i < sc->spis_num; i++) { 196 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 197 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 198 } 199 200 for (i = 0; i < sc->ehcis_num; i++) { 201 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 202 TYPE_PLATFORM_EHCI); 203 } 204 205 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 206 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 207 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 208 "ram-size"); 209 210 for (i = 0; i < sc->wdts_num; i++) { 211 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 212 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 213 } 214 215 for (i = 0; i < sc->macs_num; i++) { 216 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 217 TYPE_FTGMAC100); 218 } 219 220 for (i = 0; i < sc->uarts_num; i++) { 221 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 222 } 223 224 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 225 object_initialize_child(obj, "xdma", &s->xdma, typename); 226 227 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 228 object_initialize_child(obj, "gpio", &s->gpio, typename); 229 230 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 231 object_initialize_child(obj, "sdc", &s->sdhci, typename); 232 233 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 234 235 /* Init sd card slot class here so that they're under the correct parent */ 236 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 237 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 238 TYPE_SYSBUS_SDHCI); 239 } 240 241 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 242 243 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 244 object_initialize_child(obj, "hace", &s->hace, typename); 245 246 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 247 248 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 249 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 250 251 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 252 } 253 254 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 255 { 256 int i; 257 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 258 AspeedSoCState *s = ASPEED_SOC(dev); 259 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 260 g_autofree char *sram_name = NULL; 261 262 /* Default boot region (SPI memory or ROMs) */ 263 memory_region_init(&s->spi_boot_container, OBJECT(s), 264 "aspeed.spi_boot_container", 0x10000000); 265 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 266 &s->spi_boot_container); 267 268 /* IO space */ 269 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 270 sc->memmap[ASPEED_DEV_IOMEM], 271 ASPEED_SOC_IOMEM_SIZE); 272 273 /* Video engine stub */ 274 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 275 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 276 277 /* CPU */ 278 for (i = 0; i < sc->num_cpus; i++) { 279 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 280 OBJECT(s->memory), &error_abort); 281 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 282 return; 283 } 284 } 285 286 /* SRAM */ 287 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 288 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 289 errp)) { 290 return; 291 } 292 memory_region_add_subregion(s->memory, 293 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 294 295 /* SCU */ 296 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 297 return; 298 } 299 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 300 301 /* VIC */ 302 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 303 return; 304 } 305 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 306 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 307 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 308 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 309 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 310 311 /* RTC */ 312 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 313 return; 314 } 315 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 317 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 318 319 /* Timer */ 320 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 321 &error_abort); 322 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 323 return; 324 } 325 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 326 sc->memmap[ASPEED_DEV_TIMER1]); 327 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 328 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 330 } 331 332 /* ADC */ 333 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 334 return; 335 } 336 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 338 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 339 340 /* UART */ 341 if (!aspeed_soc_uart_realize(s, errp)) { 342 return; 343 } 344 345 /* I2C */ 346 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 347 &error_abort); 348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 349 return; 350 } 351 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 352 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 353 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 354 355 /* PECI */ 356 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 357 return; 358 } 359 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 360 sc->memmap[ASPEED_DEV_PECI]); 361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 362 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 363 364 /* FMC, The number of CS is set at the board level */ 365 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 366 &error_abort); 367 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 368 return; 369 } 370 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 371 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 372 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 373 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 374 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 375 376 /* Set up an alias on the FMC CE0 region (boot default) */ 377 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 378 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 379 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 380 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 381 382 /* SPI */ 383 for (i = 0; i < sc->spis_num; i++) { 384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 385 return; 386 } 387 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 388 sc->memmap[ASPEED_DEV_SPI1 + i]); 389 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 390 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 391 } 392 393 /* EHCI */ 394 for (i = 0; i < sc->ehcis_num; i++) { 395 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 396 return; 397 } 398 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 399 sc->memmap[ASPEED_DEV_EHCI1 + i]); 400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 401 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 402 } 403 404 /* SDMC - SDRAM Memory Controller */ 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 406 return; 407 } 408 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 409 sc->memmap[ASPEED_DEV_SDMC]); 410 411 /* Watch dog */ 412 for (i = 0; i < sc->wdts_num; i++) { 413 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 414 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 415 416 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 417 &error_abort); 418 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 419 return; 420 } 421 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 422 } 423 424 /* RAM */ 425 if (!aspeed_soc_dram_init(s, errp)) { 426 return; 427 } 428 429 /* Net */ 430 for (i = 0; i < sc->macs_num; i++) { 431 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 432 &error_abort); 433 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 434 return; 435 } 436 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 437 sc->memmap[ASPEED_DEV_ETH1 + i]); 438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 439 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 440 } 441 442 /* XDMA */ 443 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 444 return; 445 } 446 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 447 sc->memmap[ASPEED_DEV_XDMA]); 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 449 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 450 451 /* GPIO */ 452 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 453 return; 454 } 455 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 456 sc->memmap[ASPEED_DEV_GPIO]); 457 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 458 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 459 460 /* SDHCI */ 461 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 462 return; 463 } 464 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 465 sc->memmap[ASPEED_DEV_SDHCI]); 466 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 467 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 468 469 /* LPC */ 470 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 471 return; 472 } 473 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 474 475 /* Connect the LPC IRQ to the VIC */ 476 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 477 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 478 479 /* 480 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 481 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 482 * contrast, on the AST2600, the subdevice IRQs are connected straight to 483 * the GIC). 484 * 485 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 486 * to the VIC is at offset 0. 487 */ 488 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 489 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 490 491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 492 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 493 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 495 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 496 497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 498 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 499 500 /* HACE */ 501 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 502 &error_abort); 503 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 504 return; 505 } 506 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 507 sc->memmap[ASPEED_DEV_HACE]); 508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 509 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 510 511 /* GFX */ 512 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 513 return; 514 } 515 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 516 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 517 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 518 519 /* PWM */ 520 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 521 return; 522 } 523 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 524 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 525 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 526 } 527 528 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data) 529 { 530 static const char * const valid_cpu_types[] = { 531 ARM_CPU_TYPE_NAME("arm926"), 532 NULL 533 }; 534 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 535 DeviceClass *dc = DEVICE_CLASS(oc); 536 537 dc->realize = aspeed_ast2400_soc_realize; 538 /* Reason: Uses serial_hds and nd_table in realize() directly */ 539 dc->user_creatable = false; 540 541 sc->valid_cpu_types = valid_cpu_types; 542 sc->silicon_rev = AST2400_A1_SILICON_REV; 543 sc->sram_size = 0x8000; 544 sc->spis_num = 1; 545 sc->ehcis_num = 1; 546 sc->wdts_num = 2; 547 sc->macs_num = 2; 548 sc->uarts_num = 5; 549 sc->uarts_base = ASPEED_DEV_UART1; 550 sc->irqmap = aspeed_soc_ast2400_irqmap; 551 sc->memmap = aspeed_soc_ast2400_memmap; 552 sc->num_cpus = 1; 553 sc->get_irq = aspeed_soc_ast2400_get_irq; 554 } 555 556 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data) 557 { 558 static const char * const valid_cpu_types[] = { 559 ARM_CPU_TYPE_NAME("arm1176"), 560 NULL 561 }; 562 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 563 DeviceClass *dc = DEVICE_CLASS(oc); 564 565 dc->realize = aspeed_ast2400_soc_realize; 566 /* Reason: Uses serial_hds and nd_table in realize() directly */ 567 dc->user_creatable = false; 568 569 sc->valid_cpu_types = valid_cpu_types; 570 sc->silicon_rev = AST2500_A1_SILICON_REV; 571 sc->sram_size = 0x9000; 572 sc->spis_num = 2; 573 sc->ehcis_num = 2; 574 sc->wdts_num = 3; 575 sc->macs_num = 2; 576 sc->uarts_num = 5; 577 sc->uarts_base = ASPEED_DEV_UART1; 578 sc->irqmap = aspeed_soc_ast2500_irqmap; 579 sc->memmap = aspeed_soc_ast2500_memmap; 580 sc->num_cpus = 1; 581 sc->get_irq = aspeed_soc_ast2400_get_irq; 582 } 583 584 static const TypeInfo aspeed_soc_ast2400_types[] = { 585 { 586 .name = TYPE_ASPEED2400_SOC, 587 .parent = TYPE_ASPEED_SOC, 588 .instance_init = aspeed_ast2400_soc_init, 589 .instance_size = sizeof(Aspeed2400SoCState), 590 .abstract = true, 591 }, { 592 .name = "ast2400-a1", 593 .parent = TYPE_ASPEED2400_SOC, 594 .class_init = aspeed_soc_ast2400_class_init, 595 }, { 596 .name = "ast2500-a1", 597 .parent = TYPE_ASPEED2400_SOC, 598 .class_init = aspeed_soc_ast2500_class_init, 599 }, 600 }; 601 602 DEFINE_TYPES(aspeed_soc_ast2400_types) 603