1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial-mm.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "system/system.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_VIC] = 0x1E6C0000, 35 [ASPEED_DEV_SDMC] = 0x1E6E0000, 36 [ASPEED_DEV_SCU] = 0x1E6E2000, 37 [ASPEED_DEV_HACE] = 0x1E6E3000, 38 [ASPEED_DEV_GFX] = 0x1E6E6000, 39 [ASPEED_DEV_XDMA] = 0x1E6E7000, 40 [ASPEED_DEV_VIDEO] = 0x1E700000, 41 [ASPEED_DEV_ADC] = 0x1E6E9000, 42 [ASPEED_DEV_SRAM] = 0x1E720000, 43 [ASPEED_DEV_SDHCI] = 0x1E740000, 44 [ASPEED_DEV_GPIO] = 0x1E780000, 45 [ASPEED_DEV_RTC] = 0x1E781000, 46 [ASPEED_DEV_TIMER1] = 0x1E782000, 47 [ASPEED_DEV_WDT] = 0x1E785000, 48 [ASPEED_DEV_PWM] = 0x1E786000, 49 [ASPEED_DEV_LPC] = 0x1E789000, 50 [ASPEED_DEV_IBT] = 0x1E789140, 51 [ASPEED_DEV_I2C] = 0x1E78A000, 52 [ASPEED_DEV_PECI] = 0x1E78B000, 53 [ASPEED_DEV_ETH1] = 0x1E660000, 54 [ASPEED_DEV_ETH2] = 0x1E680000, 55 [ASPEED_DEV_UART1] = 0x1E783000, 56 [ASPEED_DEV_UART2] = 0x1E78D000, 57 [ASPEED_DEV_UART3] = 0x1E78E000, 58 [ASPEED_DEV_UART4] = 0x1E78F000, 59 [ASPEED_DEV_UART5] = 0x1E784000, 60 [ASPEED_DEV_VUART] = 0x1E787000, 61 [ASPEED_DEV_SDRAM] = 0x40000000, 62 }; 63 64 static const hwaddr aspeed_soc_ast2500_memmap[] = { 65 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 66 [ASPEED_DEV_IOMEM] = 0x1E600000, 67 [ASPEED_DEV_FMC] = 0x1E620000, 68 [ASPEED_DEV_SPI1] = 0x1E630000, 69 [ASPEED_DEV_SPI2] = 0x1E631000, 70 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 71 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 72 [ASPEED_DEV_VIC] = 0x1E6C0000, 73 [ASPEED_DEV_SDMC] = 0x1E6E0000, 74 [ASPEED_DEV_SCU] = 0x1E6E2000, 75 [ASPEED_DEV_HACE] = 0x1E6E3000, 76 [ASPEED_DEV_GFX] = 0x1E6E6000, 77 [ASPEED_DEV_XDMA] = 0x1E6E7000, 78 [ASPEED_DEV_ADC] = 0x1E6E9000, 79 [ASPEED_DEV_VIDEO] = 0x1E700000, 80 [ASPEED_DEV_SRAM] = 0x1E720000, 81 [ASPEED_DEV_SDHCI] = 0x1E740000, 82 [ASPEED_DEV_GPIO] = 0x1E780000, 83 [ASPEED_DEV_RTC] = 0x1E781000, 84 [ASPEED_DEV_TIMER1] = 0x1E782000, 85 [ASPEED_DEV_WDT] = 0x1E785000, 86 [ASPEED_DEV_PWM] = 0x1E786000, 87 [ASPEED_DEV_LPC] = 0x1E789000, 88 [ASPEED_DEV_IBT] = 0x1E789140, 89 [ASPEED_DEV_I2C] = 0x1E78A000, 90 [ASPEED_DEV_PECI] = 0x1E78B000, 91 [ASPEED_DEV_ETH1] = 0x1E660000, 92 [ASPEED_DEV_ETH2] = 0x1E680000, 93 [ASPEED_DEV_UART1] = 0x1E783000, 94 [ASPEED_DEV_UART2] = 0x1E78D000, 95 [ASPEED_DEV_UART3] = 0x1E78E000, 96 [ASPEED_DEV_UART4] = 0x1E78F000, 97 [ASPEED_DEV_UART5] = 0x1E784000, 98 [ASPEED_DEV_VUART] = 0x1E787000, 99 [ASPEED_DEV_SDRAM] = 0x80000000, 100 }; 101 102 static const int aspeed_soc_ast2400_irqmap[] = { 103 [ASPEED_DEV_UART1] = 9, 104 [ASPEED_DEV_UART2] = 32, 105 [ASPEED_DEV_UART3] = 33, 106 [ASPEED_DEV_UART4] = 34, 107 [ASPEED_DEV_UART5] = 10, 108 [ASPEED_DEV_VUART] = 8, 109 [ASPEED_DEV_FMC] = 19, 110 [ASPEED_DEV_EHCI1] = 5, 111 [ASPEED_DEV_EHCI2] = 13, 112 [ASPEED_DEV_SDMC] = 0, 113 [ASPEED_DEV_SCU] = 21, 114 [ASPEED_DEV_ADC] = 31, 115 [ASPEED_DEV_GFX] = 25, 116 [ASPEED_DEV_GPIO] = 20, 117 [ASPEED_DEV_RTC] = 22, 118 [ASPEED_DEV_TIMER1] = 16, 119 [ASPEED_DEV_TIMER2] = 17, 120 [ASPEED_DEV_TIMER3] = 18, 121 [ASPEED_DEV_TIMER4] = 35, 122 [ASPEED_DEV_TIMER5] = 36, 123 [ASPEED_DEV_TIMER6] = 37, 124 [ASPEED_DEV_TIMER7] = 38, 125 [ASPEED_DEV_TIMER8] = 39, 126 [ASPEED_DEV_WDT] = 27, 127 [ASPEED_DEV_PWM] = 28, 128 [ASPEED_DEV_LPC] = 8, 129 [ASPEED_DEV_I2C] = 12, 130 [ASPEED_DEV_PECI] = 15, 131 [ASPEED_DEV_ETH1] = 2, 132 [ASPEED_DEV_ETH2] = 3, 133 [ASPEED_DEV_XDMA] = 6, 134 [ASPEED_DEV_SDHCI] = 26, 135 [ASPEED_DEV_HACE] = 4, 136 }; 137 138 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 139 140 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 141 { 142 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 143 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 144 145 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 146 } 147 148 static void aspeed_ast2400_soc_init(Object *obj) 149 { 150 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 151 AspeedSoCState *s = ASPEED_SOC(obj); 152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 153 int i; 154 char socname[8]; 155 char typename[64]; 156 157 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) { 158 g_assert_not_reached(); 159 } 160 161 for (i = 0; i < sc->num_cpus; i++) { 162 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 163 aspeed_soc_cpu_type(sc)); 164 } 165 166 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 167 object_initialize_child(obj, "scu", &s->scu, typename); 168 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 169 sc->silicon_rev); 170 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 171 "hw-strap1"); 172 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 173 "hw-strap2"); 174 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 175 "hw-prot-key"); 176 177 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 178 179 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 180 181 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 182 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 183 184 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 185 object_initialize_child(obj, "adc", &s->adc, typename); 186 187 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 188 object_initialize_child(obj, "i2c", &s->i2c, typename); 189 190 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 191 192 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 193 object_initialize_child(obj, "fmc", &s->fmc, typename); 194 195 for (i = 0; i < sc->spis_num; i++) { 196 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 197 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 198 } 199 200 for (i = 0; i < sc->ehcis_num; i++) { 201 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 202 TYPE_PLATFORM_EHCI); 203 } 204 205 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 206 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 207 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 208 "ram-size"); 209 210 for (i = 0; i < sc->wdts_num; i++) { 211 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 212 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 213 } 214 215 for (i = 0; i < sc->macs_num; i++) { 216 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 217 TYPE_FTGMAC100); 218 } 219 220 for (i = 0; i < sc->uarts_num; i++) { 221 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 222 } 223 224 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 225 object_initialize_child(obj, "xdma", &s->xdma, typename); 226 227 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 228 object_initialize_child(obj, "gpio", &s->gpio, typename); 229 230 snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname); 231 object_initialize_child(obj, "sdc", &s->sdhci, typename); 232 233 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 234 235 /* Init sd card slot class here so that they're under the correct parent */ 236 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 237 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 238 TYPE_SYSBUS_SDHCI); 239 } 240 241 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 242 243 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 244 object_initialize_child(obj, "hace", &s->hace, typename); 245 246 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 247 248 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 249 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 250 } 251 252 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 253 { 254 int i; 255 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 256 AspeedSoCState *s = ASPEED_SOC(dev); 257 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 258 g_autofree char *sram_name = NULL; 259 260 /* Default boot region (SPI memory or ROMs) */ 261 memory_region_init(&s->spi_boot_container, OBJECT(s), 262 "aspeed.spi_boot_container", 0x10000000); 263 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 264 &s->spi_boot_container); 265 266 /* IO space */ 267 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 268 sc->memmap[ASPEED_DEV_IOMEM], 269 ASPEED_SOC_IOMEM_SIZE); 270 271 /* Video engine stub */ 272 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 273 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 274 275 /* CPU */ 276 for (i = 0; i < sc->num_cpus; i++) { 277 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 278 OBJECT(s->memory), &error_abort); 279 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 280 return; 281 } 282 } 283 284 /* SRAM */ 285 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 286 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 287 errp)) { 288 return; 289 } 290 memory_region_add_subregion(s->memory, 291 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 292 293 /* SCU */ 294 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 295 return; 296 } 297 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 298 299 /* VIC */ 300 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 301 return; 302 } 303 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 304 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 305 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 306 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 307 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 308 309 /* RTC */ 310 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 311 return; 312 } 313 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 315 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 316 317 /* Timer */ 318 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 319 &error_abort); 320 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 321 return; 322 } 323 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 324 sc->memmap[ASPEED_DEV_TIMER1]); 325 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 326 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 328 } 329 330 /* ADC */ 331 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 332 return; 333 } 334 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 336 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 337 338 /* UART */ 339 if (!aspeed_soc_uart_realize(s, errp)) { 340 return; 341 } 342 343 /* I2C */ 344 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 345 &error_abort); 346 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 347 return; 348 } 349 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 350 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 351 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 352 353 /* PECI */ 354 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 355 return; 356 } 357 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 358 sc->memmap[ASPEED_DEV_PECI]); 359 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 360 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 361 362 /* FMC, The number of CS is set at the board level */ 363 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 364 &error_abort); 365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 366 return; 367 } 368 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 369 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 370 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 371 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 372 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 373 374 /* Set up an alias on the FMC CE0 region (boot default) */ 375 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 376 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 377 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 378 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 379 380 /* SPI */ 381 for (i = 0; i < sc->spis_num; i++) { 382 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 383 return; 384 } 385 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 386 sc->memmap[ASPEED_DEV_SPI1 + i]); 387 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 388 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 389 } 390 391 /* EHCI */ 392 for (i = 0; i < sc->ehcis_num; i++) { 393 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 394 return; 395 } 396 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 397 sc->memmap[ASPEED_DEV_EHCI1 + i]); 398 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 399 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 400 } 401 402 /* SDMC - SDRAM Memory Controller */ 403 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 404 return; 405 } 406 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 407 sc->memmap[ASPEED_DEV_SDMC]); 408 409 /* Watch dog */ 410 for (i = 0; i < sc->wdts_num; i++) { 411 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 412 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 413 414 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 415 &error_abort); 416 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 417 return; 418 } 419 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 420 } 421 422 /* RAM */ 423 if (!aspeed_soc_dram_init(s, errp)) { 424 return; 425 } 426 427 /* Net */ 428 for (i = 0; i < sc->macs_num; i++) { 429 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 430 &error_abort); 431 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 432 return; 433 } 434 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 435 sc->memmap[ASPEED_DEV_ETH1 + i]); 436 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 437 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 438 } 439 440 /* XDMA */ 441 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 442 return; 443 } 444 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 445 sc->memmap[ASPEED_DEV_XDMA]); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 447 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 448 449 /* GPIO */ 450 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 451 return; 452 } 453 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 454 sc->memmap[ASPEED_DEV_GPIO]); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 456 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 457 458 /* SDHCI */ 459 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 460 return; 461 } 462 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 463 sc->memmap[ASPEED_DEV_SDHCI]); 464 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 465 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 466 467 /* LPC */ 468 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 469 return; 470 } 471 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 472 473 /* Connect the LPC IRQ to the VIC */ 474 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 475 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 476 477 /* 478 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 479 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 480 * contrast, on the AST2600, the subdevice IRQs are connected straight to 481 * the GIC). 482 * 483 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 484 * to the VIC is at offset 0. 485 */ 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 487 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 488 489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 490 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 491 492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 493 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 494 495 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 496 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 497 498 /* HACE */ 499 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 500 &error_abort); 501 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 502 return; 503 } 504 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 505 sc->memmap[ASPEED_DEV_HACE]); 506 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 507 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 508 509 /* GFX */ 510 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 511 return; 512 } 513 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 514 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 515 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 516 } 517 518 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, const void *data) 519 { 520 static const char * const valid_cpu_types[] = { 521 ARM_CPU_TYPE_NAME("arm926"), 522 NULL 523 }; 524 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 525 DeviceClass *dc = DEVICE_CLASS(oc); 526 527 dc->realize = aspeed_ast2400_soc_realize; 528 /* Reason: Uses serial_hds and nd_table in realize() directly */ 529 dc->user_creatable = false; 530 531 sc->valid_cpu_types = valid_cpu_types; 532 sc->silicon_rev = AST2400_A1_SILICON_REV; 533 sc->sram_size = 0x8000; 534 sc->spis_num = 1; 535 sc->ehcis_num = 1; 536 sc->wdts_num = 2; 537 sc->macs_num = 2; 538 sc->uarts_num = 5; 539 sc->uarts_base = ASPEED_DEV_UART1; 540 sc->irqmap = aspeed_soc_ast2400_irqmap; 541 sc->memmap = aspeed_soc_ast2400_memmap; 542 sc->num_cpus = 1; 543 sc->get_irq = aspeed_soc_ast2400_get_irq; 544 } 545 546 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, const void *data) 547 { 548 static const char * const valid_cpu_types[] = { 549 ARM_CPU_TYPE_NAME("arm1176"), 550 NULL 551 }; 552 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 553 DeviceClass *dc = DEVICE_CLASS(oc); 554 555 dc->realize = aspeed_ast2400_soc_realize; 556 /* Reason: Uses serial_hds and nd_table in realize() directly */ 557 dc->user_creatable = false; 558 559 sc->valid_cpu_types = valid_cpu_types; 560 sc->silicon_rev = AST2500_A1_SILICON_REV; 561 sc->sram_size = 0x9000; 562 sc->spis_num = 2; 563 sc->ehcis_num = 2; 564 sc->wdts_num = 3; 565 sc->macs_num = 2; 566 sc->uarts_num = 5; 567 sc->uarts_base = ASPEED_DEV_UART1; 568 sc->irqmap = aspeed_soc_ast2500_irqmap; 569 sc->memmap = aspeed_soc_ast2500_memmap; 570 sc->num_cpus = 1; 571 sc->get_irq = aspeed_soc_ast2400_get_irq; 572 } 573 574 static const TypeInfo aspeed_soc_ast2400_types[] = { 575 { 576 .name = TYPE_ASPEED2400_SOC, 577 .parent = TYPE_ASPEED_SOC, 578 .instance_init = aspeed_ast2400_soc_init, 579 .instance_size = sizeof(Aspeed2400SoCState), 580 .abstract = true, 581 }, { 582 .name = "ast2400-a1", 583 .parent = TYPE_ASPEED2400_SOC, 584 .class_init = aspeed_soc_ast2400_class_init, 585 }, { 586 .name = "ast2500-a1", 587 .parent = TYPE_ASPEED2400_SOC, 588 .class_init = aspeed_soc_ast2500_class_init, 589 }, 590 }; 591 592 DEFINE_TYPES(aspeed_soc_ast2400_types) 593