1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial-mm.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "sysemu/sysemu.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_UHCI] = 0x1E6B0000, 35 [ASPEED_DEV_VIC] = 0x1E6C0000, 36 [ASPEED_DEV_SDMC] = 0x1E6E0000, 37 [ASPEED_DEV_SCU] = 0x1E6E2000, 38 [ASPEED_DEV_HACE] = 0x1E6E3000, 39 [ASPEED_DEV_XDMA] = 0x1E6E7000, 40 [ASPEED_DEV_VIDEO] = 0x1E700000, 41 [ASPEED_DEV_ADC] = 0x1E6E9000, 42 [ASPEED_DEV_SRAM] = 0x1E720000, 43 [ASPEED_DEV_SDHCI] = 0x1E740000, 44 [ASPEED_DEV_GPIO] = 0x1E780000, 45 [ASPEED_DEV_RTC] = 0x1E781000, 46 [ASPEED_DEV_TIMER1] = 0x1E782000, 47 [ASPEED_DEV_WDT] = 0x1E785000, 48 [ASPEED_DEV_PWM] = 0x1E786000, 49 [ASPEED_DEV_LPC] = 0x1E789000, 50 [ASPEED_DEV_IBT] = 0x1E789140, 51 [ASPEED_DEV_I2C] = 0x1E78A000, 52 [ASPEED_DEV_PECI] = 0x1E78B000, 53 [ASPEED_DEV_ETH1] = 0x1E660000, 54 [ASPEED_DEV_ETH2] = 0x1E680000, 55 [ASPEED_DEV_UART1] = 0x1E783000, 56 [ASPEED_DEV_UART2] = 0x1E78D000, 57 [ASPEED_DEV_UART3] = 0x1E78E000, 58 [ASPEED_DEV_UART4] = 0x1E78F000, 59 [ASPEED_DEV_UART5] = 0x1E784000, 60 [ASPEED_DEV_VUART] = 0x1E787000, 61 [ASPEED_DEV_SDRAM] = 0x40000000, 62 }; 63 64 static const hwaddr aspeed_soc_ast2500_memmap[] = { 65 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 66 [ASPEED_DEV_IOMEM] = 0x1E600000, 67 [ASPEED_DEV_FMC] = 0x1E620000, 68 [ASPEED_DEV_SPI1] = 0x1E630000, 69 [ASPEED_DEV_SPI2] = 0x1E631000, 70 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 71 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 72 [ASPEED_DEV_UHCI] = 0x1E6B0000, 73 [ASPEED_DEV_VIC] = 0x1E6C0000, 74 [ASPEED_DEV_SDMC] = 0x1E6E0000, 75 [ASPEED_DEV_SCU] = 0x1E6E2000, 76 [ASPEED_DEV_HACE] = 0x1E6E3000, 77 [ASPEED_DEV_XDMA] = 0x1E6E7000, 78 [ASPEED_DEV_ADC] = 0x1E6E9000, 79 [ASPEED_DEV_VIDEO] = 0x1E700000, 80 [ASPEED_DEV_SRAM] = 0x1E720000, 81 [ASPEED_DEV_SDHCI] = 0x1E740000, 82 [ASPEED_DEV_GPIO] = 0x1E780000, 83 [ASPEED_DEV_RTC] = 0x1E781000, 84 [ASPEED_DEV_TIMER1] = 0x1E782000, 85 [ASPEED_DEV_WDT] = 0x1E785000, 86 [ASPEED_DEV_PWM] = 0x1E786000, 87 [ASPEED_DEV_LPC] = 0x1E789000, 88 [ASPEED_DEV_IBT] = 0x1E789140, 89 [ASPEED_DEV_I2C] = 0x1E78A000, 90 [ASPEED_DEV_PECI] = 0x1E78B000, 91 [ASPEED_DEV_ETH1] = 0x1E660000, 92 [ASPEED_DEV_ETH2] = 0x1E680000, 93 [ASPEED_DEV_UART1] = 0x1E783000, 94 [ASPEED_DEV_UART2] = 0x1E78D000, 95 [ASPEED_DEV_UART3] = 0x1E78E000, 96 [ASPEED_DEV_UART4] = 0x1E78F000, 97 [ASPEED_DEV_UART5] = 0x1E784000, 98 [ASPEED_DEV_VUART] = 0x1E787000, 99 [ASPEED_DEV_SDRAM] = 0x80000000, 100 }; 101 102 static const int aspeed_soc_ast2400_irqmap[] = { 103 [ASPEED_DEV_UART1] = 9, 104 [ASPEED_DEV_UART2] = 32, 105 [ASPEED_DEV_UART3] = 33, 106 [ASPEED_DEV_UART4] = 34, 107 [ASPEED_DEV_UART5] = 10, 108 [ASPEED_DEV_VUART] = 8, 109 [ASPEED_DEV_FMC] = 19, 110 [ASPEED_DEV_EHCI1] = 5, 111 [ASPEED_DEV_EHCI2] = 13, 112 [ASPEED_DEV_UHCI] = 14, 113 [ASPEED_DEV_SDMC] = 0, 114 [ASPEED_DEV_SCU] = 21, 115 [ASPEED_DEV_ADC] = 31, 116 [ASPEED_DEV_GPIO] = 20, 117 [ASPEED_DEV_RTC] = 22, 118 [ASPEED_DEV_TIMER1] = 16, 119 [ASPEED_DEV_TIMER2] = 17, 120 [ASPEED_DEV_TIMER3] = 18, 121 [ASPEED_DEV_TIMER4] = 35, 122 [ASPEED_DEV_TIMER5] = 36, 123 [ASPEED_DEV_TIMER6] = 37, 124 [ASPEED_DEV_TIMER7] = 38, 125 [ASPEED_DEV_TIMER8] = 39, 126 [ASPEED_DEV_WDT] = 27, 127 [ASPEED_DEV_PWM] = 28, 128 [ASPEED_DEV_LPC] = 8, 129 [ASPEED_DEV_I2C] = 12, 130 [ASPEED_DEV_PECI] = 15, 131 [ASPEED_DEV_ETH1] = 2, 132 [ASPEED_DEV_ETH2] = 3, 133 [ASPEED_DEV_XDMA] = 6, 134 [ASPEED_DEV_SDHCI] = 26, 135 [ASPEED_DEV_HACE] = 4, 136 }; 137 138 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 139 140 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 141 { 142 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 143 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 144 145 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 146 } 147 148 static void aspeed_ast2400_soc_init(Object *obj) 149 { 150 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 151 AspeedSoCState *s = ASPEED_SOC(obj); 152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 153 int i; 154 char socname[8]; 155 char typename[64]; 156 157 if (sscanf(sc->name, "%7s", socname) != 1) { 158 g_assert_not_reached(); 159 } 160 161 for (i = 0; i < sc->num_cpus; i++) { 162 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 163 aspeed_soc_cpu_type(sc)); 164 } 165 166 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 167 object_initialize_child(obj, "scu", &s->scu, typename); 168 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 169 sc->silicon_rev); 170 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 171 "hw-strap1"); 172 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 173 "hw-strap2"); 174 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 175 "hw-prot-key"); 176 177 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 178 179 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 180 181 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 182 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 183 184 for (i = 0; i < sc->wdts_num; i++) { 185 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 186 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 187 } 188 189 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 190 object_initialize_child(obj, "adc", &s->adc, typename); 191 192 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 193 object_initialize_child(obj, "i2c", &s->i2c, typename); 194 195 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 196 197 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 198 object_initialize_child(obj, "fmc", &s->fmc, typename); 199 200 for (i = 0; i < sc->spis_num; i++) { 201 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 202 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 203 } 204 205 for (i = 0; i < sc->ehcis_num; i++) { 206 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 207 TYPE_PLATFORM_EHCI); 208 } 209 210 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 211 212 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 213 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 214 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 215 "ram-size"); 216 217 for (i = 0; i < sc->macs_num; i++) { 218 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 219 TYPE_FTGMAC100); 220 } 221 222 for (i = 0; i < sc->uarts_num; i++) { 223 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 224 } 225 226 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 227 object_initialize_child(obj, "xdma", &s->xdma, typename); 228 229 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 230 object_initialize_child(obj, "gpio", &s->gpio, typename); 231 232 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 233 234 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 235 236 /* Init sd card slot class here so that they're under the correct parent */ 237 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 238 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 239 TYPE_SYSBUS_SDHCI); 240 } 241 242 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 243 244 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 245 object_initialize_child(obj, "hace", &s->hace, typename); 246 247 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 248 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 249 } 250 251 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 252 { 253 int i; 254 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 255 AspeedSoCState *s = ASPEED_SOC(dev); 256 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 257 g_autofree char *sram_name = NULL; 258 259 /* Default boot region (SPI memory or ROMs) */ 260 memory_region_init(&s->spi_boot_container, OBJECT(s), 261 "aspeed.spi_boot_container", 0x10000000); 262 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 263 &s->spi_boot_container); 264 265 /* IO space */ 266 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 267 sc->memmap[ASPEED_DEV_IOMEM], 268 ASPEED_SOC_IOMEM_SIZE); 269 270 /* Video engine stub */ 271 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 272 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 273 274 /* CPU */ 275 for (i = 0; i < sc->num_cpus; i++) { 276 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 277 OBJECT(s->memory), &error_abort); 278 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 279 return; 280 } 281 } 282 283 /* SRAM */ 284 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 285 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 286 errp)) { 287 return; 288 } 289 memory_region_add_subregion(s->memory, 290 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 291 292 /* SCU */ 293 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 294 return; 295 } 296 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 297 298 /* VIC */ 299 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 300 return; 301 } 302 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 303 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 304 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 305 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 306 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 307 308 /* RTC */ 309 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 310 return; 311 } 312 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 314 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 315 316 /* Timer */ 317 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 318 &error_abort); 319 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 320 return; 321 } 322 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 323 sc->memmap[ASPEED_DEV_TIMER1]); 324 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 325 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 327 } 328 329 /* Watch dog */ 330 for (i = 0; i < sc->wdts_num; i++) { 331 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 332 333 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 334 &error_abort); 335 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 336 return; 337 } 338 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 339 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 340 } 341 342 /* ADC */ 343 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 344 return; 345 } 346 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 347 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 348 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 349 350 /* UART */ 351 if (!aspeed_soc_uart_realize(s, errp)) { 352 return; 353 } 354 355 /* I2C */ 356 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 357 &error_abort); 358 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 359 return; 360 } 361 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 363 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 364 365 /* PECI */ 366 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 367 return; 368 } 369 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 370 sc->memmap[ASPEED_DEV_PECI]); 371 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 372 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 373 374 /* FMC, The number of CS is set at the board level */ 375 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 376 &error_abort); 377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 378 return; 379 } 380 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 381 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 382 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 384 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 385 386 /* Set up an alias on the FMC CE0 region (boot default) */ 387 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 388 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 389 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 390 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 391 392 /* SPI */ 393 for (i = 0; i < sc->spis_num; i++) { 394 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 395 return; 396 } 397 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 398 sc->memmap[ASPEED_DEV_SPI1 + i]); 399 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 400 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 401 } 402 403 /* EHCI */ 404 for (i = 0; i < sc->ehcis_num; i++) { 405 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 406 return; 407 } 408 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 409 sc->memmap[ASPEED_DEV_EHCI1 + i]); 410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 411 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 412 } 413 414 /* UHCI */ 415 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 416 return; 417 } 418 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 419 sc->memmap[ASPEED_DEV_UHCI]); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 421 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 422 423 /* SDMC - SDRAM Memory Controller */ 424 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 425 return; 426 } 427 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 428 sc->memmap[ASPEED_DEV_SDMC]); 429 430 /* RAM */ 431 if (!aspeed_soc_dram_init(s, errp)) { 432 return; 433 } 434 435 /* Net */ 436 for (i = 0; i < sc->macs_num; i++) { 437 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 438 &error_abort); 439 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 440 return; 441 } 442 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 443 sc->memmap[ASPEED_DEV_ETH1 + i]); 444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 445 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 446 } 447 448 /* XDMA */ 449 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 450 return; 451 } 452 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 453 sc->memmap[ASPEED_DEV_XDMA]); 454 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 455 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 456 457 /* GPIO */ 458 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 459 return; 460 } 461 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 462 sc->memmap[ASPEED_DEV_GPIO]); 463 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 464 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 465 466 /* SDHCI */ 467 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 468 return; 469 } 470 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 471 sc->memmap[ASPEED_DEV_SDHCI]); 472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 473 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 474 475 /* LPC */ 476 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 477 return; 478 } 479 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 480 481 /* Connect the LPC IRQ to the VIC */ 482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 483 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 484 485 /* 486 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 487 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 488 * contrast, on the AST2600, the subdevice IRQs are connected straight to 489 * the GIC). 490 * 491 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 492 * to the VIC is at offset 0. 493 */ 494 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 495 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 496 497 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 498 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 499 500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 501 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 502 503 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 504 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 505 506 /* HACE */ 507 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 508 &error_abort); 509 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 510 return; 511 } 512 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 513 sc->memmap[ASPEED_DEV_HACE]); 514 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 515 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 516 } 517 518 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 519 { 520 static const char * const valid_cpu_types[] = { 521 ARM_CPU_TYPE_NAME("arm926"), 522 NULL 523 }; 524 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 525 DeviceClass *dc = DEVICE_CLASS(oc); 526 527 dc->realize = aspeed_ast2400_soc_realize; 528 /* Reason: Uses serial_hds and nd_table in realize() directly */ 529 dc->user_creatable = false; 530 531 sc->name = "ast2400-a1"; 532 sc->valid_cpu_types = valid_cpu_types; 533 sc->silicon_rev = AST2400_A1_SILICON_REV; 534 sc->sram_size = 0x8000; 535 sc->spis_num = 1; 536 sc->ehcis_num = 1; 537 sc->wdts_num = 2; 538 sc->macs_num = 2; 539 sc->uarts_num = 5; 540 sc->uarts_base = ASPEED_DEV_UART1; 541 sc->irqmap = aspeed_soc_ast2400_irqmap; 542 sc->memmap = aspeed_soc_ast2400_memmap; 543 sc->num_cpus = 1; 544 sc->get_irq = aspeed_soc_ast2400_get_irq; 545 } 546 547 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 548 { 549 static const char * const valid_cpu_types[] = { 550 ARM_CPU_TYPE_NAME("arm1176"), 551 NULL 552 }; 553 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 554 DeviceClass *dc = DEVICE_CLASS(oc); 555 556 dc->realize = aspeed_ast2400_soc_realize; 557 /* Reason: Uses serial_hds and nd_table in realize() directly */ 558 dc->user_creatable = false; 559 560 sc->name = "ast2500-a1"; 561 sc->valid_cpu_types = valid_cpu_types; 562 sc->silicon_rev = AST2500_A1_SILICON_REV; 563 sc->sram_size = 0x9000; 564 sc->spis_num = 2; 565 sc->ehcis_num = 2; 566 sc->wdts_num = 3; 567 sc->macs_num = 2; 568 sc->uarts_num = 5; 569 sc->uarts_base = ASPEED_DEV_UART1; 570 sc->irqmap = aspeed_soc_ast2500_irqmap; 571 sc->memmap = aspeed_soc_ast2500_memmap; 572 sc->num_cpus = 1; 573 sc->get_irq = aspeed_soc_ast2400_get_irq; 574 } 575 576 static const TypeInfo aspeed_soc_ast2400_types[] = { 577 { 578 .name = TYPE_ASPEED2400_SOC, 579 .parent = TYPE_ASPEED_SOC, 580 .instance_init = aspeed_ast2400_soc_init, 581 .instance_size = sizeof(Aspeed2400SoCState), 582 .abstract = true, 583 }, { 584 .name = "ast2400-a1", 585 .parent = TYPE_ASPEED2400_SOC, 586 .class_init = aspeed_soc_ast2400_class_init, 587 }, { 588 .name = "ast2500-a1", 589 .parent = TYPE_ASPEED2400_SOC, 590 .class_init = aspeed_soc_ast2500_class_init, 591 }, 592 }; 593 594 DEFINE_TYPES(aspeed_soc_ast2400_types) 595