1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "sysemu/sysemu.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_VIC] = 0x1E6C0000, 35 [ASPEED_DEV_SDMC] = 0x1E6E0000, 36 [ASPEED_DEV_SCU] = 0x1E6E2000, 37 [ASPEED_DEV_HACE] = 0x1E6E3000, 38 [ASPEED_DEV_XDMA] = 0x1E6E7000, 39 [ASPEED_DEV_VIDEO] = 0x1E700000, 40 [ASPEED_DEV_ADC] = 0x1E6E9000, 41 [ASPEED_DEV_SRAM] = 0x1E720000, 42 [ASPEED_DEV_SDHCI] = 0x1E740000, 43 [ASPEED_DEV_GPIO] = 0x1E780000, 44 [ASPEED_DEV_RTC] = 0x1E781000, 45 [ASPEED_DEV_TIMER1] = 0x1E782000, 46 [ASPEED_DEV_WDT] = 0x1E785000, 47 [ASPEED_DEV_PWM] = 0x1E786000, 48 [ASPEED_DEV_LPC] = 0x1E789000, 49 [ASPEED_DEV_IBT] = 0x1E789140, 50 [ASPEED_DEV_I2C] = 0x1E78A000, 51 [ASPEED_DEV_PECI] = 0x1E78B000, 52 [ASPEED_DEV_ETH1] = 0x1E660000, 53 [ASPEED_DEV_ETH2] = 0x1E680000, 54 [ASPEED_DEV_UART1] = 0x1E783000, 55 [ASPEED_DEV_UART2] = 0x1E78D000, 56 [ASPEED_DEV_UART3] = 0x1E78E000, 57 [ASPEED_DEV_UART4] = 0x1E78F000, 58 [ASPEED_DEV_UART5] = 0x1E784000, 59 [ASPEED_DEV_VUART] = 0x1E787000, 60 [ASPEED_DEV_SDRAM] = 0x40000000, 61 }; 62 63 static const hwaddr aspeed_soc_ast2500_memmap[] = { 64 [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, 65 [ASPEED_DEV_IOMEM] = 0x1E600000, 66 [ASPEED_DEV_FMC] = 0x1E620000, 67 [ASPEED_DEV_SPI1] = 0x1E630000, 68 [ASPEED_DEV_SPI2] = 0x1E631000, 69 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 70 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 71 [ASPEED_DEV_VIC] = 0x1E6C0000, 72 [ASPEED_DEV_SDMC] = 0x1E6E0000, 73 [ASPEED_DEV_SCU] = 0x1E6E2000, 74 [ASPEED_DEV_HACE] = 0x1E6E3000, 75 [ASPEED_DEV_XDMA] = 0x1E6E7000, 76 [ASPEED_DEV_ADC] = 0x1E6E9000, 77 [ASPEED_DEV_VIDEO] = 0x1E700000, 78 [ASPEED_DEV_SRAM] = 0x1E720000, 79 [ASPEED_DEV_SDHCI] = 0x1E740000, 80 [ASPEED_DEV_GPIO] = 0x1E780000, 81 [ASPEED_DEV_RTC] = 0x1E781000, 82 [ASPEED_DEV_TIMER1] = 0x1E782000, 83 [ASPEED_DEV_WDT] = 0x1E785000, 84 [ASPEED_DEV_PWM] = 0x1E786000, 85 [ASPEED_DEV_LPC] = 0x1E789000, 86 [ASPEED_DEV_IBT] = 0x1E789140, 87 [ASPEED_DEV_I2C] = 0x1E78A000, 88 [ASPEED_DEV_PECI] = 0x1E78B000, 89 [ASPEED_DEV_ETH1] = 0x1E660000, 90 [ASPEED_DEV_ETH2] = 0x1E680000, 91 [ASPEED_DEV_UART1] = 0x1E783000, 92 [ASPEED_DEV_UART2] = 0x1E78D000, 93 [ASPEED_DEV_UART3] = 0x1E78E000, 94 [ASPEED_DEV_UART4] = 0x1E78F000, 95 [ASPEED_DEV_UART5] = 0x1E784000, 96 [ASPEED_DEV_VUART] = 0x1E787000, 97 [ASPEED_DEV_SDRAM] = 0x80000000, 98 }; 99 100 static const int aspeed_soc_ast2400_irqmap[] = { 101 [ASPEED_DEV_UART1] = 9, 102 [ASPEED_DEV_UART2] = 32, 103 [ASPEED_DEV_UART3] = 33, 104 [ASPEED_DEV_UART4] = 34, 105 [ASPEED_DEV_UART5] = 10, 106 [ASPEED_DEV_VUART] = 8, 107 [ASPEED_DEV_FMC] = 19, 108 [ASPEED_DEV_EHCI1] = 5, 109 [ASPEED_DEV_EHCI2] = 13, 110 [ASPEED_DEV_SDMC] = 0, 111 [ASPEED_DEV_SCU] = 21, 112 [ASPEED_DEV_ADC] = 31, 113 [ASPEED_DEV_GPIO] = 20, 114 [ASPEED_DEV_RTC] = 22, 115 [ASPEED_DEV_TIMER1] = 16, 116 [ASPEED_DEV_TIMER2] = 17, 117 [ASPEED_DEV_TIMER3] = 18, 118 [ASPEED_DEV_TIMER4] = 35, 119 [ASPEED_DEV_TIMER5] = 36, 120 [ASPEED_DEV_TIMER6] = 37, 121 [ASPEED_DEV_TIMER7] = 38, 122 [ASPEED_DEV_TIMER8] = 39, 123 [ASPEED_DEV_WDT] = 27, 124 [ASPEED_DEV_PWM] = 28, 125 [ASPEED_DEV_LPC] = 8, 126 [ASPEED_DEV_I2C] = 12, 127 [ASPEED_DEV_PECI] = 15, 128 [ASPEED_DEV_ETH1] = 2, 129 [ASPEED_DEV_ETH2] = 3, 130 [ASPEED_DEV_XDMA] = 6, 131 [ASPEED_DEV_SDHCI] = 26, 132 [ASPEED_DEV_HACE] = 4, 133 }; 134 135 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 136 137 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 138 { 139 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 140 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 141 142 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 143 } 144 145 static void aspeed_ast2400_soc_init(Object *obj) 146 { 147 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 148 AspeedSoCState *s = ASPEED_SOC(obj); 149 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 150 int i; 151 char socname[8]; 152 char typename[64]; 153 154 if (sscanf(sc->name, "%7s", socname) != 1) { 155 g_assert_not_reached(); 156 } 157 158 for (i = 0; i < sc->num_cpus; i++) { 159 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 160 aspeed_soc_cpu_type(sc)); 161 } 162 163 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 164 object_initialize_child(obj, "scu", &s->scu, typename); 165 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 166 sc->silicon_rev); 167 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 168 "hw-strap1"); 169 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 170 "hw-strap2"); 171 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 172 "hw-prot-key"); 173 174 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 175 176 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 177 178 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 179 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 180 181 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 182 object_initialize_child(obj, "adc", &s->adc, typename); 183 184 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 185 object_initialize_child(obj, "i2c", &s->i2c, typename); 186 187 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 188 189 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 190 object_initialize_child(obj, "fmc", &s->fmc, typename); 191 192 for (i = 0; i < sc->spis_num; i++) { 193 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 194 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 195 } 196 197 for (i = 0; i < sc->ehcis_num; i++) { 198 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 199 TYPE_PLATFORM_EHCI); 200 } 201 202 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 203 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 204 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 205 "ram-size"); 206 207 for (i = 0; i < sc->wdts_num; i++) { 208 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 209 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 210 } 211 212 for (i = 0; i < sc->macs_num; i++) { 213 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 214 TYPE_FTGMAC100); 215 } 216 217 for (i = 0; i < sc->uarts_num; i++) { 218 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 219 } 220 221 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 222 object_initialize_child(obj, "xdma", &s->xdma, typename); 223 224 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 225 object_initialize_child(obj, "gpio", &s->gpio, typename); 226 227 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 228 229 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 230 231 /* Init sd card slot class here so that they're under the correct parent */ 232 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 233 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 234 TYPE_SYSBUS_SDHCI); 235 } 236 237 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 238 239 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 240 object_initialize_child(obj, "hace", &s->hace, typename); 241 242 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 243 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 244 } 245 246 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 247 { 248 int i; 249 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 250 AspeedSoCState *s = ASPEED_SOC(dev); 251 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 252 g_autofree char *sram_name = NULL; 253 254 /* Default boot region (SPI memory or ROMs) */ 255 memory_region_init(&s->spi_boot_container, OBJECT(s), 256 "aspeed.spi_boot_container", 0x10000000); 257 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 258 &s->spi_boot_container); 259 260 /* IO space */ 261 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 262 sc->memmap[ASPEED_DEV_IOMEM], 263 ASPEED_SOC_IOMEM_SIZE); 264 265 /* Video engine stub */ 266 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 267 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 268 269 /* CPU */ 270 for (i = 0; i < sc->num_cpus; i++) { 271 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 272 OBJECT(s->memory), &error_abort); 273 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 274 return; 275 } 276 } 277 278 /* SRAM */ 279 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 280 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 281 errp)) { 282 return; 283 } 284 memory_region_add_subregion(s->memory, 285 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 286 287 /* SCU */ 288 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 289 return; 290 } 291 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 292 293 /* VIC */ 294 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 295 return; 296 } 297 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 298 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 299 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 301 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 302 303 /* RTC */ 304 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 305 return; 306 } 307 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 309 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 310 311 /* Timer */ 312 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 313 &error_abort); 314 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 315 return; 316 } 317 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 318 sc->memmap[ASPEED_DEV_TIMER1]); 319 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 320 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 321 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 322 } 323 324 /* ADC */ 325 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 326 return; 327 } 328 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 330 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 331 332 /* UART */ 333 if (!aspeed_soc_uart_realize(s, errp)) { 334 return; 335 } 336 337 /* I2C */ 338 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 339 &error_abort); 340 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 341 return; 342 } 343 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 345 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 346 347 /* PECI */ 348 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 349 return; 350 } 351 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 352 sc->memmap[ASPEED_DEV_PECI]); 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 354 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 355 356 /* FMC, The number of CS is set at the board level */ 357 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 358 &error_abort); 359 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 360 return; 361 } 362 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 363 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 364 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 365 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 366 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 367 368 /* Set up an alias on the FMC CE0 region (boot default) */ 369 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 370 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 371 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 372 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 373 374 /* SPI */ 375 for (i = 0; i < sc->spis_num; i++) { 376 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 377 return; 378 } 379 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 380 sc->memmap[ASPEED_DEV_SPI1 + i]); 381 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 382 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 383 } 384 385 /* EHCI */ 386 for (i = 0; i < sc->ehcis_num; i++) { 387 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 388 return; 389 } 390 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 391 sc->memmap[ASPEED_DEV_EHCI1 + i]); 392 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 393 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 394 } 395 396 /* SDMC - SDRAM Memory Controller */ 397 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 398 return; 399 } 400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 401 sc->memmap[ASPEED_DEV_SDMC]); 402 403 /* Watch dog */ 404 for (i = 0; i < sc->wdts_num; i++) { 405 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 406 hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; 407 408 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 409 &error_abort); 410 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 411 return; 412 } 413 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); 414 } 415 416 /* RAM */ 417 if (!aspeed_soc_dram_init(s, errp)) { 418 return; 419 } 420 421 /* Net */ 422 for (i = 0; i < sc->macs_num; i++) { 423 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 424 &error_abort); 425 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 426 return; 427 } 428 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 429 sc->memmap[ASPEED_DEV_ETH1 + i]); 430 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 431 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 432 } 433 434 /* XDMA */ 435 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 436 return; 437 } 438 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 439 sc->memmap[ASPEED_DEV_XDMA]); 440 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 441 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 442 443 /* GPIO */ 444 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 445 return; 446 } 447 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 448 sc->memmap[ASPEED_DEV_GPIO]); 449 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 450 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 451 452 /* SDHCI */ 453 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 454 return; 455 } 456 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 457 sc->memmap[ASPEED_DEV_SDHCI]); 458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 459 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 460 461 /* LPC */ 462 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 463 return; 464 } 465 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 466 467 /* Connect the LPC IRQ to the VIC */ 468 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 469 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 470 471 /* 472 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 473 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 474 * contrast, on the AST2600, the subdevice IRQs are connected straight to 475 * the GIC). 476 * 477 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 478 * to the VIC is at offset 0. 479 */ 480 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 481 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 482 483 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 484 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 485 486 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 487 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 488 489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 490 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 491 492 /* HACE */ 493 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 494 &error_abort); 495 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 496 return; 497 } 498 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 499 sc->memmap[ASPEED_DEV_HACE]); 500 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 501 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 502 } 503 504 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 505 { 506 static const char * const valid_cpu_types[] = { 507 ARM_CPU_TYPE_NAME("arm926"), 508 NULL 509 }; 510 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 511 DeviceClass *dc = DEVICE_CLASS(oc); 512 513 dc->realize = aspeed_ast2400_soc_realize; 514 /* Reason: Uses serial_hds and nd_table in realize() directly */ 515 dc->user_creatable = false; 516 517 sc->name = "ast2400-a1"; 518 sc->valid_cpu_types = valid_cpu_types; 519 sc->silicon_rev = AST2400_A1_SILICON_REV; 520 sc->sram_size = 0x8000; 521 sc->spis_num = 1; 522 sc->ehcis_num = 1; 523 sc->wdts_num = 2; 524 sc->macs_num = 2; 525 sc->uarts_num = 5; 526 sc->irqmap = aspeed_soc_ast2400_irqmap; 527 sc->memmap = aspeed_soc_ast2400_memmap; 528 sc->num_cpus = 1; 529 sc->get_irq = aspeed_soc_ast2400_get_irq; 530 } 531 532 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 533 { 534 static const char * const valid_cpu_types[] = { 535 ARM_CPU_TYPE_NAME("arm1176"), 536 NULL 537 }; 538 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 539 DeviceClass *dc = DEVICE_CLASS(oc); 540 541 dc->realize = aspeed_ast2400_soc_realize; 542 /* Reason: Uses serial_hds and nd_table in realize() directly */ 543 dc->user_creatable = false; 544 545 sc->name = "ast2500-a1"; 546 sc->valid_cpu_types = valid_cpu_types; 547 sc->silicon_rev = AST2500_A1_SILICON_REV; 548 sc->sram_size = 0x9000; 549 sc->spis_num = 2; 550 sc->ehcis_num = 2; 551 sc->wdts_num = 3; 552 sc->macs_num = 2; 553 sc->uarts_num = 5; 554 sc->irqmap = aspeed_soc_ast2500_irqmap; 555 sc->memmap = aspeed_soc_ast2500_memmap; 556 sc->num_cpus = 1; 557 sc->get_irq = aspeed_soc_ast2400_get_irq; 558 } 559 560 static const TypeInfo aspeed_soc_ast2400_types[] = { 561 { 562 .name = TYPE_ASPEED2400_SOC, 563 .parent = TYPE_ASPEED_SOC, 564 .instance_init = aspeed_ast2400_soc_init, 565 .instance_size = sizeof(Aspeed2400SoCState), 566 .abstract = true, 567 }, { 568 .name = "ast2400-a1", 569 .parent = TYPE_ASPEED2400_SOC, 570 .class_init = aspeed_soc_ast2400_class_init, 571 }, { 572 .name = "ast2500-a1", 573 .parent = TYPE_ASPEED2400_SOC, 574 .class_init = aspeed_soc_ast2500_class_init, 575 }, 576 }; 577 578 DEFINE_TYPES(aspeed_soc_ast2400_types) 579