1 /* 2 * ASPEED Ast10x0 SoC 3 * 4 * Copyright (C) 2022 ASPEED Technology Inc. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 * 9 * Implementation extracted from the AST2600 and adapted for Ast10x0. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "exec/address-spaces.h" 15 #include "sysemu/sysemu.h" 16 #include "hw/qdev-clock.h" 17 #include "hw/misc/unimp.h" 18 #include "hw/arm/aspeed_soc.h" 19 20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 21 22 static const hwaddr aspeed_soc_ast1030_memmap[] = { 23 [ASPEED_DEV_SRAM] = 0x00000000, 24 [ASPEED_DEV_SBC] = 0x79000000, 25 [ASPEED_DEV_IOMEM] = 0x7E600000, 26 [ASPEED_DEV_PWM] = 0x7E610000, 27 [ASPEED_DEV_FMC] = 0x7E620000, 28 [ASPEED_DEV_SPI1] = 0x7E630000, 29 [ASPEED_DEV_SPI2] = 0x7E640000, 30 [ASPEED_DEV_SCU] = 0x7E6E2000, 31 [ASPEED_DEV_ADC] = 0x7E6E9000, 32 [ASPEED_DEV_SBC] = 0x7E6F2000, 33 [ASPEED_DEV_GPIO] = 0x7E780000, 34 [ASPEED_DEV_TIMER1] = 0x7E782000, 35 [ASPEED_DEV_UART1] = 0x7E783000, 36 [ASPEED_DEV_UART2] = 0x7E78D000, 37 [ASPEED_DEV_UART3] = 0x7E78E000, 38 [ASPEED_DEV_UART4] = 0x7E78F000, 39 [ASPEED_DEV_UART5] = 0x7E784000, 40 [ASPEED_DEV_UART6] = 0x7E790000, 41 [ASPEED_DEV_UART7] = 0x7E790100, 42 [ASPEED_DEV_UART8] = 0x7E790200, 43 [ASPEED_DEV_UART9] = 0x7E790300, 44 [ASPEED_DEV_UART10] = 0x7E790400, 45 [ASPEED_DEV_UART11] = 0x7E790500, 46 [ASPEED_DEV_UART12] = 0x7E790600, 47 [ASPEED_DEV_UART13] = 0x7E790700, 48 [ASPEED_DEV_WDT] = 0x7E785000, 49 [ASPEED_DEV_LPC] = 0x7E789000, 50 [ASPEED_DEV_PECI] = 0x7E78B000, 51 [ASPEED_DEV_I2C] = 0x7E7B0000, 52 }; 53 54 static const int aspeed_soc_ast1030_irqmap[] = { 55 [ASPEED_DEV_UART1] = 47, 56 [ASPEED_DEV_UART2] = 48, 57 [ASPEED_DEV_UART3] = 49, 58 [ASPEED_DEV_UART4] = 50, 59 [ASPEED_DEV_UART5] = 8, 60 [ASPEED_DEV_UART6] = 57, 61 [ASPEED_DEV_UART7] = 58, 62 [ASPEED_DEV_UART8] = 59, 63 [ASPEED_DEV_UART9] = 60, 64 [ASPEED_DEV_UART10] = 61, 65 [ASPEED_DEV_UART11] = 62, 66 [ASPEED_DEV_UART12] = 63, 67 [ASPEED_DEV_UART13] = 64, 68 [ASPEED_DEV_GPIO] = 11, 69 [ASPEED_DEV_TIMER1] = 16, 70 [ASPEED_DEV_TIMER2] = 17, 71 [ASPEED_DEV_TIMER3] = 18, 72 [ASPEED_DEV_TIMER4] = 19, 73 [ASPEED_DEV_TIMER5] = 20, 74 [ASPEED_DEV_TIMER6] = 21, 75 [ASPEED_DEV_TIMER7] = 22, 76 [ASPEED_DEV_TIMER8] = 23, 77 [ASPEED_DEV_WDT] = 24, 78 [ASPEED_DEV_LPC] = 35, 79 [ASPEED_DEV_PECI] = 38, 80 [ASPEED_DEV_FMC] = 39, 81 [ASPEED_DEV_PWM] = 44, 82 [ASPEED_DEV_ADC] = 46, 83 [ASPEED_DEV_SPI1] = 65, 84 [ASPEED_DEV_SPI2] = 66, 85 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ 86 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ 87 }; 88 89 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) 90 { 91 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 92 93 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); 94 } 95 96 static void aspeed_soc_ast1030_init(Object *obj) 97 { 98 AspeedSoCState *s = ASPEED_SOC(obj); 99 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 100 char socname[8]; 101 char typename[64]; 102 int i; 103 104 if (sscanf(sc->name, "%7s", socname) != 1) { 105 g_assert_not_reached(); 106 } 107 108 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); 109 110 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); 111 112 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 113 object_initialize_child(obj, "scu", &s->scu, typename); 114 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); 115 116 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); 117 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); 118 119 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 120 object_initialize_child(obj, "i2c", &s->i2c, typename); 121 122 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 123 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 124 125 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 126 object_initialize_child(obj, "adc", &s->adc, typename); 127 128 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 129 object_initialize_child(obj, "fmc", &s->fmc, typename); 130 131 for (i = 0; i < sc->spis_num; i++) { 132 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 133 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 134 } 135 136 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 137 138 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 139 140 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); 141 142 for (i = 0; i < sc->wdts_num; i++) { 143 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 144 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 145 } 146 147 for (i = 0; i < sc->uarts_num; i++) { 148 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 149 } 150 151 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 152 object_initialize_child(obj, "gpio", &s->gpio, typename); 153 154 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 155 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, 156 TYPE_UNIMPLEMENTED_DEVICE); 157 } 158 159 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) 160 { 161 AspeedSoCState *s = ASPEED_SOC(dev_soc); 162 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 163 DeviceState *armv7m; 164 Error *err = NULL; 165 int i; 166 g_autofree char *sram_name = NULL; 167 168 if (!clock_has_source(s->sysclk)) { 169 error_setg(errp, "sysclk clock must be wired up by the board code"); 170 return; 171 } 172 173 /* General I/O memory space to catch all unimplemented device */ 174 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 175 sc->memmap[ASPEED_DEV_IOMEM], 176 ASPEED_SOC_IOMEM_SIZE); 177 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented), 178 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 179 0x40000); 180 181 /* AST1030 CPU Core */ 182 armv7m = DEVICE(&s->armv7m); 183 qdev_prop_set_uint32(armv7m, "num-irq", 256); 184 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); 185 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); 186 object_property_set_link(OBJECT(&s->armv7m), "memory", 187 OBJECT(s->memory), &error_abort); 188 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); 189 190 /* Internal SRAM */ 191 sram_name = g_strdup_printf("aspeed.sram.%d", 192 CPU(s->armv7m.cpu)->cpu_index); 193 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); 194 if (err != NULL) { 195 error_propagate(errp, err); 196 return; 197 } 198 memory_region_add_subregion(s->memory, 199 sc->memmap[ASPEED_DEV_SRAM], 200 &s->sram); 201 202 /* SCU */ 203 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 204 return; 205 } 206 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 207 208 /* I2C */ 209 210 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), 211 &error_abort); 212 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 213 return; 214 } 215 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 216 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { 217 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), 218 sc->irqmap[ASPEED_DEV_I2C] + i); 219 /* The AST1030 I2C controller has one IRQ per bus. */ 220 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); 221 } 222 223 /* PECI */ 224 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 225 return; 226 } 227 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 228 sc->memmap[ASPEED_DEV_PECI]); 229 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 230 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 231 232 /* LPC */ 233 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 234 return; 235 } 236 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 237 238 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ 239 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 240 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 241 242 /* 243 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. 244 */ 245 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 246 qdev_get_gpio_in(DEVICE(&s->armv7m), 247 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); 248 249 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 250 qdev_get_gpio_in(DEVICE(&s->armv7m), 251 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); 252 253 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 254 qdev_get_gpio_in(DEVICE(&s->armv7m), 255 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); 256 257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 258 qdev_get_gpio_in(DEVICE(&s->armv7m), 259 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); 260 261 /* UART */ 262 if (!aspeed_soc_uart_realize(s, errp)) { 263 return; 264 } 265 266 /* Timer */ 267 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 268 &error_abort); 269 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 270 return; 271 } 272 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 273 sc->memmap[ASPEED_DEV_TIMER1]); 274 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 275 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 277 } 278 279 /* ADC */ 280 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 281 return; 282 } 283 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 285 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 286 287 /* FMC, The number of CS is set at the board level */ 288 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), 289 &error_abort); 290 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 291 return; 292 } 293 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 294 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 295 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 296 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 297 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 298 299 /* SPI */ 300 for (i = 0; i < sc->spis_num; i++) { 301 object_property_set_link(OBJECT(&s->spi[i]), "dram", 302 OBJECT(&s->sram), &error_abort); 303 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 304 return; 305 } 306 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 307 sc->memmap[ASPEED_DEV_SPI1 + i]); 308 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 309 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 310 } 311 312 /* Secure Boot Controller */ 313 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { 314 return; 315 } 316 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); 317 318 /* Watch dog */ 319 for (i = 0; i < sc->wdts_num; i++) { 320 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 321 322 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 323 &error_abort); 324 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 325 return; 326 } 327 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 328 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); 329 } 330 331 /* GPIO */ 332 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 333 return; 334 } 335 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 336 sc->memmap[ASPEED_DEV_GPIO]); 337 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 338 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 339 } 340 341 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) 342 { 343 DeviceClass *dc = DEVICE_CLASS(klass); 344 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); 345 346 dc->realize = aspeed_soc_ast1030_realize; 347 348 sc->name = "ast1030-a1"; 349 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); 350 sc->silicon_rev = AST1030_A1_SILICON_REV; 351 sc->sram_size = 0xc0000; 352 sc->spis_num = 2; 353 sc->ehcis_num = 0; 354 sc->wdts_num = 4; 355 sc->macs_num = 1; 356 sc->uarts_num = 13; 357 sc->irqmap = aspeed_soc_ast1030_irqmap; 358 sc->memmap = aspeed_soc_ast1030_memmap; 359 sc->num_cpus = 1; 360 sc->get_irq = aspeed_soc_ast1030_get_irq; 361 } 362 363 static const TypeInfo aspeed_soc_ast1030_type_info = { 364 .name = "ast1030-a1", 365 .parent = TYPE_ASPEED_SOC, 366 .instance_size = sizeof(AspeedSoCState), 367 .instance_init = aspeed_soc_ast1030_init, 368 .class_init = aspeed_soc_ast1030_class_init, 369 .class_size = sizeof(AspeedSoCClass), 370 }; 371 372 static void aspeed_soc_register_types(void) 373 { 374 type_register_static(&aspeed_soc_ast1030_type_info); 375 } 376 377 type_init(aspeed_soc_register_types) 378