1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/misc/led.h" 24 #include "hw/qdev-properties.h" 25 #include "qemu/log.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 32 static struct arm_boot_info aspeed_board_binfo = { 33 .board_id = -1, /* device-tree-only board */ 34 }; 35 36 struct AspeedMachineState { 37 /* Private */ 38 MachineState parent_obj; 39 /* Public */ 40 41 AspeedSoCState soc; 42 MemoryRegion ram_container; 43 MemoryRegion max_ram; 44 bool mmio_exec; 45 char *fmc_model; 46 char *spi_model; 47 }; 48 49 /* Palmetto hardware value: 0x120CE416 */ 50 #define PALMETTO_BMC_HW_STRAP1 ( \ 51 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 52 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 53 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 54 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 55 SCU_HW_STRAP_VGA_CLASS_CODE | \ 56 SCU_HW_STRAP_LPC_RESET_PIN | \ 57 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 58 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 59 SCU_HW_STRAP_SPI_WIDTH | \ 60 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 61 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 62 63 /* TODO: Find the actual hardware value */ 64 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 65 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 66 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 67 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 68 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 69 SCU_HW_STRAP_VGA_CLASS_CODE | \ 70 SCU_HW_STRAP_LPC_RESET_PIN | \ 71 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 72 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 73 SCU_HW_STRAP_SPI_WIDTH | \ 74 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 75 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 76 77 /* AST2500 evb hardware value: 0xF100C2E6 */ 78 #define AST2500_EVB_HW_STRAP1 (( \ 79 AST2500_HW_STRAP1_DEFAULTS | \ 80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 82 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 84 SCU_HW_STRAP_MAC1_RGMII | \ 85 SCU_HW_STRAP_MAC0_RGMII) & \ 86 ~SCU_HW_STRAP_2ND_BOOT_WDT) 87 88 /* Romulus hardware value: 0xF10AD206 */ 89 #define ROMULUS_BMC_HW_STRAP1 ( \ 90 AST2500_HW_STRAP1_DEFAULTS | \ 91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 93 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 95 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 96 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 97 98 /* Sonorapass hardware value: 0xF100D216 */ 99 #define SONORAPASS_BMC_HW_STRAP1 ( \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_RESERVED28 | \ 104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 105 SCU_HW_STRAP_VGA_CLASS_CODE | \ 106 SCU_HW_STRAP_LPC_RESET_PIN | \ 107 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 108 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 109 SCU_HW_STRAP_VGA_BIOS_ROM | \ 110 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 111 SCU_AST2500_HW_STRAP_RESERVED1) 112 113 /* Swift hardware value: 0xF11AD206 */ 114 #define SWIFT_BMC_HW_STRAP1 ( \ 115 AST2500_HW_STRAP1_DEFAULTS | \ 116 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 117 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 118 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 119 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 120 SCU_H_PLL_BYPASS_EN | \ 121 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 122 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 123 124 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 125 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 126 127 /* AST2600 evb hardware value */ 128 #define AST2600_EVB_HW_STRAP1 0x000000C0 129 #define AST2600_EVB_HW_STRAP2 0x00000003 130 131 /* Tacoma hardware value */ 132 #define TACOMA_BMC_HW_STRAP1 0x00000000 133 #define TACOMA_BMC_HW_STRAP2 0x00000040 134 135 /* 136 * The max ram region is for firmwares that scan the address space 137 * with load/store to guess how much RAM the SoC has. 138 */ 139 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 140 { 141 return 0; 142 } 143 144 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 145 unsigned size) 146 { 147 /* Discard writes */ 148 } 149 150 static const MemoryRegionOps max_ram_ops = { 151 .read = max_ram_read, 152 .write = max_ram_write, 153 .endianness = DEVICE_NATIVE_ENDIAN, 154 }; 155 156 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 157 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 158 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 159 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 160 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 161 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 162 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 163 164 static void aspeed_write_smpboot(ARMCPU *cpu, 165 const struct arm_boot_info *info) 166 { 167 static const uint32_t poll_mailbox_ready[] = { 168 /* 169 * r2 = per-cpu go sign value 170 * r1 = AST_SMP_MBOX_FIELD_ENTRY 171 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 172 */ 173 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 174 0xe21000ff, /* ands r0, r0, #255 */ 175 0xe59f201c, /* ldr r2, [pc, #28] */ 176 0xe1822000, /* orr r2, r2, r0 */ 177 178 0xe59f1018, /* ldr r1, [pc, #24] */ 179 0xe59f0018, /* ldr r0, [pc, #24] */ 180 181 0xe320f002, /* wfe */ 182 0xe5904000, /* ldr r4, [r0] */ 183 0xe1520004, /* cmp r2, r4 */ 184 0x1afffffb, /* bne <wfe> */ 185 0xe591f000, /* ldr pc, [r1] */ 186 AST_SMP_MBOX_GOSIGN, 187 AST_SMP_MBOX_FIELD_ENTRY, 188 AST_SMP_MBOX_FIELD_GOSIGN, 189 }; 190 191 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 192 sizeof(poll_mailbox_ready), 193 info->smp_loader_start); 194 } 195 196 static void aspeed_reset_secondary(ARMCPU *cpu, 197 const struct arm_boot_info *info) 198 { 199 AddressSpace *as = arm_boot_address_space(cpu, info); 200 CPUState *cs = CPU(cpu); 201 202 /* info->smp_bootreg_addr */ 203 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 204 MEMTXATTRS_UNSPECIFIED, NULL); 205 cpu_set_pc(cs, info->smp_loader_start); 206 } 207 208 #define FIRMWARE_ADDR 0x0 209 210 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 211 Error **errp) 212 { 213 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 214 uint8_t *storage; 215 int64_t size; 216 217 /* The block backend size should have already been 'validated' by 218 * the creation of the m25p80 object. 219 */ 220 size = blk_getlength(blk); 221 if (size <= 0) { 222 error_setg(errp, "failed to get flash size"); 223 return; 224 } 225 226 if (rom_size > size) { 227 rom_size = size; 228 } 229 230 storage = g_new0(uint8_t, rom_size); 231 if (blk_pread(blk, 0, storage, rom_size) < 0) { 232 error_setg(errp, "failed to read the initial flash content"); 233 return; 234 } 235 236 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 237 g_free(storage); 238 } 239 240 static void aspeed_board_init_flashes(AspeedSMCState *s, 241 const char *flashtype) 242 { 243 int i ; 244 245 for (i = 0; i < s->num_cs; ++i) { 246 AspeedSMCFlash *fl = &s->flashes[i]; 247 DriveInfo *dinfo = drive_get_next(IF_MTD); 248 qemu_irq cs_line; 249 250 fl->flash = qdev_new(flashtype); 251 if (dinfo) { 252 qdev_prop_set_drive(fl->flash, "drive", 253 blk_by_legacy_dinfo(dinfo)); 254 } 255 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 256 257 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 258 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 259 } 260 } 261 262 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 263 { 264 DeviceState *card; 265 266 if (!dinfo) { 267 return; 268 } 269 card = qdev_new(TYPE_SD_CARD); 270 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 271 &error_fatal); 272 qdev_realize_and_unref(card, 273 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 274 &error_fatal); 275 } 276 277 static void aspeed_machine_init(MachineState *machine) 278 { 279 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 280 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 281 AspeedSoCClass *sc; 282 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 283 ram_addr_t max_ram_size; 284 int i; 285 NICInfo *nd = &nd_table[0]; 286 287 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 288 4 * GiB); 289 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 290 291 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 292 293 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 294 295 /* 296 * This will error out if isize is not supported by memory controller. 297 */ 298 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size, 299 &error_fatal); 300 301 for (i = 0; i < sc->macs_num; i++) { 302 if ((amc->macs_mask & (1 << i)) && nd->used) { 303 qemu_check_nic_model(nd, TYPE_FTGMAC100); 304 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 305 nd++; 306 } 307 } 308 309 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 310 &error_abort); 311 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 312 &error_abort); 313 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 314 &error_abort); 315 object_property_set_link(OBJECT(&bmc->soc), "dram", 316 OBJECT(&bmc->ram_container), &error_abort); 317 if (machine->kernel_filename) { 318 /* 319 * When booting with a -kernel command line there is no u-boot 320 * that runs to unlock the SCU. In this case set the default to 321 * be unlocked as the kernel expects 322 */ 323 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 324 ASPEED_SCU_PROT_KEY, &error_abort); 325 } 326 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 327 328 memory_region_add_subregion(get_system_memory(), 329 sc->memmap[ASPEED_DEV_SDRAM], 330 &bmc->ram_container); 331 332 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 333 &error_abort); 334 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 335 "max_ram", max_ram_size - ram_size); 336 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 337 338 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 339 bmc->fmc_model : amc->fmc_model); 340 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 341 bmc->spi_model : amc->spi_model); 342 343 /* Install first FMC flash content as a boot rom. */ 344 if (drive0) { 345 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 346 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 347 348 /* 349 * create a ROM region using the default mapping window size of 350 * the flash module. The window size is 64MB for the AST2400 351 * SoC and 128MB for the AST2500 SoC, which is twice as big as 352 * needed by the flash modules of the Aspeed machines. 353 */ 354 if (ASPEED_MACHINE(machine)->mmio_exec) { 355 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 356 &fl->mmio, 0, fl->size); 357 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 358 boot_rom); 359 } else { 360 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 361 fl->size, &error_abort); 362 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 363 boot_rom); 364 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 365 } 366 } 367 368 if (machine->kernel_filename && sc->num_cpus > 1) { 369 /* With no u-boot we must set up a boot stub for the secondary CPU */ 370 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 371 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 372 0x80, &error_abort); 373 memory_region_add_subregion(get_system_memory(), 374 AST_SMP_MAILBOX_BASE, smpboot); 375 376 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 377 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 378 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 379 } 380 381 aspeed_board_binfo.ram_size = ram_size; 382 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 383 aspeed_board_binfo.nb_cpus = sc->num_cpus; 384 385 if (amc->i2c_init) { 386 amc->i2c_init(bmc); 387 } 388 389 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 390 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 391 } 392 393 if (bmc->soc.emmc.num_slots) { 394 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 395 } 396 397 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 398 } 399 400 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 401 { 402 AspeedSoCState *soc = &bmc->soc; 403 DeviceState *dev; 404 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 405 406 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 407 * enough to provide basic RTC features. Alarms will be missing */ 408 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 409 410 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 411 eeprom_buf); 412 413 /* add a TMP423 temperature sensor */ 414 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 415 "tmp423", 0x4c)); 416 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 417 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 418 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 419 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 420 } 421 422 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 423 { 424 AspeedSoCState *soc = &bmc->soc; 425 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 426 427 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 428 eeprom_buf); 429 430 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 431 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 432 TYPE_TMP105, 0x4d); 433 434 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 435 * plugged on the I2C bus header */ 436 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 437 } 438 439 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 440 { 441 /* Start with some devices on our I2C busses */ 442 ast2500_evb_i2c_init(bmc); 443 } 444 445 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 446 { 447 AspeedSoCState *soc = &bmc->soc; 448 449 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 450 * good enough */ 451 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 452 } 453 454 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 455 { 456 AspeedSoCState *soc = &bmc->soc; 457 458 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 459 460 /* The swift board expects a TMP275 but a TMP105 is compatible */ 461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 462 /* The swift board expects a pca9551 but a pca9552 is compatible */ 463 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 464 465 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 466 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 467 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 468 469 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 470 /* The swift board expects a pca9539 but a pca9552 is compatible */ 471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 472 473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 474 /* The swift board expects a pca9539 but a pca9552 is compatible */ 475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 476 0x74); 477 478 /* The swift board expects a TMP275 but a TMP105 is compatible */ 479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 481 } 482 483 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 484 { 485 AspeedSoCState *soc = &bmc->soc; 486 487 /* bus 2 : */ 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 490 /* bus 2 : pca9546 @ 0x73 */ 491 492 /* bus 3 : pca9548 @ 0x70 */ 493 494 /* bus 4 : */ 495 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 496 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 497 eeprom4_54); 498 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 500 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 502 503 /* bus 6 : */ 504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 506 /* bus 6 : pca9546 @ 0x73 */ 507 508 /* bus 8 : */ 509 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 510 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 511 eeprom8_56); 512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 513 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 514 /* bus 8 : adc128d818 @ 0x1d */ 515 /* bus 8 : adc128d818 @ 0x1f */ 516 517 /* 518 * bus 13 : pca9548 @ 0x71 519 * - channel 3: 520 * - tmm421 @ 0x4c 521 * - tmp421 @ 0x4e 522 * - tmp421 @ 0x4f 523 */ 524 525 } 526 527 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 528 { 529 static const struct { 530 unsigned gpio_id; 531 LEDColor color; 532 const char *description; 533 bool gpio_polarity; 534 } pca1_leds[] = { 535 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 536 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 537 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 538 }; 539 AspeedSoCState *soc = &bmc->soc; 540 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 541 DeviceState *dev; 542 LEDState *led; 543 544 /* Bus 3: TODO bmp280@77 */ 545 /* Bus 3: TODO max31785@52 */ 546 /* Bus 3: TODO dps310@76 */ 547 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 548 qdev_prop_set_string(dev, "description", "pca1"); 549 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 550 aspeed_i2c_get_bus(&soc->i2c, 3), 551 &error_fatal); 552 553 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 554 led = led_create_simple(OBJECT(bmc), 555 pca1_leds[i].gpio_polarity, 556 pca1_leds[i].color, 557 pca1_leds[i].description); 558 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 559 qdev_get_gpio_in(DEVICE(led), 0)); 560 } 561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 563 564 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 566 0x4a); 567 568 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 569 * good enough */ 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 571 572 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 573 eeprom_buf); 574 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 575 qdev_prop_set_string(dev, "description", "pca0"); 576 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 577 aspeed_i2c_get_bus(&soc->i2c, 11), 578 &error_fatal); 579 /* Bus 11: TODO ucd90160@64 */ 580 } 581 582 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 583 { 584 return ASPEED_MACHINE(obj)->mmio_exec; 585 } 586 587 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 588 { 589 ASPEED_MACHINE(obj)->mmio_exec = value; 590 } 591 592 static void aspeed_machine_instance_init(Object *obj) 593 { 594 ASPEED_MACHINE(obj)->mmio_exec = false; 595 } 596 597 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 598 { 599 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 600 return g_strdup(bmc->fmc_model); 601 } 602 603 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 604 { 605 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 606 607 g_free(bmc->fmc_model); 608 bmc->fmc_model = g_strdup(value); 609 } 610 611 static char *aspeed_get_spi_model(Object *obj, Error **errp) 612 { 613 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 614 return g_strdup(bmc->spi_model); 615 } 616 617 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 618 { 619 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 620 621 g_free(bmc->spi_model); 622 bmc->spi_model = g_strdup(value); 623 } 624 625 static void aspeed_machine_class_props_init(ObjectClass *oc) 626 { 627 object_class_property_add_bool(oc, "execute-in-place", 628 aspeed_get_mmio_exec, 629 aspeed_set_mmio_exec); 630 object_class_property_set_description(oc, "execute-in-place", 631 "boot directly from CE0 flash device"); 632 633 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 634 aspeed_set_fmc_model); 635 object_class_property_set_description(oc, "fmc-model", 636 "Change the FMC Flash model"); 637 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 638 aspeed_set_spi_model); 639 object_class_property_set_description(oc, "spi-model", 640 "Change the SPI Flash model"); 641 } 642 643 static int aspeed_soc_num_cpus(const char *soc_name) 644 { 645 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 646 return sc->num_cpus; 647 } 648 649 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 650 { 651 MachineClass *mc = MACHINE_CLASS(oc); 652 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 653 654 mc->init = aspeed_machine_init; 655 mc->no_floppy = 1; 656 mc->no_cdrom = 1; 657 mc->no_parallel = 1; 658 mc->default_ram_id = "ram"; 659 amc->macs_mask = ASPEED_MAC0_ON; 660 661 aspeed_machine_class_props_init(oc); 662 } 663 664 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 665 { 666 MachineClass *mc = MACHINE_CLASS(oc); 667 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 668 669 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 670 amc->soc_name = "ast2400-a1"; 671 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 672 amc->fmc_model = "n25q256a"; 673 amc->spi_model = "mx25l25635e"; 674 amc->num_cs = 1; 675 amc->i2c_init = palmetto_bmc_i2c_init; 676 mc->default_ram_size = 256 * MiB; 677 mc->default_cpus = mc->min_cpus = mc->max_cpus = 678 aspeed_soc_num_cpus(amc->soc_name); 679 }; 680 681 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 682 void *data) 683 { 684 MachineClass *mc = MACHINE_CLASS(oc); 685 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 686 687 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 688 amc->soc_name = "ast2400-a1"; 689 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 690 amc->fmc_model = "mx25l25635e"; 691 amc->spi_model = "mx25l25635e"; 692 amc->num_cs = 1; 693 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 694 amc->i2c_init = palmetto_bmc_i2c_init; 695 mc->default_ram_size = 256 * MiB; 696 } 697 698 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 699 { 700 MachineClass *mc = MACHINE_CLASS(oc); 701 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 702 703 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 704 amc->soc_name = "ast2500-a1"; 705 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 706 amc->fmc_model = "w25q256"; 707 amc->spi_model = "mx25l25635e"; 708 amc->num_cs = 1; 709 amc->i2c_init = ast2500_evb_i2c_init; 710 mc->default_ram_size = 512 * MiB; 711 mc->default_cpus = mc->min_cpus = mc->max_cpus = 712 aspeed_soc_num_cpus(amc->soc_name); 713 }; 714 715 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 716 { 717 MachineClass *mc = MACHINE_CLASS(oc); 718 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 719 720 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 721 amc->soc_name = "ast2500-a1"; 722 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 723 amc->fmc_model = "n25q256a"; 724 amc->spi_model = "mx66l1g45g"; 725 amc->num_cs = 2; 726 amc->i2c_init = romulus_bmc_i2c_init; 727 mc->default_ram_size = 512 * MiB; 728 mc->default_cpus = mc->min_cpus = mc->max_cpus = 729 aspeed_soc_num_cpus(amc->soc_name); 730 }; 731 732 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 733 { 734 MachineClass *mc = MACHINE_CLASS(oc); 735 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 736 737 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 738 amc->soc_name = "ast2500-a1"; 739 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 740 amc->fmc_model = "mx66l1g45g"; 741 amc->spi_model = "mx66l1g45g"; 742 amc->num_cs = 2; 743 amc->i2c_init = sonorapass_bmc_i2c_init; 744 mc->default_ram_size = 512 * MiB; 745 mc->default_cpus = mc->min_cpus = mc->max_cpus = 746 aspeed_soc_num_cpus(amc->soc_name); 747 }; 748 749 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 750 { 751 MachineClass *mc = MACHINE_CLASS(oc); 752 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 753 754 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 755 amc->soc_name = "ast2500-a1"; 756 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 757 amc->fmc_model = "mx66l1g45g"; 758 amc->spi_model = "mx66l1g45g"; 759 amc->num_cs = 2; 760 amc->i2c_init = swift_bmc_i2c_init; 761 mc->default_ram_size = 512 * MiB; 762 mc->default_cpus = mc->min_cpus = mc->max_cpus = 763 aspeed_soc_num_cpus(amc->soc_name); 764 }; 765 766 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 767 { 768 MachineClass *mc = MACHINE_CLASS(oc); 769 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 770 771 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 772 amc->soc_name = "ast2500-a1"; 773 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 774 amc->fmc_model = "mx25l25635e"; 775 amc->spi_model = "mx66l1g45g"; 776 amc->num_cs = 2; 777 amc->i2c_init = witherspoon_bmc_i2c_init; 778 mc->default_ram_size = 512 * MiB; 779 mc->default_cpus = mc->min_cpus = mc->max_cpus = 780 aspeed_soc_num_cpus(amc->soc_name); 781 }; 782 783 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 784 { 785 MachineClass *mc = MACHINE_CLASS(oc); 786 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 787 788 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 789 amc->soc_name = "ast2600-a1"; 790 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 791 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 792 amc->fmc_model = "w25q512jv"; 793 amc->spi_model = "mx66u51235f"; 794 amc->num_cs = 1; 795 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 796 amc->i2c_init = ast2600_evb_i2c_init; 797 mc->default_ram_size = 1 * GiB; 798 mc->default_cpus = mc->min_cpus = mc->max_cpus = 799 aspeed_soc_num_cpus(amc->soc_name); 800 }; 801 802 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 803 { 804 MachineClass *mc = MACHINE_CLASS(oc); 805 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 806 807 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 808 amc->soc_name = "ast2600-a1"; 809 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 810 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 811 amc->fmc_model = "mx66l1g45g"; 812 amc->spi_model = "mx66l1g45g"; 813 amc->num_cs = 2; 814 amc->macs_mask = ASPEED_MAC2_ON; 815 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 816 mc->default_ram_size = 1 * GiB; 817 mc->default_cpus = mc->min_cpus = mc->max_cpus = 818 aspeed_soc_num_cpus(amc->soc_name); 819 }; 820 821 static const TypeInfo aspeed_machine_types[] = { 822 { 823 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 824 .parent = TYPE_ASPEED_MACHINE, 825 .class_init = aspeed_machine_palmetto_class_init, 826 }, { 827 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 828 .parent = TYPE_ASPEED_MACHINE, 829 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 830 }, { 831 .name = MACHINE_TYPE_NAME("ast2500-evb"), 832 .parent = TYPE_ASPEED_MACHINE, 833 .class_init = aspeed_machine_ast2500_evb_class_init, 834 }, { 835 .name = MACHINE_TYPE_NAME("romulus-bmc"), 836 .parent = TYPE_ASPEED_MACHINE, 837 .class_init = aspeed_machine_romulus_class_init, 838 }, { 839 .name = MACHINE_TYPE_NAME("swift-bmc"), 840 .parent = TYPE_ASPEED_MACHINE, 841 .class_init = aspeed_machine_swift_class_init, 842 }, { 843 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 844 .parent = TYPE_ASPEED_MACHINE, 845 .class_init = aspeed_machine_sonorapass_class_init, 846 }, { 847 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 848 .parent = TYPE_ASPEED_MACHINE, 849 .class_init = aspeed_machine_witherspoon_class_init, 850 }, { 851 .name = MACHINE_TYPE_NAME("ast2600-evb"), 852 .parent = TYPE_ASPEED_MACHINE, 853 .class_init = aspeed_machine_ast2600_evb_class_init, 854 }, { 855 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 856 .parent = TYPE_ASPEED_MACHINE, 857 .class_init = aspeed_machine_tacoma_class_init, 858 }, { 859 .name = TYPE_ASPEED_MACHINE, 860 .parent = TYPE_MACHINE, 861 .instance_size = sizeof(AspeedMachineState), 862 .instance_init = aspeed_machine_instance_init, 863 .class_size = sizeof(AspeedMachineClass), 864 .class_init = aspeed_machine_class_init, 865 .abstract = true, 866 } 867 }; 868 869 DEFINE_TYPES(aspeed_machine_types) 870