1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "qemu/error-report.h" 26 #include "qemu/units.h" 27 28 static struct arm_boot_info aspeed_board_binfo = { 29 .board_id = -1, /* device-tree-only board */ 30 }; 31 32 struct AspeedMachineState { 33 /* Private */ 34 MachineState parent_obj; 35 /* Public */ 36 37 AspeedSoCState soc; 38 MemoryRegion ram_container; 39 MemoryRegion max_ram; 40 bool mmio_exec; 41 char *fmc_model; 42 char *spi_model; 43 }; 44 45 /* Palmetto hardware value: 0x120CE416 */ 46 #define PALMETTO_BMC_HW_STRAP1 ( \ 47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 49 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 51 SCU_HW_STRAP_VGA_CLASS_CODE | \ 52 SCU_HW_STRAP_LPC_RESET_PIN | \ 53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 55 SCU_HW_STRAP_SPI_WIDTH | \ 56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 58 59 /* TODO: Find the actual hardware value */ 60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* AST2500 evb hardware value: 0xF100C2E6 */ 74 #define AST2500_EVB_HW_STRAP1 (( \ 75 AST2500_HW_STRAP1_DEFAULTS | \ 76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 78 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 80 SCU_HW_STRAP_MAC1_RGMII | \ 81 SCU_HW_STRAP_MAC0_RGMII) & \ 82 ~SCU_HW_STRAP_2ND_BOOT_WDT) 83 84 /* Romulus hardware value: 0xF10AD206 */ 85 #define ROMULUS_BMC_HW_STRAP1 ( \ 86 AST2500_HW_STRAP1_DEFAULTS | \ 87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 89 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 93 94 /* Sonorapass hardware value: 0xF100D216 */ 95 #define SONORAPASS_BMC_HW_STRAP1 ( \ 96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 98 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 99 SCU_AST2500_HW_STRAP_RESERVED28 | \ 100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 101 SCU_HW_STRAP_VGA_CLASS_CODE | \ 102 SCU_HW_STRAP_LPC_RESET_PIN | \ 103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 105 SCU_HW_STRAP_VGA_BIOS_ROM | \ 106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 107 SCU_AST2500_HW_STRAP_RESERVED1) 108 109 /* Swift hardware value: 0xF11AD206 */ 110 #define SWIFT_BMC_HW_STRAP1 ( \ 111 AST2500_HW_STRAP1_DEFAULTS | \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_H_PLL_BYPASS_EN | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 #define G220A_BMC_HW_STRAP1 ( \ 121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 123 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 124 SCU_AST2500_HW_STRAP_RESERVED28 | \ 125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 126 SCU_HW_STRAP_2ND_BOOT_WDT | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 132 SCU_AST2500_HW_STRAP_RESERVED1) 133 134 /* FP5280G2 hardware value: 0XF100D286 */ 135 #define FP5280G2_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_VGA_CLASS_CODE | \ 142 SCU_HW_STRAP_LPC_RESET_PIN | \ 143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 144 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 145 SCU_HW_STRAP_MAC1_RGMII | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 150 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 151 152 /* Quanta-Q71l hardware value */ 153 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 154 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 155 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 156 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 157 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 158 SCU_HW_STRAP_VGA_CLASS_CODE | \ 159 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 160 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 161 SCU_HW_STRAP_SPI_WIDTH | \ 162 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 163 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 164 165 /* AST2600 evb hardware value */ 166 #define AST2600_EVB_HW_STRAP1 0x000000C0 167 #define AST2600_EVB_HW_STRAP2 0x00000003 168 169 /* Tacoma hardware value */ 170 #define TACOMA_BMC_HW_STRAP1 0x00000000 171 #define TACOMA_BMC_HW_STRAP2 0x00000040 172 173 /* Rainier hardware value: (QEMU prototype) */ 174 #define RAINIER_BMC_HW_STRAP1 0x00000000 175 #define RAINIER_BMC_HW_STRAP2 0x00000000 176 177 /* Fuji hardware value */ 178 #define FUJI_BMC_HW_STRAP1 0x00000000 179 #define FUJI_BMC_HW_STRAP2 0x00000000 180 181 /* 182 * The max ram region is for firmwares that scan the address space 183 * with load/store to guess how much RAM the SoC has. 184 */ 185 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 186 { 187 return 0; 188 } 189 190 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 191 unsigned size) 192 { 193 /* Discard writes */ 194 } 195 196 static const MemoryRegionOps max_ram_ops = { 197 .read = max_ram_read, 198 .write = max_ram_write, 199 .endianness = DEVICE_NATIVE_ENDIAN, 200 }; 201 202 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 203 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 204 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 205 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 206 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 207 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 208 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 209 210 static void aspeed_write_smpboot(ARMCPU *cpu, 211 const struct arm_boot_info *info) 212 { 213 static const uint32_t poll_mailbox_ready[] = { 214 /* 215 * r2 = per-cpu go sign value 216 * r1 = AST_SMP_MBOX_FIELD_ENTRY 217 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 218 */ 219 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 220 0xe21000ff, /* ands r0, r0, #255 */ 221 0xe59f201c, /* ldr r2, [pc, #28] */ 222 0xe1822000, /* orr r2, r2, r0 */ 223 224 0xe59f1018, /* ldr r1, [pc, #24] */ 225 0xe59f0018, /* ldr r0, [pc, #24] */ 226 227 0xe320f002, /* wfe */ 228 0xe5904000, /* ldr r4, [r0] */ 229 0xe1520004, /* cmp r2, r4 */ 230 0x1afffffb, /* bne <wfe> */ 231 0xe591f000, /* ldr pc, [r1] */ 232 AST_SMP_MBOX_GOSIGN, 233 AST_SMP_MBOX_FIELD_ENTRY, 234 AST_SMP_MBOX_FIELD_GOSIGN, 235 }; 236 237 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 238 sizeof(poll_mailbox_ready), 239 info->smp_loader_start); 240 } 241 242 static void aspeed_reset_secondary(ARMCPU *cpu, 243 const struct arm_boot_info *info) 244 { 245 AddressSpace *as = arm_boot_address_space(cpu, info); 246 CPUState *cs = CPU(cpu); 247 248 /* info->smp_bootreg_addr */ 249 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 250 MEMTXATTRS_UNSPECIFIED, NULL); 251 cpu_set_pc(cs, info->smp_loader_start); 252 } 253 254 #define FIRMWARE_ADDR 0x0 255 256 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 257 Error **errp) 258 { 259 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 260 uint8_t *storage; 261 int64_t size; 262 263 /* The block backend size should have already been 'validated' by 264 * the creation of the m25p80 object. 265 */ 266 size = blk_getlength(blk); 267 if (size <= 0) { 268 error_setg(errp, "failed to get flash size"); 269 return; 270 } 271 272 if (rom_size > size) { 273 rom_size = size; 274 } 275 276 storage = g_new0(uint8_t, rom_size); 277 if (blk_pread(blk, 0, storage, rom_size) < 0) { 278 error_setg(errp, "failed to read the initial flash content"); 279 return; 280 } 281 282 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 283 g_free(storage); 284 } 285 286 static void aspeed_board_init_flashes(AspeedSMCState *s, 287 const char *flashtype) 288 { 289 int i ; 290 291 for (i = 0; i < s->num_cs; ++i) { 292 DriveInfo *dinfo = drive_get_next(IF_MTD); 293 qemu_irq cs_line; 294 DeviceState *dev; 295 296 dev = qdev_new(flashtype); 297 if (dinfo) { 298 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 299 } 300 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 301 302 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 303 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 304 } 305 } 306 307 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 308 { 309 DeviceState *card; 310 311 if (!dinfo) { 312 return; 313 } 314 card = qdev_new(TYPE_SD_CARD); 315 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 316 &error_fatal); 317 qdev_realize_and_unref(card, 318 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 319 &error_fatal); 320 } 321 322 static void aspeed_machine_init(MachineState *machine) 323 { 324 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 325 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 326 AspeedSoCClass *sc; 327 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 328 ram_addr_t max_ram_size; 329 int i; 330 NICInfo *nd = &nd_table[0]; 331 332 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 333 4 * GiB); 334 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 335 336 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 337 338 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 339 340 /* 341 * This will error out if isize is not supported by memory controller. 342 */ 343 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 344 &error_fatal); 345 346 for (i = 0; i < sc->macs_num; i++) { 347 if ((amc->macs_mask & (1 << i)) && nd->used) { 348 qemu_check_nic_model(nd, TYPE_FTGMAC100); 349 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 350 nd++; 351 } 352 } 353 354 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 355 &error_abort); 356 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 357 &error_abort); 358 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 359 &error_abort); 360 object_property_set_link(OBJECT(&bmc->soc), "dram", 361 OBJECT(machine->ram), &error_abort); 362 if (machine->kernel_filename) { 363 /* 364 * When booting with a -kernel command line there is no u-boot 365 * that runs to unlock the SCU. In this case set the default to 366 * be unlocked as the kernel expects 367 */ 368 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 369 ASPEED_SCU_PROT_KEY, &error_abort); 370 } 371 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 372 amc->uart_default); 373 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 374 375 memory_region_add_subregion(get_system_memory(), 376 sc->memmap[ASPEED_DEV_SDRAM], 377 &bmc->ram_container); 378 379 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 380 &error_abort); 381 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 382 "max_ram", max_ram_size - machine->ram_size); 383 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 384 385 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 386 bmc->fmc_model : amc->fmc_model); 387 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 388 bmc->spi_model : amc->spi_model); 389 390 /* Install first FMC flash content as a boot rom. */ 391 if (drive0) { 392 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 393 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 394 uint64_t size = memory_region_size(&fl->mmio); 395 396 /* 397 * create a ROM region using the default mapping window size of 398 * the flash module. The window size is 64MB for the AST2400 399 * SoC and 128MB for the AST2500 SoC, which is twice as big as 400 * needed by the flash modules of the Aspeed machines. 401 */ 402 if (ASPEED_MACHINE(machine)->mmio_exec) { 403 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 404 &fl->mmio, 0, size); 405 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 406 boot_rom); 407 } else { 408 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 409 size, &error_abort); 410 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 411 boot_rom); 412 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 413 } 414 } 415 416 if (machine->kernel_filename && sc->num_cpus > 1) { 417 /* With no u-boot we must set up a boot stub for the secondary CPU */ 418 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 419 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 420 0x80, &error_abort); 421 memory_region_add_subregion(get_system_memory(), 422 AST_SMP_MAILBOX_BASE, smpboot); 423 424 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 425 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 426 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 427 } 428 429 aspeed_board_binfo.ram_size = machine->ram_size; 430 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 431 aspeed_board_binfo.nb_cpus = sc->num_cpus; 432 433 if (amc->i2c_init) { 434 amc->i2c_init(bmc); 435 } 436 437 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 438 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 439 } 440 441 if (bmc->soc.emmc.num_slots) { 442 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 443 } 444 445 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 446 } 447 448 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 449 { 450 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 451 DeviceState *dev = DEVICE(i2c_dev); 452 453 qdev_prop_set_uint32(dev, "rom-size", rsize); 454 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 455 } 456 457 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 458 { 459 AspeedSoCState *soc = &bmc->soc; 460 DeviceState *dev; 461 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 462 463 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 464 * enough to provide basic RTC features. Alarms will be missing */ 465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 466 467 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 468 eeprom_buf); 469 470 /* add a TMP423 temperature sensor */ 471 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 472 "tmp423", 0x4c)); 473 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 474 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 475 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 476 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 477 } 478 479 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 480 { 481 AspeedSoCState *soc = &bmc->soc; 482 483 /* 484 * The quanta-q71l platform expects tmp75s which are compatible with 485 * tmp105s. 486 */ 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 490 491 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 492 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 493 /* TODO: Add Memory Riser i2c mux and eeproms. */ 494 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 497 498 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 499 500 /* i2c-7 */ 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 502 /* - i2c@0: pmbus@59 */ 503 /* - i2c@1: pmbus@58 */ 504 /* - i2c@2: pmbus@58 */ 505 /* - i2c@3: pmbus@59 */ 506 507 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 508 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 509 } 510 511 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 512 { 513 AspeedSoCState *soc = &bmc->soc; 514 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 515 516 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 517 eeprom_buf); 518 519 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 521 TYPE_TMP105, 0x4d); 522 523 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 524 * plugged on the I2C bus header */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 526 } 527 528 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 529 { 530 /* Start with some devices on our I2C busses */ 531 ast2500_evb_i2c_init(bmc); 532 } 533 534 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 535 { 536 AspeedSoCState *soc = &bmc->soc; 537 538 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 539 * good enough */ 540 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 541 } 542 543 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 544 { 545 AspeedSoCState *soc = &bmc->soc; 546 547 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 548 549 /* The swift board expects a TMP275 but a TMP105 is compatible */ 550 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 551 /* The swift board expects a pca9551 but a pca9552 is compatible */ 552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 553 554 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 557 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 559 /* The swift board expects a pca9539 but a pca9552 is compatible */ 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 561 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 563 /* The swift board expects a pca9539 but a pca9552 is compatible */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 565 0x74); 566 567 /* The swift board expects a TMP275 but a TMP105 is compatible */ 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 570 } 571 572 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 573 { 574 AspeedSoCState *soc = &bmc->soc; 575 576 /* bus 2 : */ 577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 579 /* bus 2 : pca9546 @ 0x73 */ 580 581 /* bus 3 : pca9548 @ 0x70 */ 582 583 /* bus 4 : */ 584 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 585 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 586 eeprom4_54); 587 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 589 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 591 592 /* bus 6 : */ 593 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 594 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 595 /* bus 6 : pca9546 @ 0x73 */ 596 597 /* bus 8 : */ 598 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 599 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 600 eeprom8_56); 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 603 /* bus 8 : adc128d818 @ 0x1d */ 604 /* bus 8 : adc128d818 @ 0x1f */ 605 606 /* 607 * bus 13 : pca9548 @ 0x71 608 * - channel 3: 609 * - tmm421 @ 0x4c 610 * - tmp421 @ 0x4e 611 * - tmp421 @ 0x4f 612 */ 613 614 } 615 616 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 617 { 618 static const struct { 619 unsigned gpio_id; 620 LEDColor color; 621 const char *description; 622 bool gpio_polarity; 623 } pca1_leds[] = { 624 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 625 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 626 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 627 }; 628 AspeedSoCState *soc = &bmc->soc; 629 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 630 DeviceState *dev; 631 LEDState *led; 632 633 /* Bus 3: TODO bmp280@77 */ 634 /* Bus 3: TODO max31785@52 */ 635 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 636 qdev_prop_set_string(dev, "description", "pca1"); 637 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 638 aspeed_i2c_get_bus(&soc->i2c, 3), 639 &error_fatal); 640 641 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 642 led = led_create_simple(OBJECT(bmc), 643 pca1_leds[i].gpio_polarity, 644 pca1_leds[i].color, 645 pca1_leds[i].description); 646 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 647 qdev_get_gpio_in(DEVICE(led), 0)); 648 } 649 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 650 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 651 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 652 653 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 655 0x4a); 656 657 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 658 * good enough */ 659 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 660 661 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 662 eeprom_buf); 663 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 664 qdev_prop_set_string(dev, "description", "pca0"); 665 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 666 aspeed_i2c_get_bus(&soc->i2c, 11), 667 &error_fatal); 668 /* Bus 11: TODO ucd90160@64 */ 669 } 670 671 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 672 { 673 AspeedSoCState *soc = &bmc->soc; 674 DeviceState *dev; 675 676 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 677 "emc1413", 0x4c)); 678 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 679 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 680 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 681 682 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 683 "emc1413", 0x4c)); 684 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 685 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 686 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 687 688 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 689 "emc1413", 0x4c)); 690 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 691 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 692 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 693 694 static uint8_t eeprom_buf[2 * 1024] = { 695 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 696 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 697 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 698 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 699 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 700 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 701 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 702 }; 703 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 704 eeprom_buf); 705 } 706 707 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 708 { 709 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 710 DeviceState *dev = DEVICE(i2c_dev); 711 712 qdev_prop_set_uint32(dev, "rom-size", rsize); 713 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 714 } 715 716 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 717 { 718 AspeedSoCState *soc = &bmc->soc; 719 I2CSlave *i2c_mux; 720 721 /* The at24c256 */ 722 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 723 724 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 725 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 726 0x48); 727 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 728 0x49); 729 730 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 731 "pca9546", 0x70); 732 /* It expects a TMP112 but a TMP105 is compatible */ 733 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 734 0x4a); 735 736 /* It expects a ds3232 but a ds1338 is good enough */ 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 738 739 /* It expects a pca9555 but a pca9552 is compatible */ 740 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552, 741 0x20); 742 } 743 744 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 745 { 746 AspeedSoCState *soc = &bmc->soc; 747 I2CSlave *i2c_mux; 748 749 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 750 751 /* The rainier expects a TMP275 but a TMP105 is compatible */ 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 753 0x48); 754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 755 0x49); 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 757 0x4a); 758 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 759 "pca9546", 0x70); 760 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 761 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 762 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 763 764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 765 0x48); 766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 767 0x49); 768 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 769 "pca9546", 0x70); 770 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 771 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 772 773 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 774 0x48); 775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 776 0x4a); 777 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 778 0x4b); 779 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 780 "pca9546", 0x70); 781 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 782 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 783 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 784 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 785 786 /* Bus 7: TODO max31785@52 */ 787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); 788 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 789 /* Bus 7: TODO si7021-a20@20 */ 790 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 791 0x48); 792 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 793 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 794 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 796 0x48); 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 798 0x4a); 799 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 800 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 802 /* Bus 8: ucd90320@11 */ 803 /* Bus 8: ucd90320@b */ 804 /* Bus 8: ucd90320@c */ 805 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 808 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 809 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 811 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 812 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 813 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 815 0x48); 816 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 817 0x49); 818 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 819 "pca9546", 0x70); 820 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 821 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 822 823 824 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 825 826 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 827 828 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 829 } 830 831 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 832 I2CBus **channels) 833 { 834 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 835 for (int i = 0; i < 8; i++) { 836 channels[i] = pca954x_i2c_get_bus(mux, i); 837 } 838 } 839 840 #define TYPE_LM75 TYPE_TMP105 841 #define TYPE_TMP75 TYPE_TMP105 842 #define TYPE_TMP422 "tmp422" 843 844 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 845 { 846 AspeedSoCState *soc = &bmc->soc; 847 I2CBus *i2c[144] = {}; 848 849 for (int i = 0; i < 16; i++) { 850 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 851 } 852 I2CBus *i2c180 = i2c[2]; 853 I2CBus *i2c480 = i2c[8]; 854 I2CBus *i2c600 = i2c[11]; 855 856 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 857 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 858 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 859 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 860 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 861 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 862 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 863 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 864 for (int i = 0; i < 8; i++) { 865 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 866 } 867 868 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 869 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 870 871 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 872 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 873 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 874 875 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 876 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 877 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 878 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 879 880 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 881 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 882 883 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 884 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 885 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 886 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 887 888 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 889 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 890 891 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 892 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 893 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 894 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 895 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 896 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 897 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 898 899 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 900 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 901 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 902 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 903 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 904 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 905 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 906 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 907 908 for (int i = 0; i < 8; i++) { 909 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 910 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 911 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 912 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 913 } 914 } 915 916 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 917 { 918 return ASPEED_MACHINE(obj)->mmio_exec; 919 } 920 921 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 922 { 923 ASPEED_MACHINE(obj)->mmio_exec = value; 924 } 925 926 static void aspeed_machine_instance_init(Object *obj) 927 { 928 ASPEED_MACHINE(obj)->mmio_exec = false; 929 } 930 931 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 932 { 933 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 934 return g_strdup(bmc->fmc_model); 935 } 936 937 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 938 { 939 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 940 941 g_free(bmc->fmc_model); 942 bmc->fmc_model = g_strdup(value); 943 } 944 945 static char *aspeed_get_spi_model(Object *obj, Error **errp) 946 { 947 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 948 return g_strdup(bmc->spi_model); 949 } 950 951 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 952 { 953 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 954 955 g_free(bmc->spi_model); 956 bmc->spi_model = g_strdup(value); 957 } 958 959 static void aspeed_machine_class_props_init(ObjectClass *oc) 960 { 961 object_class_property_add_bool(oc, "execute-in-place", 962 aspeed_get_mmio_exec, 963 aspeed_set_mmio_exec); 964 object_class_property_set_description(oc, "execute-in-place", 965 "boot directly from CE0 flash device"); 966 967 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 968 aspeed_set_fmc_model); 969 object_class_property_set_description(oc, "fmc-model", 970 "Change the FMC Flash model"); 971 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 972 aspeed_set_spi_model); 973 object_class_property_set_description(oc, "spi-model", 974 "Change the SPI Flash model"); 975 } 976 977 static int aspeed_soc_num_cpus(const char *soc_name) 978 { 979 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 980 return sc->num_cpus; 981 } 982 983 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 984 { 985 MachineClass *mc = MACHINE_CLASS(oc); 986 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 987 988 mc->init = aspeed_machine_init; 989 mc->no_floppy = 1; 990 mc->no_cdrom = 1; 991 mc->no_parallel = 1; 992 mc->default_ram_id = "ram"; 993 amc->macs_mask = ASPEED_MAC0_ON; 994 amc->uart_default = ASPEED_DEV_UART5; 995 996 aspeed_machine_class_props_init(oc); 997 } 998 999 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1000 { 1001 MachineClass *mc = MACHINE_CLASS(oc); 1002 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1003 1004 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1005 amc->soc_name = "ast2400-a1"; 1006 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1007 amc->fmc_model = "n25q256a"; 1008 amc->spi_model = "mx25l25635e"; 1009 amc->num_cs = 1; 1010 amc->i2c_init = palmetto_bmc_i2c_init; 1011 mc->default_ram_size = 256 * MiB; 1012 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1013 aspeed_soc_num_cpus(amc->soc_name); 1014 }; 1015 1016 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1017 { 1018 MachineClass *mc = MACHINE_CLASS(oc); 1019 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1020 1021 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1022 amc->soc_name = "ast2400-a1"; 1023 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1024 amc->fmc_model = "n25q256a"; 1025 amc->spi_model = "mx25l25635e"; 1026 amc->num_cs = 1; 1027 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1028 mc->default_ram_size = 128 * MiB; 1029 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1030 aspeed_soc_num_cpus(amc->soc_name); 1031 } 1032 1033 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1034 void *data) 1035 { 1036 MachineClass *mc = MACHINE_CLASS(oc); 1037 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1038 1039 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1040 amc->soc_name = "ast2400-a1"; 1041 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1042 amc->fmc_model = "mx25l25635e"; 1043 amc->spi_model = "mx25l25635e"; 1044 amc->num_cs = 1; 1045 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1046 amc->i2c_init = palmetto_bmc_i2c_init; 1047 mc->default_ram_size = 256 * MiB; 1048 } 1049 1050 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1051 { 1052 MachineClass *mc = MACHINE_CLASS(oc); 1053 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1054 1055 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1056 amc->soc_name = "ast2500-a1"; 1057 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1058 amc->fmc_model = "w25q256"; 1059 amc->spi_model = "mx25l25635e"; 1060 amc->num_cs = 1; 1061 amc->i2c_init = ast2500_evb_i2c_init; 1062 mc->default_ram_size = 512 * MiB; 1063 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1064 aspeed_soc_num_cpus(amc->soc_name); 1065 }; 1066 1067 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1068 { 1069 MachineClass *mc = MACHINE_CLASS(oc); 1070 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1071 1072 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1073 amc->soc_name = "ast2500-a1"; 1074 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1075 amc->fmc_model = "n25q256a"; 1076 amc->spi_model = "mx66l1g45g"; 1077 amc->num_cs = 2; 1078 amc->i2c_init = romulus_bmc_i2c_init; 1079 mc->default_ram_size = 512 * MiB; 1080 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1081 aspeed_soc_num_cpus(amc->soc_name); 1082 }; 1083 1084 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1085 { 1086 MachineClass *mc = MACHINE_CLASS(oc); 1087 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1088 1089 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1090 amc->soc_name = "ast2500-a1"; 1091 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1092 amc->fmc_model = "mx66l1g45g"; 1093 amc->spi_model = "mx66l1g45g"; 1094 amc->num_cs = 2; 1095 amc->i2c_init = sonorapass_bmc_i2c_init; 1096 mc->default_ram_size = 512 * MiB; 1097 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1098 aspeed_soc_num_cpus(amc->soc_name); 1099 }; 1100 1101 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 1102 { 1103 MachineClass *mc = MACHINE_CLASS(oc); 1104 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1105 1106 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 1107 amc->soc_name = "ast2500-a1"; 1108 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 1109 amc->fmc_model = "mx66l1g45g"; 1110 amc->spi_model = "mx66l1g45g"; 1111 amc->num_cs = 2; 1112 amc->i2c_init = swift_bmc_i2c_init; 1113 mc->default_ram_size = 512 * MiB; 1114 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1115 aspeed_soc_num_cpus(amc->soc_name); 1116 1117 mc->deprecation_reason = "redundant system. Please use a similar " 1118 "OpenPOWER BMC, Witherspoon or Romulus."; 1119 }; 1120 1121 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1122 { 1123 MachineClass *mc = MACHINE_CLASS(oc); 1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1125 1126 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1127 amc->soc_name = "ast2500-a1"; 1128 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1129 amc->fmc_model = "mx25l25635e"; 1130 amc->spi_model = "mx66l1g45g"; 1131 amc->num_cs = 2; 1132 amc->i2c_init = witherspoon_bmc_i2c_init; 1133 mc->default_ram_size = 512 * MiB; 1134 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1135 aspeed_soc_num_cpus(amc->soc_name); 1136 }; 1137 1138 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1139 { 1140 MachineClass *mc = MACHINE_CLASS(oc); 1141 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1142 1143 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1144 amc->soc_name = "ast2600-a3"; 1145 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1146 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1147 amc->fmc_model = "w25q512jv"; 1148 amc->spi_model = "mx66u51235f"; 1149 amc->num_cs = 1; 1150 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1151 ASPEED_MAC3_ON; 1152 amc->i2c_init = ast2600_evb_i2c_init; 1153 mc->default_ram_size = 1 * GiB; 1154 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1155 aspeed_soc_num_cpus(amc->soc_name); 1156 }; 1157 1158 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1159 { 1160 MachineClass *mc = MACHINE_CLASS(oc); 1161 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1162 1163 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1164 amc->soc_name = "ast2600-a3"; 1165 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1166 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1167 amc->fmc_model = "mx66l1g45g"; 1168 amc->spi_model = "mx66l1g45g"; 1169 amc->num_cs = 2; 1170 amc->macs_mask = ASPEED_MAC2_ON; 1171 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1172 mc->default_ram_size = 1 * GiB; 1173 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1174 aspeed_soc_num_cpus(amc->soc_name); 1175 }; 1176 1177 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1178 { 1179 MachineClass *mc = MACHINE_CLASS(oc); 1180 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1181 1182 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1183 amc->soc_name = "ast2500-a1"; 1184 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1185 amc->fmc_model = "n25q512a"; 1186 amc->spi_model = "mx25l25635e"; 1187 amc->num_cs = 2; 1188 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1189 amc->i2c_init = g220a_bmc_i2c_init; 1190 mc->default_ram_size = 1024 * MiB; 1191 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1192 aspeed_soc_num_cpus(amc->soc_name); 1193 }; 1194 1195 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1196 { 1197 MachineClass *mc = MACHINE_CLASS(oc); 1198 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1199 1200 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1201 amc->soc_name = "ast2500-a1"; 1202 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1203 amc->fmc_model = "n25q512a"; 1204 amc->spi_model = "mx25l25635e"; 1205 amc->num_cs = 2; 1206 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1207 amc->i2c_init = fp5280g2_bmc_i2c_init; 1208 mc->default_ram_size = 512 * MiB; 1209 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1210 aspeed_soc_num_cpus(amc->soc_name); 1211 }; 1212 1213 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1214 { 1215 MachineClass *mc = MACHINE_CLASS(oc); 1216 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1217 1218 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1219 amc->soc_name = "ast2600-a3"; 1220 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1221 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1222 amc->fmc_model = "mx66l1g45g"; 1223 amc->spi_model = "mx66l1g45g"; 1224 amc->num_cs = 2; 1225 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1226 amc->i2c_init = rainier_bmc_i2c_init; 1227 mc->default_ram_size = 1 * GiB; 1228 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1229 aspeed_soc_num_cpus(amc->soc_name); 1230 }; 1231 1232 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1233 #if HOST_LONG_BITS == 32 1234 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1235 #else 1236 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1237 #endif 1238 1239 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1240 { 1241 MachineClass *mc = MACHINE_CLASS(oc); 1242 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1243 1244 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1245 amc->soc_name = "ast2600-a3"; 1246 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1247 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1248 amc->fmc_model = "mx66l1g45g"; 1249 amc->spi_model = "mx66l1g45g"; 1250 amc->num_cs = 2; 1251 amc->macs_mask = ASPEED_MAC3_ON; 1252 amc->i2c_init = fuji_bmc_i2c_init; 1253 amc->uart_default = ASPEED_DEV_UART1; 1254 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1255 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1256 aspeed_soc_num_cpus(amc->soc_name); 1257 }; 1258 1259 static const TypeInfo aspeed_machine_types[] = { 1260 { 1261 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1262 .parent = TYPE_ASPEED_MACHINE, 1263 .class_init = aspeed_machine_palmetto_class_init, 1264 }, { 1265 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1266 .parent = TYPE_ASPEED_MACHINE, 1267 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1268 }, { 1269 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1270 .parent = TYPE_ASPEED_MACHINE, 1271 .class_init = aspeed_machine_ast2500_evb_class_init, 1272 }, { 1273 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1274 .parent = TYPE_ASPEED_MACHINE, 1275 .class_init = aspeed_machine_romulus_class_init, 1276 }, { 1277 .name = MACHINE_TYPE_NAME("swift-bmc"), 1278 .parent = TYPE_ASPEED_MACHINE, 1279 .class_init = aspeed_machine_swift_class_init, 1280 }, { 1281 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1282 .parent = TYPE_ASPEED_MACHINE, 1283 .class_init = aspeed_machine_sonorapass_class_init, 1284 }, { 1285 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1286 .parent = TYPE_ASPEED_MACHINE, 1287 .class_init = aspeed_machine_witherspoon_class_init, 1288 }, { 1289 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1290 .parent = TYPE_ASPEED_MACHINE, 1291 .class_init = aspeed_machine_ast2600_evb_class_init, 1292 }, { 1293 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1294 .parent = TYPE_ASPEED_MACHINE, 1295 .class_init = aspeed_machine_tacoma_class_init, 1296 }, { 1297 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1298 .parent = TYPE_ASPEED_MACHINE, 1299 .class_init = aspeed_machine_g220a_class_init, 1300 }, { 1301 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1302 .parent = TYPE_ASPEED_MACHINE, 1303 .class_init = aspeed_machine_fp5280g2_class_init, 1304 }, { 1305 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1306 .parent = TYPE_ASPEED_MACHINE, 1307 .class_init = aspeed_machine_quanta_q71l_class_init, 1308 }, { 1309 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1310 .parent = TYPE_ASPEED_MACHINE, 1311 .class_init = aspeed_machine_rainier_class_init, 1312 }, { 1313 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1314 .parent = TYPE_ASPEED_MACHINE, 1315 .class_init = aspeed_machine_fuji_class_init, 1316 }, { 1317 .name = TYPE_ASPEED_MACHINE, 1318 .parent = TYPE_MACHINE, 1319 .instance_size = sizeof(AspeedMachineState), 1320 .instance_init = aspeed_machine_instance_init, 1321 .class_size = sizeof(AspeedMachineClass), 1322 .class_init = aspeed_machine_class_init, 1323 .abstract = true, 1324 } 1325 }; 1326 1327 DEFINE_TYPES(aspeed_machine_types) 1328