1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/smbus_eeprom.h" 18 #include "hw/misc/pca9552.h" 19 #include "hw/misc/tmp105.h" 20 #include "hw/misc/led.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/block-backend.h" 23 #include "hw/loader.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 27 static struct arm_boot_info aspeed_board_binfo = { 28 .board_id = -1, /* device-tree-only board */ 29 }; 30 31 struct AspeedMachineState { 32 /* Private */ 33 MachineState parent_obj; 34 /* Public */ 35 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 bool mmio_exec; 40 char *fmc_model; 41 char *spi_model; 42 }; 43 44 /* Palmetto hardware value: 0x120CE416 */ 45 #define PALMETTO_BMC_HW_STRAP1 ( \ 46 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 47 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 48 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 49 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 50 SCU_HW_STRAP_VGA_CLASS_CODE | \ 51 SCU_HW_STRAP_LPC_RESET_PIN | \ 52 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 53 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 54 SCU_HW_STRAP_SPI_WIDTH | \ 55 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 56 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 57 58 /* TODO: Find the actual hardware value */ 59 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* AST2500 evb hardware value: 0xF100C2E6 */ 73 #define AST2500_EVB_HW_STRAP1 (( \ 74 AST2500_HW_STRAP1_DEFAULTS | \ 75 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 76 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 77 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 78 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 79 SCU_HW_STRAP_MAC1_RGMII | \ 80 SCU_HW_STRAP_MAC0_RGMII) & \ 81 ~SCU_HW_STRAP_2ND_BOOT_WDT) 82 83 /* Romulus hardware value: 0xF10AD206 */ 84 #define ROMULUS_BMC_HW_STRAP1 ( \ 85 AST2500_HW_STRAP1_DEFAULTS | \ 86 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 87 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 88 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 89 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 90 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 91 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 92 93 /* Sonorapass hardware value: 0xF100D216 */ 94 #define SONORAPASS_BMC_HW_STRAP1 ( \ 95 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 96 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 97 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 98 SCU_AST2500_HW_STRAP_RESERVED28 | \ 99 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 100 SCU_HW_STRAP_VGA_CLASS_CODE | \ 101 SCU_HW_STRAP_LPC_RESET_PIN | \ 102 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 103 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 104 SCU_HW_STRAP_VGA_BIOS_ROM | \ 105 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 106 SCU_AST2500_HW_STRAP_RESERVED1) 107 108 /* Swift hardware value: 0xF11AD206 */ 109 #define SWIFT_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_H_PLL_BYPASS_EN | \ 116 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 117 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 118 119 #define G220A_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_2ND_BOOT_WDT | \ 126 SCU_HW_STRAP_VGA_CLASS_CODE | \ 127 SCU_HW_STRAP_LPC_RESET_PIN | \ 128 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 129 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 134 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 135 136 /* AST2600 evb hardware value */ 137 #define AST2600_EVB_HW_STRAP1 0x000000C0 138 #define AST2600_EVB_HW_STRAP2 0x00000003 139 140 /* Tacoma hardware value */ 141 #define TACOMA_BMC_HW_STRAP1 0x00000000 142 #define TACOMA_BMC_HW_STRAP2 0x00000040 143 144 /* 145 * The max ram region is for firmwares that scan the address space 146 * with load/store to guess how much RAM the SoC has. 147 */ 148 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 149 { 150 return 0; 151 } 152 153 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 154 unsigned size) 155 { 156 /* Discard writes */ 157 } 158 159 static const MemoryRegionOps max_ram_ops = { 160 .read = max_ram_read, 161 .write = max_ram_write, 162 .endianness = DEVICE_NATIVE_ENDIAN, 163 }; 164 165 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 166 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 167 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 168 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 169 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 170 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 171 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 172 173 static void aspeed_write_smpboot(ARMCPU *cpu, 174 const struct arm_boot_info *info) 175 { 176 static const uint32_t poll_mailbox_ready[] = { 177 /* 178 * r2 = per-cpu go sign value 179 * r1 = AST_SMP_MBOX_FIELD_ENTRY 180 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 181 */ 182 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 183 0xe21000ff, /* ands r0, r0, #255 */ 184 0xe59f201c, /* ldr r2, [pc, #28] */ 185 0xe1822000, /* orr r2, r2, r0 */ 186 187 0xe59f1018, /* ldr r1, [pc, #24] */ 188 0xe59f0018, /* ldr r0, [pc, #24] */ 189 190 0xe320f002, /* wfe */ 191 0xe5904000, /* ldr r4, [r0] */ 192 0xe1520004, /* cmp r2, r4 */ 193 0x1afffffb, /* bne <wfe> */ 194 0xe591f000, /* ldr pc, [r1] */ 195 AST_SMP_MBOX_GOSIGN, 196 AST_SMP_MBOX_FIELD_ENTRY, 197 AST_SMP_MBOX_FIELD_GOSIGN, 198 }; 199 200 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 201 sizeof(poll_mailbox_ready), 202 info->smp_loader_start); 203 } 204 205 static void aspeed_reset_secondary(ARMCPU *cpu, 206 const struct arm_boot_info *info) 207 { 208 AddressSpace *as = arm_boot_address_space(cpu, info); 209 CPUState *cs = CPU(cpu); 210 211 /* info->smp_bootreg_addr */ 212 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 213 MEMTXATTRS_UNSPECIFIED, NULL); 214 cpu_set_pc(cs, info->smp_loader_start); 215 } 216 217 #define FIRMWARE_ADDR 0x0 218 219 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 220 Error **errp) 221 { 222 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 223 uint8_t *storage; 224 int64_t size; 225 226 /* The block backend size should have already been 'validated' by 227 * the creation of the m25p80 object. 228 */ 229 size = blk_getlength(blk); 230 if (size <= 0) { 231 error_setg(errp, "failed to get flash size"); 232 return; 233 } 234 235 if (rom_size > size) { 236 rom_size = size; 237 } 238 239 storage = g_new0(uint8_t, rom_size); 240 if (blk_pread(blk, 0, storage, rom_size) < 0) { 241 error_setg(errp, "failed to read the initial flash content"); 242 return; 243 } 244 245 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 246 g_free(storage); 247 } 248 249 static void aspeed_board_init_flashes(AspeedSMCState *s, 250 const char *flashtype) 251 { 252 int i ; 253 254 for (i = 0; i < s->num_cs; ++i) { 255 AspeedSMCFlash *fl = &s->flashes[i]; 256 DriveInfo *dinfo = drive_get_next(IF_MTD); 257 qemu_irq cs_line; 258 259 fl->flash = qdev_new(flashtype); 260 if (dinfo) { 261 qdev_prop_set_drive(fl->flash, "drive", 262 blk_by_legacy_dinfo(dinfo)); 263 } 264 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 265 266 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 267 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 268 } 269 } 270 271 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 272 { 273 DeviceState *card; 274 275 if (!dinfo) { 276 return; 277 } 278 card = qdev_new(TYPE_SD_CARD); 279 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 280 &error_fatal); 281 qdev_realize_and_unref(card, 282 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 283 &error_fatal); 284 } 285 286 static void aspeed_machine_init(MachineState *machine) 287 { 288 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 289 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 290 AspeedSoCClass *sc; 291 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 292 ram_addr_t max_ram_size; 293 int i; 294 NICInfo *nd = &nd_table[0]; 295 296 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 297 4 * GiB); 298 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 299 300 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 301 302 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 303 304 /* 305 * This will error out if isize is not supported by memory controller. 306 */ 307 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 308 &error_fatal); 309 310 for (i = 0; i < sc->macs_num; i++) { 311 if ((amc->macs_mask & (1 << i)) && nd->used) { 312 qemu_check_nic_model(nd, TYPE_FTGMAC100); 313 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 314 nd++; 315 } 316 } 317 318 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 319 &error_abort); 320 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 321 &error_abort); 322 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 323 &error_abort); 324 object_property_set_link(OBJECT(&bmc->soc), "dram", 325 OBJECT(&bmc->ram_container), &error_abort); 326 if (machine->kernel_filename) { 327 /* 328 * When booting with a -kernel command line there is no u-boot 329 * that runs to unlock the SCU. In this case set the default to 330 * be unlocked as the kernel expects 331 */ 332 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 333 ASPEED_SCU_PROT_KEY, &error_abort); 334 } 335 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 336 337 memory_region_add_subregion(get_system_memory(), 338 sc->memmap[ASPEED_DEV_SDRAM], 339 &bmc->ram_container); 340 341 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 342 &error_abort); 343 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 344 "max_ram", max_ram_size - machine->ram_size); 345 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 346 347 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 348 bmc->fmc_model : amc->fmc_model); 349 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 350 bmc->spi_model : amc->spi_model); 351 352 /* Install first FMC flash content as a boot rom. */ 353 if (drive0) { 354 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 355 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 356 357 /* 358 * create a ROM region using the default mapping window size of 359 * the flash module. The window size is 64MB for the AST2400 360 * SoC and 128MB for the AST2500 SoC, which is twice as big as 361 * needed by the flash modules of the Aspeed machines. 362 */ 363 if (ASPEED_MACHINE(machine)->mmio_exec) { 364 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 365 &fl->mmio, 0, fl->size); 366 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 367 boot_rom); 368 } else { 369 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 370 fl->size, &error_abort); 371 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 372 boot_rom); 373 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 374 } 375 } 376 377 if (machine->kernel_filename && sc->num_cpus > 1) { 378 /* With no u-boot we must set up a boot stub for the secondary CPU */ 379 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 380 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 381 0x80, &error_abort); 382 memory_region_add_subregion(get_system_memory(), 383 AST_SMP_MAILBOX_BASE, smpboot); 384 385 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 386 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 387 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 388 } 389 390 aspeed_board_binfo.ram_size = machine->ram_size; 391 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 392 aspeed_board_binfo.nb_cpus = sc->num_cpus; 393 394 if (amc->i2c_init) { 395 amc->i2c_init(bmc); 396 } 397 398 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 399 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 400 } 401 402 if (bmc->soc.emmc.num_slots) { 403 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 404 } 405 406 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 407 } 408 409 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 410 { 411 AspeedSoCState *soc = &bmc->soc; 412 DeviceState *dev; 413 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 414 415 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 416 * enough to provide basic RTC features. Alarms will be missing */ 417 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 418 419 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 420 eeprom_buf); 421 422 /* add a TMP423 temperature sensor */ 423 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 424 "tmp423", 0x4c)); 425 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 426 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 427 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 428 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 429 } 430 431 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 432 { 433 AspeedSoCState *soc = &bmc->soc; 434 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 435 436 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 437 eeprom_buf); 438 439 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 440 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 441 TYPE_TMP105, 0x4d); 442 443 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 444 * plugged on the I2C bus header */ 445 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 446 } 447 448 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 449 { 450 /* Start with some devices on our I2C busses */ 451 ast2500_evb_i2c_init(bmc); 452 } 453 454 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 455 { 456 AspeedSoCState *soc = &bmc->soc; 457 458 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 459 * good enough */ 460 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 461 } 462 463 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 464 { 465 AspeedSoCState *soc = &bmc->soc; 466 467 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 468 469 /* The swift board expects a TMP275 but a TMP105 is compatible */ 470 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 471 /* The swift board expects a pca9551 but a pca9552 is compatible */ 472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 473 474 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 475 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 476 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 477 478 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 479 /* The swift board expects a pca9539 but a pca9552 is compatible */ 480 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 481 482 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 483 /* The swift board expects a pca9539 but a pca9552 is compatible */ 484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 485 0x74); 486 487 /* The swift board expects a TMP275 but a TMP105 is compatible */ 488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 490 } 491 492 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 493 { 494 AspeedSoCState *soc = &bmc->soc; 495 496 /* bus 2 : */ 497 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 499 /* bus 2 : pca9546 @ 0x73 */ 500 501 /* bus 3 : pca9548 @ 0x70 */ 502 503 /* bus 4 : */ 504 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 505 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 506 eeprom4_54); 507 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 508 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 509 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 510 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 511 512 /* bus 6 : */ 513 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 515 /* bus 6 : pca9546 @ 0x73 */ 516 517 /* bus 8 : */ 518 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 519 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 520 eeprom8_56); 521 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 523 /* bus 8 : adc128d818 @ 0x1d */ 524 /* bus 8 : adc128d818 @ 0x1f */ 525 526 /* 527 * bus 13 : pca9548 @ 0x71 528 * - channel 3: 529 * - tmm421 @ 0x4c 530 * - tmp421 @ 0x4e 531 * - tmp421 @ 0x4f 532 */ 533 534 } 535 536 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 537 { 538 static const struct { 539 unsigned gpio_id; 540 LEDColor color; 541 const char *description; 542 bool gpio_polarity; 543 } pca1_leds[] = { 544 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 545 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 546 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 547 }; 548 AspeedSoCState *soc = &bmc->soc; 549 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 550 DeviceState *dev; 551 LEDState *led; 552 553 /* Bus 3: TODO bmp280@77 */ 554 /* Bus 3: TODO max31785@52 */ 555 /* Bus 3: TODO dps310@76 */ 556 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 557 qdev_prop_set_string(dev, "description", "pca1"); 558 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 559 aspeed_i2c_get_bus(&soc->i2c, 3), 560 &error_fatal); 561 562 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 563 led = led_create_simple(OBJECT(bmc), 564 pca1_leds[i].gpio_polarity, 565 pca1_leds[i].color, 566 pca1_leds[i].description); 567 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 568 qdev_get_gpio_in(DEVICE(led), 0)); 569 } 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 572 573 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 575 0x4a); 576 577 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 578 * good enough */ 579 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 580 581 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 582 eeprom_buf); 583 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 584 qdev_prop_set_string(dev, "description", "pca0"); 585 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 586 aspeed_i2c_get_bus(&soc->i2c, 11), 587 &error_fatal); 588 /* Bus 11: TODO ucd90160@64 */ 589 } 590 591 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 592 { 593 AspeedSoCState *soc = &bmc->soc; 594 DeviceState *dev; 595 596 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 597 "emc1413", 0x4c)); 598 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 599 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 600 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 601 602 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 603 "emc1413", 0x4c)); 604 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 605 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 606 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 607 608 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 609 "emc1413", 0x4c)); 610 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 611 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 612 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 613 614 static uint8_t eeprom_buf[2 * 1024] = { 615 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 616 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 617 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 618 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 619 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 620 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 621 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 622 }; 623 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 624 eeprom_buf); 625 } 626 627 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 628 { 629 return ASPEED_MACHINE(obj)->mmio_exec; 630 } 631 632 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 633 { 634 ASPEED_MACHINE(obj)->mmio_exec = value; 635 } 636 637 static void aspeed_machine_instance_init(Object *obj) 638 { 639 ASPEED_MACHINE(obj)->mmio_exec = false; 640 } 641 642 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 643 { 644 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 645 return g_strdup(bmc->fmc_model); 646 } 647 648 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 649 { 650 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 651 652 g_free(bmc->fmc_model); 653 bmc->fmc_model = g_strdup(value); 654 } 655 656 static char *aspeed_get_spi_model(Object *obj, Error **errp) 657 { 658 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 659 return g_strdup(bmc->spi_model); 660 } 661 662 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 663 { 664 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 665 666 g_free(bmc->spi_model); 667 bmc->spi_model = g_strdup(value); 668 } 669 670 static void aspeed_machine_class_props_init(ObjectClass *oc) 671 { 672 object_class_property_add_bool(oc, "execute-in-place", 673 aspeed_get_mmio_exec, 674 aspeed_set_mmio_exec); 675 object_class_property_set_description(oc, "execute-in-place", 676 "boot directly from CE0 flash device"); 677 678 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 679 aspeed_set_fmc_model); 680 object_class_property_set_description(oc, "fmc-model", 681 "Change the FMC Flash model"); 682 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 683 aspeed_set_spi_model); 684 object_class_property_set_description(oc, "spi-model", 685 "Change the SPI Flash model"); 686 } 687 688 static int aspeed_soc_num_cpus(const char *soc_name) 689 { 690 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 691 return sc->num_cpus; 692 } 693 694 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 695 { 696 MachineClass *mc = MACHINE_CLASS(oc); 697 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 698 699 mc->init = aspeed_machine_init; 700 mc->no_floppy = 1; 701 mc->no_cdrom = 1; 702 mc->no_parallel = 1; 703 mc->default_ram_id = "ram"; 704 amc->macs_mask = ASPEED_MAC0_ON; 705 706 aspeed_machine_class_props_init(oc); 707 } 708 709 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 710 { 711 MachineClass *mc = MACHINE_CLASS(oc); 712 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 713 714 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 715 amc->soc_name = "ast2400-a1"; 716 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 717 amc->fmc_model = "n25q256a"; 718 amc->spi_model = "mx25l25635e"; 719 amc->num_cs = 1; 720 amc->i2c_init = palmetto_bmc_i2c_init; 721 mc->default_ram_size = 256 * MiB; 722 mc->default_cpus = mc->min_cpus = mc->max_cpus = 723 aspeed_soc_num_cpus(amc->soc_name); 724 }; 725 726 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 727 void *data) 728 { 729 MachineClass *mc = MACHINE_CLASS(oc); 730 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 731 732 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 733 amc->soc_name = "ast2400-a1"; 734 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 735 amc->fmc_model = "mx25l25635e"; 736 amc->spi_model = "mx25l25635e"; 737 amc->num_cs = 1; 738 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 739 amc->i2c_init = palmetto_bmc_i2c_init; 740 mc->default_ram_size = 256 * MiB; 741 } 742 743 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 744 { 745 MachineClass *mc = MACHINE_CLASS(oc); 746 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 747 748 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 749 amc->soc_name = "ast2500-a1"; 750 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 751 amc->fmc_model = "w25q256"; 752 amc->spi_model = "mx25l25635e"; 753 amc->num_cs = 1; 754 amc->i2c_init = ast2500_evb_i2c_init; 755 mc->default_ram_size = 512 * MiB; 756 mc->default_cpus = mc->min_cpus = mc->max_cpus = 757 aspeed_soc_num_cpus(amc->soc_name); 758 }; 759 760 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 761 { 762 MachineClass *mc = MACHINE_CLASS(oc); 763 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 764 765 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 766 amc->soc_name = "ast2500-a1"; 767 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 768 amc->fmc_model = "n25q256a"; 769 amc->spi_model = "mx66l1g45g"; 770 amc->num_cs = 2; 771 amc->i2c_init = romulus_bmc_i2c_init; 772 mc->default_ram_size = 512 * MiB; 773 mc->default_cpus = mc->min_cpus = mc->max_cpus = 774 aspeed_soc_num_cpus(amc->soc_name); 775 }; 776 777 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 778 { 779 MachineClass *mc = MACHINE_CLASS(oc); 780 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 781 782 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 783 amc->soc_name = "ast2500-a1"; 784 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 785 amc->fmc_model = "mx66l1g45g"; 786 amc->spi_model = "mx66l1g45g"; 787 amc->num_cs = 2; 788 amc->i2c_init = sonorapass_bmc_i2c_init; 789 mc->default_ram_size = 512 * MiB; 790 mc->default_cpus = mc->min_cpus = mc->max_cpus = 791 aspeed_soc_num_cpus(amc->soc_name); 792 }; 793 794 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 795 { 796 MachineClass *mc = MACHINE_CLASS(oc); 797 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 798 799 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 800 amc->soc_name = "ast2500-a1"; 801 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 802 amc->fmc_model = "mx66l1g45g"; 803 amc->spi_model = "mx66l1g45g"; 804 amc->num_cs = 2; 805 amc->i2c_init = swift_bmc_i2c_init; 806 mc->default_ram_size = 512 * MiB; 807 mc->default_cpus = mc->min_cpus = mc->max_cpus = 808 aspeed_soc_num_cpus(amc->soc_name); 809 }; 810 811 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 812 { 813 MachineClass *mc = MACHINE_CLASS(oc); 814 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 815 816 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 817 amc->soc_name = "ast2500-a1"; 818 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 819 amc->fmc_model = "mx25l25635e"; 820 amc->spi_model = "mx66l1g45g"; 821 amc->num_cs = 2; 822 amc->i2c_init = witherspoon_bmc_i2c_init; 823 mc->default_ram_size = 512 * MiB; 824 mc->default_cpus = mc->min_cpus = mc->max_cpus = 825 aspeed_soc_num_cpus(amc->soc_name); 826 }; 827 828 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 829 { 830 MachineClass *mc = MACHINE_CLASS(oc); 831 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 832 833 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 834 amc->soc_name = "ast2600-a1"; 835 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 836 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 837 amc->fmc_model = "w25q512jv"; 838 amc->spi_model = "mx66u51235f"; 839 amc->num_cs = 1; 840 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 841 amc->i2c_init = ast2600_evb_i2c_init; 842 mc->default_ram_size = 1 * GiB; 843 mc->default_cpus = mc->min_cpus = mc->max_cpus = 844 aspeed_soc_num_cpus(amc->soc_name); 845 }; 846 847 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 848 { 849 MachineClass *mc = MACHINE_CLASS(oc); 850 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 851 852 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 853 amc->soc_name = "ast2600-a1"; 854 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 855 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 856 amc->fmc_model = "mx66l1g45g"; 857 amc->spi_model = "mx66l1g45g"; 858 amc->num_cs = 2; 859 amc->macs_mask = ASPEED_MAC2_ON; 860 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 861 mc->default_ram_size = 1 * GiB; 862 mc->default_cpus = mc->min_cpus = mc->max_cpus = 863 aspeed_soc_num_cpus(amc->soc_name); 864 }; 865 866 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 867 { 868 MachineClass *mc = MACHINE_CLASS(oc); 869 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 870 871 mc->desc = "Bytedance G220A BMC (ARM1176)"; 872 amc->soc_name = "ast2500-a1"; 873 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 874 amc->fmc_model = "n25q512a"; 875 amc->spi_model = "mx25l25635e"; 876 amc->num_cs = 2; 877 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON; 878 amc->i2c_init = g220a_bmc_i2c_init; 879 mc->default_ram_size = 1024 * MiB; 880 mc->default_cpus = mc->min_cpus = mc->max_cpus = 881 aspeed_soc_num_cpus(amc->soc_name); 882 }; 883 884 static const TypeInfo aspeed_machine_types[] = { 885 { 886 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 887 .parent = TYPE_ASPEED_MACHINE, 888 .class_init = aspeed_machine_palmetto_class_init, 889 }, { 890 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 891 .parent = TYPE_ASPEED_MACHINE, 892 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 893 }, { 894 .name = MACHINE_TYPE_NAME("ast2500-evb"), 895 .parent = TYPE_ASPEED_MACHINE, 896 .class_init = aspeed_machine_ast2500_evb_class_init, 897 }, { 898 .name = MACHINE_TYPE_NAME("romulus-bmc"), 899 .parent = TYPE_ASPEED_MACHINE, 900 .class_init = aspeed_machine_romulus_class_init, 901 }, { 902 .name = MACHINE_TYPE_NAME("swift-bmc"), 903 .parent = TYPE_ASPEED_MACHINE, 904 .class_init = aspeed_machine_swift_class_init, 905 }, { 906 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 907 .parent = TYPE_ASPEED_MACHINE, 908 .class_init = aspeed_machine_sonorapass_class_init, 909 }, { 910 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 911 .parent = TYPE_ASPEED_MACHINE, 912 .class_init = aspeed_machine_witherspoon_class_init, 913 }, { 914 .name = MACHINE_TYPE_NAME("ast2600-evb"), 915 .parent = TYPE_ASPEED_MACHINE, 916 .class_init = aspeed_machine_ast2600_evb_class_init, 917 }, { 918 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 919 .parent = TYPE_ASPEED_MACHINE, 920 .class_init = aspeed_machine_tacoma_class_init, 921 }, { 922 .name = MACHINE_TYPE_NAME("g220a-bmc"), 923 .parent = TYPE_ASPEED_MACHINE, 924 .class_init = aspeed_machine_g220a_class_init, 925 }, { 926 .name = TYPE_ASPEED_MACHINE, 927 .parent = TYPE_MACHINE, 928 .instance_size = sizeof(AspeedMachineState), 929 .instance_init = aspeed_machine_instance_init, 930 .class_size = sizeof(AspeedMachineClass), 931 .class_init = aspeed_machine_class_init, 932 .abstract = true, 933 } 934 }; 935 936 DEFINE_TYPES(aspeed_machine_types) 937