1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion ram; 39 MemoryRegion max_ram; 40 }; 41 42 /* Palmetto hardware value: 0x120CE416 */ 43 #define PALMETTO_BMC_HW_STRAP1 ( \ 44 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 45 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 46 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 47 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 48 SCU_HW_STRAP_VGA_CLASS_CODE | \ 49 SCU_HW_STRAP_LPC_RESET_PIN | \ 50 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 51 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 52 SCU_HW_STRAP_SPI_WIDTH | \ 53 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 54 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 55 56 /* AST2500 evb hardware value: 0xF100C2E6 */ 57 #define AST2500_EVB_HW_STRAP1 (( \ 58 AST2500_HW_STRAP1_DEFAULTS | \ 59 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 60 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 61 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 62 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 63 SCU_HW_STRAP_MAC1_RGMII | \ 64 SCU_HW_STRAP_MAC0_RGMII) & \ 65 ~SCU_HW_STRAP_2ND_BOOT_WDT) 66 67 /* Romulus hardware value: 0xF10AD206 */ 68 #define ROMULUS_BMC_HW_STRAP1 ( \ 69 AST2500_HW_STRAP1_DEFAULTS | \ 70 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 71 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 72 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 73 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 74 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 75 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 76 77 /* Swift hardware value: 0xF11AD206 */ 78 #define SWIFT_BMC_HW_STRAP1 ( \ 79 AST2500_HW_STRAP1_DEFAULTS | \ 80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 82 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 84 SCU_H_PLL_BYPASS_EN | \ 85 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 86 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 87 88 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 89 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 90 91 /* AST2600 evb hardware value */ 92 #define AST2600_EVB_HW_STRAP1 0x000000C0 93 #define AST2600_EVB_HW_STRAP2 0x00000003 94 95 /* 96 * The max ram region is for firmwares that scan the address space 97 * with load/store to guess how much RAM the SoC has. 98 */ 99 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 100 { 101 return 0; 102 } 103 104 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 105 unsigned size) 106 { 107 /* Discard writes */ 108 } 109 110 static const MemoryRegionOps max_ram_ops = { 111 .read = max_ram_read, 112 .write = max_ram_write, 113 .endianness = DEVICE_NATIVE_ENDIAN, 114 }; 115 116 #define FIRMWARE_ADDR 0x0 117 118 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 119 Error **errp) 120 { 121 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 122 uint8_t *storage; 123 int64_t size; 124 125 /* The block backend size should have already been 'validated' by 126 * the creation of the m25p80 object. 127 */ 128 size = blk_getlength(blk); 129 if (size <= 0) { 130 error_setg(errp, "failed to get flash size"); 131 return; 132 } 133 134 if (rom_size > size) { 135 rom_size = size; 136 } 137 138 storage = g_new0(uint8_t, rom_size); 139 if (blk_pread(blk, 0, storage, rom_size) < 0) { 140 error_setg(errp, "failed to read the initial flash content"); 141 return; 142 } 143 144 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 145 g_free(storage); 146 } 147 148 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 149 Error **errp) 150 { 151 int i ; 152 153 for (i = 0; i < s->num_cs; ++i) { 154 AspeedSMCFlash *fl = &s->flashes[i]; 155 DriveInfo *dinfo = drive_get_next(IF_MTD); 156 qemu_irq cs_line; 157 158 fl->flash = ssi_create_slave_no_init(s->spi, flashtype); 159 if (dinfo) { 160 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 161 errp); 162 } 163 qdev_init_nofail(fl->flash); 164 165 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 166 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 167 } 168 } 169 170 static void aspeed_board_init(MachineState *machine, 171 const AspeedBoardConfig *cfg) 172 { 173 AspeedBoardState *bmc; 174 AspeedSoCClass *sc; 175 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 176 ram_addr_t max_ram_size; 177 int i; 178 179 bmc = g_new0(AspeedBoardState, 1); 180 181 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 182 UINT32_MAX); 183 184 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 185 (sizeof(bmc->soc)), cfg->soc_name, &error_abort, 186 NULL); 187 188 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 189 190 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 191 &error_abort); 192 object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", 193 &error_abort); 194 object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2", 195 &error_abort); 196 object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", 197 &error_abort); 198 object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", 199 &error_abort); 200 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 201 "dram", &error_abort); 202 if (machine->kernel_filename) { 203 /* 204 * When booting with a -kernel command line there is no u-boot 205 * that runs to unlock the SCU. In this case set the default to 206 * be unlocked as the kernel expects 207 */ 208 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 209 "hw-prot-key", &error_abort); 210 } 211 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 212 &error_abort); 213 214 /* 215 * Allocate RAM after the memory controller has checked the size 216 * was valid. If not, a default value is used. 217 */ 218 ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", 219 &error_abort); 220 221 memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); 222 memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); 223 memory_region_add_subregion(get_system_memory(), 224 sc->memmap[ASPEED_SDRAM], 225 &bmc->ram_container); 226 227 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 228 &error_abort); 229 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 230 "max_ram", max_ram_size - ram_size); 231 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 232 233 aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); 234 aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); 235 236 /* Install first FMC flash content as a boot rom. */ 237 if (drive0) { 238 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 239 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 240 241 /* 242 * create a ROM region using the default mapping window size of 243 * the flash module. The window size is 64MB for the AST2400 244 * SoC and 128MB for the AST2500 SoC, which is twice as big as 245 * needed by the flash modules of the Aspeed machines. 246 */ 247 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 248 fl->size, &error_abort); 249 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 250 boot_rom); 251 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 252 } 253 254 aspeed_board_binfo.ram_size = ram_size; 255 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 256 aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; 257 258 if (cfg->i2c_init) { 259 cfg->i2c_init(bmc); 260 } 261 262 for (i = 0; i < ARRAY_SIZE(bmc->soc.sdhci.slots); i++) { 263 SDHCIState *sdhci = &bmc->soc.sdhci.slots[i]; 264 DriveInfo *dinfo = drive_get_next(IF_SD); 265 BlockBackend *blk; 266 DeviceState *card; 267 268 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 269 card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 270 TYPE_SD_CARD); 271 qdev_prop_set_drive(card, "drive", blk, &error_fatal); 272 object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); 273 } 274 275 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 276 } 277 278 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 279 { 280 AspeedSoCState *soc = &bmc->soc; 281 DeviceState *dev; 282 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 283 284 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 285 * enough to provide basic RTC features. Alarms will be missing */ 286 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 287 288 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 289 eeprom_buf); 290 291 /* add a TMP423 temperature sensor */ 292 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 293 "tmp423", 0x4c); 294 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 295 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 296 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 297 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 298 } 299 300 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 301 { 302 AspeedSoCState *soc = &bmc->soc; 303 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 304 305 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 306 eeprom_buf); 307 308 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 309 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 310 TYPE_TMP105, 0x4d); 311 312 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 313 * plugged on the I2C bus header */ 314 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 315 } 316 317 static void ast2600_evb_i2c_init(AspeedBoardState *bmc) 318 { 319 /* Start with some devices on our I2C busses */ 320 ast2500_evb_i2c_init(bmc); 321 } 322 323 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 324 { 325 AspeedSoCState *soc = &bmc->soc; 326 327 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 328 * good enough */ 329 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 330 } 331 332 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 333 { 334 AspeedSoCState *soc = &bmc->soc; 335 336 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 337 338 /* The swift board expects a TMP275 but a TMP105 is compatible */ 339 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 340 /* The swift board expects a pca9551 but a pca9552 is compatible */ 341 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 342 343 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 344 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 345 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 346 347 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 348 /* The swift board expects a pca9539 but a pca9552 is compatible */ 349 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 350 351 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 352 /* The swift board expects a pca9539 but a pca9552 is compatible */ 353 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 354 0x74); 355 356 /* The swift board expects a TMP275 but a TMP105 is compatible */ 357 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 358 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 359 } 360 361 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 362 { 363 AspeedSoCState *soc = &bmc->soc; 364 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 365 366 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 367 0x60); 368 369 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 370 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 371 372 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 373 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 374 0x4a); 375 376 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 377 * good enough */ 378 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 379 380 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 381 eeprom_buf); 382 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 383 0x60); 384 } 385 386 static void aspeed_machine_init(MachineState *machine) 387 { 388 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 389 390 aspeed_board_init(machine, amc->board); 391 } 392 393 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 394 { 395 MachineClass *mc = MACHINE_CLASS(oc); 396 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 397 const AspeedBoardConfig *board = data; 398 399 mc->desc = board->desc; 400 mc->init = aspeed_machine_init; 401 mc->max_cpus = ASPEED_CPUS_NUM; 402 mc->no_floppy = 1; 403 mc->no_cdrom = 1; 404 mc->no_parallel = 1; 405 if (board->ram) { 406 mc->default_ram_size = board->ram; 407 } 408 amc->board = board; 409 } 410 411 static const TypeInfo aspeed_machine_type = { 412 .name = TYPE_ASPEED_MACHINE, 413 .parent = TYPE_MACHINE, 414 .instance_size = sizeof(AspeedMachine), 415 .class_size = sizeof(AspeedMachineClass), 416 .abstract = true, 417 }; 418 419 static const AspeedBoardConfig aspeed_boards[] = { 420 { 421 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 422 .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", 423 .soc_name = "ast2400-a1", 424 .hw_strap1 = PALMETTO_BMC_HW_STRAP1, 425 .fmc_model = "n25q256a", 426 .spi_model = "mx25l25635e", 427 .num_cs = 1, 428 .i2c_init = palmetto_bmc_i2c_init, 429 .ram = 256 * MiB, 430 }, { 431 .name = MACHINE_TYPE_NAME("ast2500-evb"), 432 .desc = "Aspeed AST2500 EVB (ARM1176)", 433 .soc_name = "ast2500-a1", 434 .hw_strap1 = AST2500_EVB_HW_STRAP1, 435 .fmc_model = "w25q256", 436 .spi_model = "mx25l25635e", 437 .num_cs = 1, 438 .i2c_init = ast2500_evb_i2c_init, 439 .ram = 512 * MiB, 440 }, { 441 .name = MACHINE_TYPE_NAME("romulus-bmc"), 442 .desc = "OpenPOWER Romulus BMC (ARM1176)", 443 .soc_name = "ast2500-a1", 444 .hw_strap1 = ROMULUS_BMC_HW_STRAP1, 445 .fmc_model = "n25q256a", 446 .spi_model = "mx66l1g45g", 447 .num_cs = 2, 448 .i2c_init = romulus_bmc_i2c_init, 449 .ram = 512 * MiB, 450 }, { 451 .name = MACHINE_TYPE_NAME("swift-bmc"), 452 .desc = "OpenPOWER Swift BMC (ARM1176)", 453 .soc_name = "ast2500-a1", 454 .hw_strap1 = SWIFT_BMC_HW_STRAP1, 455 .fmc_model = "mx66l1g45g", 456 .spi_model = "mx66l1g45g", 457 .num_cs = 2, 458 .i2c_init = swift_bmc_i2c_init, 459 .ram = 512 * MiB, 460 }, { 461 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 462 .desc = "OpenPOWER Witherspoon BMC (ARM1176)", 463 .soc_name = "ast2500-a1", 464 .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, 465 .fmc_model = "mx25l25635e", 466 .spi_model = "mx66l1g45g", 467 .num_cs = 2, 468 .i2c_init = witherspoon_bmc_i2c_init, 469 .ram = 512 * MiB, 470 }, { 471 .name = MACHINE_TYPE_NAME("ast2600-evb"), 472 .desc = "Aspeed AST2600 EVB (Cortex A7)", 473 .soc_name = "ast2600-a0", 474 .hw_strap1 = AST2600_EVB_HW_STRAP1, 475 .hw_strap2 = AST2600_EVB_HW_STRAP2, 476 .fmc_model = "w25q512jv", 477 .spi_model = "mx66u51235f", 478 .num_cs = 1, 479 .i2c_init = ast2600_evb_i2c_init, 480 .ram = 1 * GiB, 481 }, 482 }; 483 484 static void aspeed_machine_types(void) 485 { 486 int i; 487 488 type_register_static(&aspeed_machine_type); 489 for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { 490 TypeInfo ti = { 491 .name = aspeed_boards[i].name, 492 .parent = TYPE_ASPEED_MACHINE, 493 .class_init = aspeed_machine_class_init, 494 .class_data = (void *)&aspeed_boards[i], 495 }; 496 type_register(&ti); 497 } 498 } 499 500 type_init(aspeed_machine_types) 501