1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion ram; 39 MemoryRegion max_ram; 40 }; 41 42 /* Palmetto hardware value: 0x120CE416 */ 43 #define PALMETTO_BMC_HW_STRAP1 ( \ 44 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 45 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 46 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 47 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 48 SCU_HW_STRAP_VGA_CLASS_CODE | \ 49 SCU_HW_STRAP_LPC_RESET_PIN | \ 50 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 51 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 52 SCU_HW_STRAP_SPI_WIDTH | \ 53 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 54 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 55 56 /* AST2500 evb hardware value: 0xF100C2E6 */ 57 #define AST2500_EVB_HW_STRAP1 (( \ 58 AST2500_HW_STRAP1_DEFAULTS | \ 59 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 60 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 61 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 62 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 63 SCU_HW_STRAP_MAC1_RGMII | \ 64 SCU_HW_STRAP_MAC0_RGMII) & \ 65 ~SCU_HW_STRAP_2ND_BOOT_WDT) 66 67 /* Romulus hardware value: 0xF10AD206 */ 68 #define ROMULUS_BMC_HW_STRAP1 ( \ 69 AST2500_HW_STRAP1_DEFAULTS | \ 70 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 71 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 72 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 73 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 74 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 75 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 76 77 /* Swift hardware value: 0xF11AD206 */ 78 #define SWIFT_BMC_HW_STRAP1 ( \ 79 AST2500_HW_STRAP1_DEFAULTS | \ 80 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 81 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 82 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 83 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 84 SCU_H_PLL_BYPASS_EN | \ 85 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 86 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 87 88 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 89 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 90 91 /* 92 * The max ram region is for firmwares that scan the address space 93 * with load/store to guess how much RAM the SoC has. 94 */ 95 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 96 { 97 return 0; 98 } 99 100 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 101 unsigned size) 102 { 103 /* Discard writes */ 104 } 105 106 static const MemoryRegionOps max_ram_ops = { 107 .read = max_ram_read, 108 .write = max_ram_write, 109 .endianness = DEVICE_NATIVE_ENDIAN, 110 }; 111 112 #define FIRMWARE_ADDR 0x0 113 114 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 115 Error **errp) 116 { 117 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 118 uint8_t *storage; 119 int64_t size; 120 121 /* The block backend size should have already been 'validated' by 122 * the creation of the m25p80 object. 123 */ 124 size = blk_getlength(blk); 125 if (size <= 0) { 126 error_setg(errp, "failed to get flash size"); 127 return; 128 } 129 130 if (rom_size > size) { 131 rom_size = size; 132 } 133 134 storage = g_new0(uint8_t, rom_size); 135 if (blk_pread(blk, 0, storage, rom_size) < 0) { 136 error_setg(errp, "failed to read the initial flash content"); 137 return; 138 } 139 140 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 141 g_free(storage); 142 } 143 144 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 145 Error **errp) 146 { 147 int i ; 148 149 for (i = 0; i < s->num_cs; ++i) { 150 AspeedSMCFlash *fl = &s->flashes[i]; 151 DriveInfo *dinfo = drive_get_next(IF_MTD); 152 qemu_irq cs_line; 153 154 fl->flash = ssi_create_slave_no_init(s->spi, flashtype); 155 if (dinfo) { 156 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 157 errp); 158 } 159 qdev_init_nofail(fl->flash); 160 161 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 162 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 163 } 164 } 165 166 static void aspeed_board_init(MachineState *machine, 167 const AspeedBoardConfig *cfg) 168 { 169 AspeedBoardState *bmc; 170 AspeedSoCClass *sc; 171 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 172 ram_addr_t max_ram_size; 173 174 bmc = g_new0(AspeedBoardState, 1); 175 176 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 177 UINT32_MAX); 178 179 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 180 (sizeof(bmc->soc)), cfg->soc_name, &error_abort, 181 NULL); 182 183 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 184 185 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 186 &error_abort); 187 object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", 188 &error_abort); 189 object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", 190 &error_abort); 191 object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", 192 &error_abort); 193 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 194 "dram", &error_abort); 195 if (machine->kernel_filename) { 196 /* 197 * When booting with a -kernel command line there is no u-boot 198 * that runs to unlock the SCU. In this case set the default to 199 * be unlocked as the kernel expects 200 */ 201 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 202 "hw-prot-key", &error_abort); 203 } 204 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 205 &error_abort); 206 207 /* 208 * Allocate RAM after the memory controller has checked the size 209 * was valid. If not, a default value is used. 210 */ 211 ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", 212 &error_abort); 213 214 memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); 215 memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); 216 memory_region_add_subregion(get_system_memory(), 217 sc->info->memmap[ASPEED_SDRAM], 218 &bmc->ram_container); 219 220 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 221 &error_abort); 222 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 223 "max_ram", max_ram_size - ram_size); 224 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 225 226 aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); 227 aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); 228 229 /* Install first FMC flash content as a boot rom. */ 230 if (drive0) { 231 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 232 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 233 234 /* 235 * create a ROM region using the default mapping window size of 236 * the flash module. The window size is 64MB for the AST2400 237 * SoC and 128MB for the AST2500 SoC, which is twice as big as 238 * needed by the flash modules of the Aspeed machines. 239 */ 240 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 241 fl->size, &error_abort); 242 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 243 boot_rom); 244 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 245 } 246 247 aspeed_board_binfo.ram_size = ram_size; 248 aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM]; 249 aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; 250 251 if (cfg->i2c_init) { 252 cfg->i2c_init(bmc); 253 } 254 255 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 256 } 257 258 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 259 { 260 AspeedSoCState *soc = &bmc->soc; 261 DeviceState *dev; 262 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 263 264 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 265 * enough to provide basic RTC features. Alarms will be missing */ 266 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 267 268 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 269 eeprom_buf); 270 271 /* add a TMP423 temperature sensor */ 272 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 273 "tmp423", 0x4c); 274 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 275 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 276 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 277 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 278 } 279 280 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 281 { 282 AspeedSoCState *soc = &bmc->soc; 283 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 284 285 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 286 eeprom_buf); 287 288 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 289 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 290 TYPE_TMP105, 0x4d); 291 292 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 293 * plugged on the I2C bus header */ 294 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 295 } 296 297 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 298 { 299 AspeedSoCState *soc = &bmc->soc; 300 301 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 302 * good enough */ 303 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 304 } 305 306 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 307 { 308 AspeedSoCState *soc = &bmc->soc; 309 310 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 311 312 /* The swift board expects a TMP275 but a TMP105 is compatible */ 313 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 314 /* The swift board expects a pca9551 but a pca9552 is compatible */ 315 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 316 317 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 318 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 319 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 320 321 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 322 /* The swift board expects a pca9539 but a pca9552 is compatible */ 323 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 324 325 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 326 /* The swift board expects a pca9539 but a pca9552 is compatible */ 327 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 328 0x74); 329 330 /* The swift board expects a TMP275 but a TMP105 is compatible */ 331 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 332 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 333 } 334 335 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 336 { 337 AspeedSoCState *soc = &bmc->soc; 338 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 339 340 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 341 0x60); 342 343 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 344 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 345 346 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 347 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 348 0x4a); 349 350 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 351 * good enough */ 352 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 353 354 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 355 eeprom_buf); 356 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 357 0x60); 358 } 359 360 static void aspeed_machine_init(MachineState *machine) 361 { 362 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 363 364 aspeed_board_init(machine, amc->board); 365 } 366 367 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 368 { 369 MachineClass *mc = MACHINE_CLASS(oc); 370 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 371 const AspeedBoardConfig *board = data; 372 373 mc->desc = board->desc; 374 mc->init = aspeed_machine_init; 375 mc->max_cpus = ASPEED_CPUS_NUM; 376 mc->no_sdcard = 1; 377 mc->no_floppy = 1; 378 mc->no_cdrom = 1; 379 mc->no_parallel = 1; 380 if (board->ram) { 381 mc->default_ram_size = board->ram; 382 } 383 amc->board = board; 384 } 385 386 static const TypeInfo aspeed_machine_type = { 387 .name = TYPE_ASPEED_MACHINE, 388 .parent = TYPE_MACHINE, 389 .instance_size = sizeof(AspeedMachine), 390 .class_size = sizeof(AspeedMachineClass), 391 .abstract = true, 392 }; 393 394 static const AspeedBoardConfig aspeed_boards[] = { 395 { 396 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 397 .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)", 398 .soc_name = "ast2400-a1", 399 .hw_strap1 = PALMETTO_BMC_HW_STRAP1, 400 .fmc_model = "n25q256a", 401 .spi_model = "mx25l25635e", 402 .num_cs = 1, 403 .i2c_init = palmetto_bmc_i2c_init, 404 .ram = 256 * MiB, 405 }, { 406 .name = MACHINE_TYPE_NAME("ast2500-evb"), 407 .desc = "Aspeed AST2500 EVB (ARM1176)", 408 .soc_name = "ast2500-a1", 409 .hw_strap1 = AST2500_EVB_HW_STRAP1, 410 .fmc_model = "w25q256", 411 .spi_model = "mx25l25635e", 412 .num_cs = 1, 413 .i2c_init = ast2500_evb_i2c_init, 414 .ram = 512 * MiB, 415 }, { 416 .name = MACHINE_TYPE_NAME("romulus-bmc"), 417 .desc = "OpenPOWER Romulus BMC (ARM1176)", 418 .soc_name = "ast2500-a1", 419 .hw_strap1 = ROMULUS_BMC_HW_STRAP1, 420 .fmc_model = "n25q256a", 421 .spi_model = "mx66l1g45g", 422 .num_cs = 2, 423 .i2c_init = romulus_bmc_i2c_init, 424 .ram = 512 * MiB, 425 }, { 426 .name = MACHINE_TYPE_NAME("swift-bmc"), 427 .desc = "OpenPOWER Swift BMC (ARM1176)", 428 .soc_name = "ast2500-a1", 429 .hw_strap1 = SWIFT_BMC_HW_STRAP1, 430 .fmc_model = "mx66l1g45g", 431 .spi_model = "mx66l1g45g", 432 .num_cs = 2, 433 .i2c_init = swift_bmc_i2c_init, 434 .ram = 512 * MiB, 435 }, { 436 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 437 .desc = "OpenPOWER Witherspoon BMC (ARM1176)", 438 .soc_name = "ast2500-a1", 439 .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1, 440 .fmc_model = "mx25l25635e", 441 .spi_model = "mx66l1g45g", 442 .num_cs = 2, 443 .i2c_init = witherspoon_bmc_i2c_init, 444 .ram = 512 * MiB, 445 }, 446 }; 447 448 static void aspeed_machine_types(void) 449 { 450 int i; 451 452 type_register_static(&aspeed_machine_type); 453 for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) { 454 TypeInfo ti = { 455 .name = aspeed_boards[i].name, 456 .parent = TYPE_ASPEED_MACHINE, 457 .class_init = aspeed_machine_class_init, 458 .class_data = (void *)&aspeed_boards[i], 459 }; 460 type_register(&ti); 461 } 462 } 463 464 type_init(aspeed_machine_types) 465