1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 }; 50 51 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 52 #if HOST_LONG_BITS == 32 53 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 54 #else 55 #define ASPEED_RAM_SIZE(sz) (sz) 56 #endif 57 58 /* Palmetto hardware value: 0x120CE416 */ 59 #define PALMETTO_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* TODO: Find the actual hardware value */ 73 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 74 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 75 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 76 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 77 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 78 SCU_HW_STRAP_VGA_CLASS_CODE | \ 79 SCU_HW_STRAP_LPC_RESET_PIN | \ 80 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 81 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 82 SCU_HW_STRAP_SPI_WIDTH | \ 83 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 84 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 85 86 /* TODO: Find the actual hardware value */ 87 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_HW_STRAP_SPI_WIDTH | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 95 96 /* AST2500 evb hardware value: 0xF100C2E6 */ 97 #define AST2500_EVB_HW_STRAP1 (( \ 98 AST2500_HW_STRAP1_DEFAULTS | \ 99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 101 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_MAC1_RGMII | \ 104 SCU_HW_STRAP_MAC0_RGMII) & \ 105 ~SCU_HW_STRAP_2ND_BOOT_WDT) 106 107 /* Romulus hardware value: 0xF10AD206 */ 108 #define ROMULUS_BMC_HW_STRAP1 ( \ 109 AST2500_HW_STRAP1_DEFAULTS | \ 110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 112 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 114 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 115 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 116 117 /* Sonorapass hardware value: 0xF100D216 */ 118 #define SONORAPASS_BMC_HW_STRAP1 ( \ 119 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 120 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 121 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 122 SCU_AST2500_HW_STRAP_RESERVED28 | \ 123 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 124 SCU_HW_STRAP_VGA_CLASS_CODE | \ 125 SCU_HW_STRAP_LPC_RESET_PIN | \ 126 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 127 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 128 SCU_HW_STRAP_VGA_BIOS_ROM | \ 129 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 130 SCU_AST2500_HW_STRAP_RESERVED1) 131 132 #define G220A_BMC_HW_STRAP1 ( \ 133 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 134 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 135 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 136 SCU_AST2500_HW_STRAP_RESERVED28 | \ 137 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 138 SCU_HW_STRAP_2ND_BOOT_WDT | \ 139 SCU_HW_STRAP_VGA_CLASS_CODE | \ 140 SCU_HW_STRAP_LPC_RESET_PIN | \ 141 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 142 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 143 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 144 SCU_AST2500_HW_STRAP_RESERVED1) 145 146 /* FP5280G2 hardware value: 0XF100D286 */ 147 #define FP5280G2_BMC_HW_STRAP1 ( \ 148 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 149 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 150 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 151 SCU_AST2500_HW_STRAP_RESERVED28 | \ 152 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 153 SCU_HW_STRAP_VGA_CLASS_CODE | \ 154 SCU_HW_STRAP_LPC_RESET_PIN | \ 155 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 156 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 157 SCU_HW_STRAP_MAC1_RGMII | \ 158 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 159 SCU_AST2500_HW_STRAP_RESERVED1) 160 161 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 162 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 163 164 /* Quanta-Q71l hardware value */ 165 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 166 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 167 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 168 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 169 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 170 SCU_HW_STRAP_VGA_CLASS_CODE | \ 171 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 172 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 173 SCU_HW_STRAP_SPI_WIDTH | \ 174 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 175 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 176 177 /* AST2600 evb hardware value */ 178 #define AST2600_EVB_HW_STRAP1 0x000000C0 179 #define AST2600_EVB_HW_STRAP2 0x00000003 180 181 #ifdef TARGET_AARCH64 182 /* AST2700 evb hardware value */ 183 #define AST2700_EVB_HW_STRAP1 0x000000C0 184 #define AST2700_EVB_HW_STRAP2 0x00000003 185 #endif 186 187 /* Tacoma hardware value */ 188 #define TACOMA_BMC_HW_STRAP1 0x00000000 189 #define TACOMA_BMC_HW_STRAP2 0x00000040 190 191 /* Rainier hardware value: (QEMU prototype) */ 192 #define RAINIER_BMC_HW_STRAP1 0x00422016 193 #define RAINIER_BMC_HW_STRAP2 0x80000848 194 195 /* Fuji hardware value */ 196 #define FUJI_BMC_HW_STRAP1 0x00000000 197 #define FUJI_BMC_HW_STRAP2 0x00000000 198 199 /* Bletchley hardware value */ 200 /* TODO: Leave same as EVB for now. */ 201 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 202 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 203 204 /* Qualcomm DC-SCM hardware value */ 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 207 208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 215 216 static void aspeed_write_smpboot(ARMCPU *cpu, 217 const struct arm_boot_info *info) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 static const ARMInsnFixup poll_mailbox_ready[] = { 221 /* 222 * r2 = per-cpu go sign value 223 * r1 = AST_SMP_MBOX_FIELD_ENTRY 224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 225 */ 226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 227 { 0xe21000ff }, /* ands r0, r0, #255 */ 228 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 229 { 0xe1822000 }, /* orr r2, r2, r0 */ 230 231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 233 234 { 0xe320f002 }, /* wfe */ 235 { 0xe5904000 }, /* ldr r4, [r0] */ 236 { 0xe1520004 }, /* cmp r2, r4 */ 237 { 0x1afffffb }, /* bne <wfe> */ 238 { 0xe591f000 }, /* ldr pc, [r1] */ 239 { AST_SMP_MBOX_GOSIGN }, 240 { AST_SMP_MBOX_FIELD_ENTRY }, 241 { AST_SMP_MBOX_FIELD_GOSIGN }, 242 { 0, FIXUP_TERMINATOR } 243 }; 244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 245 246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 247 poll_mailbox_ready, fixupcontext); 248 } 249 250 static void aspeed_reset_secondary(ARMCPU *cpu, 251 const struct arm_boot_info *info) 252 { 253 AddressSpace *as = arm_boot_address_space(cpu, info); 254 CPUState *cs = CPU(cpu); 255 256 /* info->smp_bootreg_addr */ 257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 258 MEMTXATTRS_UNSPECIFIED, NULL); 259 cpu_set_pc(cs, info->smp_loader_start); 260 } 261 262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 263 Error **errp) 264 { 265 g_autofree void *storage = NULL; 266 int64_t size; 267 268 /* The block backend size should have already been 'validated' by 269 * the creation of the m25p80 object. 270 */ 271 size = blk_getlength(blk); 272 if (size <= 0) { 273 error_setg(errp, "failed to get flash size"); 274 return; 275 } 276 277 if (rom_size > size) { 278 rom_size = size; 279 } 280 281 storage = g_malloc0(rom_size); 282 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 283 error_setg(errp, "failed to read the initial flash content"); 284 return; 285 } 286 287 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 288 } 289 290 /* 291 * Create a ROM and copy the flash contents at the expected address 292 * (0x0). Boots faster than execute-in-place. 293 */ 294 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 295 uint64_t rom_size) 296 { 297 AspeedSoCState *soc = bmc->soc; 298 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 299 300 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 301 &error_abort); 302 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 303 &bmc->boot_rom, 1); 304 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 305 rom_size, &error_abort); 306 } 307 308 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 309 unsigned int count, int unit0) 310 { 311 int i; 312 313 if (!flashtype) { 314 return; 315 } 316 317 for (i = 0; i < count; ++i) { 318 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 319 DeviceState *dev; 320 321 dev = qdev_new(flashtype); 322 if (dinfo) { 323 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 324 } 325 qdev_prop_set_uint8(dev, "cs", i); 326 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 327 } 328 } 329 330 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 331 { 332 DeviceState *card; 333 334 if (!dinfo) { 335 return; 336 } 337 card = qdev_new(TYPE_SD_CARD); 338 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 339 &error_fatal); 340 qdev_realize_and_unref(card, 341 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 342 &error_fatal); 343 } 344 345 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 346 { 347 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 348 AspeedSoCState *s = bmc->soc; 349 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 350 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 351 352 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 353 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 354 if (uart == uart_chosen) { 355 continue; 356 } 357 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 358 } 359 } 360 361 static void aspeed_machine_init(MachineState *machine) 362 { 363 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 364 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 365 AspeedSoCClass *sc; 366 int i; 367 368 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 369 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 370 object_unref(OBJECT(bmc->soc)); 371 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 372 373 /* 374 * This will error out if the RAM size is not supported by the 375 * memory controller of the SoC. 376 */ 377 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 378 &error_fatal); 379 380 for (i = 0; i < sc->macs_num; i++) { 381 if ((amc->macs_mask & (1 << i)) && 382 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 383 true, NULL)) { 384 break; /* No configs left; stop asking */ 385 } 386 } 387 388 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1, 389 &error_abort); 390 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 391 &error_abort); 392 object_property_set_link(OBJECT(bmc->soc), "memory", 393 OBJECT(get_system_memory()), &error_abort); 394 object_property_set_link(OBJECT(bmc->soc), "dram", 395 OBJECT(machine->ram), &error_abort); 396 if (machine->kernel_filename) { 397 /* 398 * When booting with a -kernel command line there is no u-boot 399 * that runs to unlock the SCU. In this case set the default to 400 * be unlocked as the kernel expects 401 */ 402 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 403 ASPEED_SCU_PROT_KEY, &error_abort); 404 } 405 connect_serial_hds_to_uarts(bmc); 406 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 407 408 if (defaults_enabled()) { 409 aspeed_board_init_flashes(&bmc->soc->fmc, 410 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 411 amc->num_cs, 0); 412 aspeed_board_init_flashes(&bmc->soc->spi[0], 413 bmc->spi_model ? bmc->spi_model : amc->spi_model, 414 1, amc->num_cs); 415 } 416 417 if (machine->kernel_filename && sc->num_cpus > 1) { 418 /* With no u-boot we must set up a boot stub for the secondary CPU */ 419 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 420 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 421 0x80, &error_abort); 422 memory_region_add_subregion(get_system_memory(), 423 AST_SMP_MAILBOX_BASE, smpboot); 424 425 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 426 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 427 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 428 } 429 430 aspeed_board_binfo.ram_size = machine->ram_size; 431 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 432 433 if (amc->i2c_init) { 434 amc->i2c_init(bmc); 435 } 436 437 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 438 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 439 drive_get(IF_SD, 0, i)); 440 } 441 442 if (bmc->soc->emmc.num_slots) { 443 sdhci_attach_drive(&bmc->soc->emmc.slots[0], 444 drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots)); 445 } 446 447 if (!bmc->mmio_exec) { 448 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 449 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 450 451 if (fmc0) { 452 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 453 aspeed_install_boot_rom(bmc, fmc0, rom_size); 454 } 455 } 456 457 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 458 } 459 460 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 461 { 462 AspeedSoCState *soc = bmc->soc; 463 DeviceState *dev; 464 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 465 466 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 467 * enough to provide basic RTC features. Alarms will be missing */ 468 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 469 470 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 471 eeprom_buf); 472 473 /* add a TMP423 temperature sensor */ 474 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 475 "tmp423", 0x4c)); 476 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 477 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 478 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 479 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 480 } 481 482 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 483 { 484 AspeedSoCState *soc = bmc->soc; 485 486 /* 487 * The quanta-q71l platform expects tmp75s which are compatible with 488 * tmp105s. 489 */ 490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 491 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 492 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 493 494 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 495 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 496 /* TODO: Add Memory Riser i2c mux and eeproms. */ 497 498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 500 501 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 502 503 /* i2c-7 */ 504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 505 /* - i2c@0: pmbus@59 */ 506 /* - i2c@1: pmbus@58 */ 507 /* - i2c@2: pmbus@58 */ 508 /* - i2c@3: pmbus@59 */ 509 510 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 511 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 512 } 513 514 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 515 { 516 AspeedSoCState *soc = bmc->soc; 517 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 518 519 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 520 eeprom_buf); 521 522 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 524 TYPE_TMP105, 0x4d); 525 } 526 527 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 528 { 529 AspeedSoCState *soc = bmc->soc; 530 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 531 532 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 533 eeprom_buf); 534 535 /* LM75 is compatible with TMP105 driver */ 536 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 537 TYPE_TMP105, 0x4d); 538 } 539 540 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 541 { 542 AspeedSoCState *soc = bmc->soc; 543 544 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 545 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 546 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 547 /* TMP421 */ 548 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 549 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 550 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 551 552 } 553 554 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 555 { 556 AspeedSoCState *soc = bmc->soc; 557 558 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 559 * good enough */ 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 561 } 562 563 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 564 { 565 AspeedSoCState *soc = bmc->soc; 566 567 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 568 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 569 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 570 /* TMP421 */ 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 573 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 574 } 575 576 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 577 { 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 579 TYPE_PCA9552, addr); 580 } 581 582 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 583 { 584 AspeedSoCState *soc = bmc->soc; 585 586 /* bus 2 : */ 587 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 588 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 589 /* bus 2 : pca9546 @ 0x73 */ 590 591 /* bus 3 : pca9548 @ 0x70 */ 592 593 /* bus 4 : */ 594 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 595 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 596 eeprom4_54); 597 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 598 create_pca9552(soc, 4, 0x76); 599 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 600 create_pca9552(soc, 4, 0x77); 601 602 /* bus 6 : */ 603 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 604 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 605 /* bus 6 : pca9546 @ 0x73 */ 606 607 /* bus 8 : */ 608 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 609 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 610 eeprom8_56); 611 create_pca9552(soc, 8, 0x60); 612 create_pca9552(soc, 8, 0x61); 613 /* bus 8 : adc128d818 @ 0x1d */ 614 /* bus 8 : adc128d818 @ 0x1f */ 615 616 /* 617 * bus 13 : pca9548 @ 0x71 618 * - channel 3: 619 * - tmm421 @ 0x4c 620 * - tmp421 @ 0x4e 621 * - tmp421 @ 0x4f 622 */ 623 624 } 625 626 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 627 { 628 static const struct { 629 unsigned gpio_id; 630 LEDColor color; 631 const char *description; 632 bool gpio_polarity; 633 } pca1_leds[] = { 634 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 635 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 636 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 637 }; 638 AspeedSoCState *soc = bmc->soc; 639 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 640 DeviceState *dev; 641 LEDState *led; 642 643 /* Bus 3: TODO bmp280@77 */ 644 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 645 qdev_prop_set_string(dev, "description", "pca1"); 646 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 647 aspeed_i2c_get_bus(&soc->i2c, 3), 648 &error_fatal); 649 650 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 651 led = led_create_simple(OBJECT(bmc), 652 pca1_leds[i].gpio_polarity, 653 pca1_leds[i].color, 654 pca1_leds[i].description); 655 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 656 qdev_get_gpio_in(DEVICE(led), 0)); 657 } 658 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 659 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 660 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 661 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 662 663 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 664 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 665 0x4a); 666 667 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 668 * good enough */ 669 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 670 671 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 672 eeprom_buf); 673 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 674 qdev_prop_set_string(dev, "description", "pca0"); 675 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 676 aspeed_i2c_get_bus(&soc->i2c, 11), 677 &error_fatal); 678 /* Bus 11: TODO ucd90160@64 */ 679 } 680 681 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 682 { 683 AspeedSoCState *soc = bmc->soc; 684 DeviceState *dev; 685 686 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 687 "emc1413", 0x4c)); 688 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 689 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 690 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 691 692 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 693 "emc1413", 0x4c)); 694 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 695 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 696 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 697 698 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 699 "emc1413", 0x4c)); 700 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 701 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 702 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 703 704 static uint8_t eeprom_buf[2 * 1024] = { 705 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 706 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 707 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 708 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 709 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 710 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 711 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 712 }; 713 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 714 eeprom_buf); 715 } 716 717 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 718 { 719 AspeedSoCState *soc = bmc->soc; 720 I2CSlave *i2c_mux; 721 722 /* The at24c256 */ 723 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 724 725 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 727 0x48); 728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 729 0x49); 730 731 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 732 "pca9546", 0x70); 733 /* It expects a TMP112 but a TMP105 is compatible */ 734 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 735 0x4a); 736 737 /* It expects a ds3232 but a ds1338 is good enough */ 738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 739 740 /* It expects a pca9555 but a pca9552 is compatible */ 741 create_pca9552(soc, 8, 0x30); 742 } 743 744 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 745 { 746 AspeedSoCState *soc = bmc->soc; 747 I2CSlave *i2c_mux; 748 749 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 750 751 create_pca9552(soc, 3, 0x61); 752 753 /* The rainier expects a TMP275 but a TMP105 is compatible */ 754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 755 0x48); 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 757 0x49); 758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 759 0x4a); 760 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 761 "pca9546", 0x70); 762 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 763 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 764 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 765 create_pca9552(soc, 4, 0x60); 766 767 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 768 0x48); 769 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 770 0x49); 771 create_pca9552(soc, 5, 0x60); 772 create_pca9552(soc, 5, 0x61); 773 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 774 "pca9546", 0x70); 775 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 776 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 777 778 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 779 0x48); 780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 781 0x4a); 782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 783 0x4b); 784 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 785 "pca9546", 0x70); 786 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 787 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 788 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 789 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 790 791 create_pca9552(soc, 7, 0x30); 792 create_pca9552(soc, 7, 0x31); 793 create_pca9552(soc, 7, 0x32); 794 create_pca9552(soc, 7, 0x33); 795 create_pca9552(soc, 7, 0x60); 796 create_pca9552(soc, 7, 0x61); 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 798 /* Bus 7: TODO si7021-a20@20 */ 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 800 0x48); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 802 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 803 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 804 805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 806 0x48); 807 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 808 0x4a); 809 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 810 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 811 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 812 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 813 create_pca9552(soc, 8, 0x60); 814 create_pca9552(soc, 8, 0x61); 815 /* Bus 8: ucd90320@11 */ 816 /* Bus 8: ucd90320@b */ 817 /* Bus 8: ucd90320@c */ 818 819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 820 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 821 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 822 823 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 824 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 825 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 826 827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 828 0x48); 829 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 830 0x49); 831 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 832 "pca9546", 0x70); 833 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 834 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 835 create_pca9552(soc, 11, 0x60); 836 837 838 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 839 create_pca9552(soc, 13, 0x60); 840 841 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 842 create_pca9552(soc, 14, 0x60); 843 844 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 845 create_pca9552(soc, 15, 0x60); 846 } 847 848 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 849 I2CBus **channels) 850 { 851 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 852 for (int i = 0; i < 8; i++) { 853 channels[i] = pca954x_i2c_get_bus(mux, i); 854 } 855 } 856 857 #define TYPE_LM75 TYPE_TMP105 858 #define TYPE_TMP75 TYPE_TMP105 859 #define TYPE_TMP422 "tmp422" 860 861 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 862 { 863 AspeedSoCState *soc = bmc->soc; 864 I2CBus *i2c[144] = {}; 865 866 for (int i = 0; i < 16; i++) { 867 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 868 } 869 I2CBus *i2c180 = i2c[2]; 870 I2CBus *i2c480 = i2c[8]; 871 I2CBus *i2c600 = i2c[11]; 872 873 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 874 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 875 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 876 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 877 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 878 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 879 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 880 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 881 for (int i = 0; i < 8; i++) { 882 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 883 } 884 885 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 886 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 887 888 /* 889 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 890 * 24c02 size is 2Kbits or 256 bytes 891 */ 892 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 893 at24c_eeprom_init(i2c[20], 0x50, 256); 894 at24c_eeprom_init(i2c[22], 0x52, 256); 895 896 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 897 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 898 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 899 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 900 901 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 902 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 903 904 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 905 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 906 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 907 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 908 909 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 910 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 911 912 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 913 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 914 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 915 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 916 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 917 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 918 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 919 920 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 921 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 922 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 923 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 924 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 925 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 926 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 927 at24c_eeprom_init(i2c[28], 0x50, 256); 928 929 for (int i = 0; i < 8; i++) { 930 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 931 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 932 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 933 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 934 } 935 } 936 937 #define TYPE_TMP421 "tmp421" 938 939 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 940 { 941 AspeedSoCState *soc = bmc->soc; 942 I2CBus *i2c[13] = {}; 943 for (int i = 0; i < 13; i++) { 944 if ((i == 8) || (i == 11)) { 945 continue; 946 } 947 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 948 } 949 950 /* Bus 0 - 5 all have the same config. */ 951 for (int i = 0; i < 6; i++) { 952 /* Missing model: ti,ina230 @ 0x45 */ 953 /* Missing model: mps,mp5023 @ 0x40 */ 954 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 955 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 956 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 957 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 958 /* Missing model: fsc,fusb302 @ 0x22 */ 959 } 960 961 /* Bus 6 */ 962 at24c_eeprom_init(i2c[6], 0x56, 65536); 963 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 964 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 965 966 967 /* Bus 7 */ 968 at24c_eeprom_init(i2c[7], 0x54, 65536); 969 970 /* Bus 9 */ 971 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 972 973 /* Bus 10 */ 974 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 975 /* Missing model: ti,hdc1080 @ 0x40 */ 976 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 977 978 /* Bus 12 */ 979 /* Missing model: adi,adm1278 @ 0x11 */ 980 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 981 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 982 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 983 } 984 985 static void fby35_i2c_init(AspeedMachineState *bmc) 986 { 987 AspeedSoCState *soc = bmc->soc; 988 I2CBus *i2c[16]; 989 990 for (int i = 0; i < 16; i++) { 991 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 992 } 993 994 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 995 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 996 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 997 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 998 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 999 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1000 1001 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1002 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1003 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1004 fby35_nic_fruid_len); 1005 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1006 fby35_bb_fruid_len); 1007 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1008 fby35_bmc_fruid_len); 1009 1010 /* 1011 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1012 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1013 * each. 1014 */ 1015 } 1016 1017 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1018 { 1019 AspeedSoCState *soc = bmc->soc; 1020 1021 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1022 } 1023 1024 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1025 { 1026 AspeedSoCState *soc = bmc->soc; 1027 I2CSlave *therm_mux, *cpuvr_mux; 1028 1029 /* Create the generic DC-SCM hardware */ 1030 qcom_dc_scm_bmc_i2c_init(bmc); 1031 1032 /* Now create the Firework specific hardware */ 1033 1034 /* I2C7 CPUVR MUX */ 1035 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1036 "pca9546", 0x70); 1037 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1038 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1039 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1040 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1041 1042 /* I2C8 Thermal Diodes*/ 1043 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1044 "pca9548", 0x70); 1045 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1046 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1047 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1048 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1049 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1050 1051 /* I2C9 Fan Controller (MAX31785) */ 1052 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1053 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1054 } 1055 1056 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1057 { 1058 return ASPEED_MACHINE(obj)->mmio_exec; 1059 } 1060 1061 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1062 { 1063 ASPEED_MACHINE(obj)->mmio_exec = value; 1064 } 1065 1066 static void aspeed_machine_instance_init(Object *obj) 1067 { 1068 ASPEED_MACHINE(obj)->mmio_exec = false; 1069 } 1070 1071 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1072 { 1073 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1074 return g_strdup(bmc->fmc_model); 1075 } 1076 1077 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1078 { 1079 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1080 1081 g_free(bmc->fmc_model); 1082 bmc->fmc_model = g_strdup(value); 1083 } 1084 1085 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1086 { 1087 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1088 return g_strdup(bmc->spi_model); 1089 } 1090 1091 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1092 { 1093 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1094 1095 g_free(bmc->spi_model); 1096 bmc->spi_model = g_strdup(value); 1097 } 1098 1099 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1100 { 1101 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1102 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1103 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1104 1105 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1106 } 1107 1108 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1109 { 1110 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1111 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1112 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1113 int val; 1114 int uart_first = aspeed_uart_first(sc); 1115 int uart_last = aspeed_uart_last(sc); 1116 1117 if (sscanf(value, "uart%u", &val) != 1) { 1118 error_setg(errp, "Bad value for \"uart\" property"); 1119 return; 1120 } 1121 1122 /* The number of UART depends on the SoC */ 1123 if (val < uart_first || val > uart_last) { 1124 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1125 uart_first, uart_last); 1126 return; 1127 } 1128 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1129 } 1130 1131 static void aspeed_machine_class_props_init(ObjectClass *oc) 1132 { 1133 object_class_property_add_bool(oc, "execute-in-place", 1134 aspeed_get_mmio_exec, 1135 aspeed_set_mmio_exec); 1136 object_class_property_set_description(oc, "execute-in-place", 1137 "boot directly from CE0 flash device"); 1138 1139 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1140 aspeed_set_bmc_console); 1141 object_class_property_set_description(oc, "bmc-console", 1142 "Change the default UART to \"uartX\""); 1143 1144 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1145 aspeed_set_fmc_model); 1146 object_class_property_set_description(oc, "fmc-model", 1147 "Change the FMC Flash model"); 1148 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1149 aspeed_set_spi_model); 1150 object_class_property_set_description(oc, "spi-model", 1151 "Change the SPI Flash model"); 1152 } 1153 1154 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1155 { 1156 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1157 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1158 1159 mc->default_cpus = sc->num_cpus; 1160 mc->min_cpus = sc->num_cpus; 1161 mc->max_cpus = sc->num_cpus; 1162 mc->valid_cpu_types = sc->valid_cpu_types; 1163 } 1164 1165 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1166 { 1167 MachineClass *mc = MACHINE_CLASS(oc); 1168 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1169 1170 mc->init = aspeed_machine_init; 1171 mc->no_floppy = 1; 1172 mc->no_cdrom = 1; 1173 mc->no_parallel = 1; 1174 mc->default_ram_id = "ram"; 1175 amc->macs_mask = ASPEED_MAC0_ON; 1176 amc->uart_default = ASPEED_DEV_UART5; 1177 1178 aspeed_machine_class_props_init(oc); 1179 } 1180 1181 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1182 { 1183 MachineClass *mc = MACHINE_CLASS(oc); 1184 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1185 1186 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1187 amc->soc_name = "ast2400-a1"; 1188 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1189 amc->fmc_model = "n25q256a"; 1190 amc->spi_model = "mx25l25635f"; 1191 amc->num_cs = 1; 1192 amc->i2c_init = palmetto_bmc_i2c_init; 1193 mc->default_ram_size = 256 * MiB; 1194 aspeed_machine_class_init_cpus_defaults(mc); 1195 }; 1196 1197 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1198 { 1199 MachineClass *mc = MACHINE_CLASS(oc); 1200 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1201 1202 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1203 amc->soc_name = "ast2400-a1"; 1204 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1205 amc->fmc_model = "n25q256a"; 1206 amc->spi_model = "mx25l25635e"; 1207 amc->num_cs = 1; 1208 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1209 mc->default_ram_size = 128 * MiB; 1210 aspeed_machine_class_init_cpus_defaults(mc); 1211 } 1212 1213 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1214 void *data) 1215 { 1216 MachineClass *mc = MACHINE_CLASS(oc); 1217 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1218 1219 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1220 amc->soc_name = "ast2400-a1"; 1221 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1222 amc->fmc_model = "mx25l25635e"; 1223 amc->spi_model = "mx25l25635e"; 1224 amc->num_cs = 1; 1225 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1226 amc->i2c_init = palmetto_bmc_i2c_init; 1227 mc->default_ram_size = 256 * MiB; 1228 aspeed_machine_class_init_cpus_defaults(mc); 1229 } 1230 1231 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1232 void *data) 1233 { 1234 MachineClass *mc = MACHINE_CLASS(oc); 1235 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1236 1237 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1238 amc->soc_name = "ast2500-a1"; 1239 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1240 amc->fmc_model = "mx25l25635e"; 1241 amc->spi_model = "mx25l25635e"; 1242 amc->num_cs = 1; 1243 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1244 amc->i2c_init = palmetto_bmc_i2c_init; 1245 mc->default_ram_size = 512 * MiB; 1246 aspeed_machine_class_init_cpus_defaults(mc); 1247 } 1248 1249 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1250 { 1251 MachineClass *mc = MACHINE_CLASS(oc); 1252 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1253 1254 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1255 amc->soc_name = "ast2500-a1"; 1256 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1257 amc->fmc_model = "mx25l25635e"; 1258 amc->spi_model = "mx25l25635f"; 1259 amc->num_cs = 1; 1260 amc->i2c_init = ast2500_evb_i2c_init; 1261 mc->default_ram_size = 512 * MiB; 1262 aspeed_machine_class_init_cpus_defaults(mc); 1263 }; 1264 1265 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1266 { 1267 MachineClass *mc = MACHINE_CLASS(oc); 1268 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1269 1270 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1271 amc->soc_name = "ast2500-a1"; 1272 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1273 amc->hw_strap2 = 0; 1274 amc->fmc_model = "n25q256a"; 1275 amc->spi_model = "mx25l25635e"; 1276 amc->num_cs = 2; 1277 amc->i2c_init = yosemitev2_bmc_i2c_init; 1278 mc->default_ram_size = 512 * MiB; 1279 aspeed_machine_class_init_cpus_defaults(mc); 1280 }; 1281 1282 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1283 { 1284 MachineClass *mc = MACHINE_CLASS(oc); 1285 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1286 1287 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1288 amc->soc_name = "ast2500-a1"; 1289 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1290 amc->fmc_model = "n25q256a"; 1291 amc->spi_model = "mx66l1g45g"; 1292 amc->num_cs = 2; 1293 amc->i2c_init = romulus_bmc_i2c_init; 1294 mc->default_ram_size = 512 * MiB; 1295 aspeed_machine_class_init_cpus_defaults(mc); 1296 }; 1297 1298 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1299 { 1300 MachineClass *mc = MACHINE_CLASS(oc); 1301 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1302 1303 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1304 amc->soc_name = "ast2500-a1"; 1305 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1306 amc->hw_strap2 = 0; 1307 amc->fmc_model = "n25q256a"; 1308 amc->spi_model = "mx25l25635e"; 1309 amc->num_cs = 2; 1310 amc->i2c_init = tiogapass_bmc_i2c_init; 1311 mc->default_ram_size = 1 * GiB; 1312 aspeed_machine_class_init_cpus_defaults(mc); 1313 }; 1314 1315 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1316 { 1317 MachineClass *mc = MACHINE_CLASS(oc); 1318 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1319 1320 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1321 amc->soc_name = "ast2500-a1"; 1322 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1323 amc->fmc_model = "mx66l1g45g"; 1324 amc->spi_model = "mx66l1g45g"; 1325 amc->num_cs = 2; 1326 amc->i2c_init = sonorapass_bmc_i2c_init; 1327 mc->default_ram_size = 512 * MiB; 1328 aspeed_machine_class_init_cpus_defaults(mc); 1329 }; 1330 1331 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1332 { 1333 MachineClass *mc = MACHINE_CLASS(oc); 1334 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1335 1336 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1337 amc->soc_name = "ast2500-a1"; 1338 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1339 amc->fmc_model = "mx25l25635f"; 1340 amc->spi_model = "mx66l1g45g"; 1341 amc->num_cs = 2; 1342 amc->i2c_init = witherspoon_bmc_i2c_init; 1343 mc->default_ram_size = 512 * MiB; 1344 aspeed_machine_class_init_cpus_defaults(mc); 1345 }; 1346 1347 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1348 { 1349 MachineClass *mc = MACHINE_CLASS(oc); 1350 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1351 1352 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1353 amc->soc_name = "ast2600-a3"; 1354 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1355 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1356 amc->fmc_model = "mx66u51235f"; 1357 amc->spi_model = "mx66u51235f"; 1358 amc->num_cs = 1; 1359 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1360 ASPEED_MAC3_ON; 1361 amc->i2c_init = ast2600_evb_i2c_init; 1362 mc->default_ram_size = 1 * GiB; 1363 aspeed_machine_class_init_cpus_defaults(mc); 1364 }; 1365 1366 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1367 { 1368 MachineClass *mc = MACHINE_CLASS(oc); 1369 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1370 1371 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1372 amc->soc_name = "ast2600-a3"; 1373 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1374 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1375 amc->fmc_model = "mx66l1g45g"; 1376 amc->spi_model = "mx66l1g45g"; 1377 amc->num_cs = 2; 1378 amc->macs_mask = ASPEED_MAC2_ON; 1379 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1380 mc->default_ram_size = 1 * GiB; 1381 aspeed_machine_class_init_cpus_defaults(mc); 1382 }; 1383 1384 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1385 { 1386 MachineClass *mc = MACHINE_CLASS(oc); 1387 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1388 1389 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1390 amc->soc_name = "ast2500-a1"; 1391 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1392 amc->fmc_model = "n25q512a"; 1393 amc->spi_model = "mx25l25635e"; 1394 amc->num_cs = 2; 1395 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1396 amc->i2c_init = g220a_bmc_i2c_init; 1397 mc->default_ram_size = 1024 * MiB; 1398 aspeed_machine_class_init_cpus_defaults(mc); 1399 }; 1400 1401 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1402 { 1403 MachineClass *mc = MACHINE_CLASS(oc); 1404 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1405 1406 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1407 amc->soc_name = "ast2500-a1"; 1408 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1409 amc->fmc_model = "n25q512a"; 1410 amc->spi_model = "mx25l25635e"; 1411 amc->num_cs = 2; 1412 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1413 amc->i2c_init = fp5280g2_bmc_i2c_init; 1414 mc->default_ram_size = 512 * MiB; 1415 aspeed_machine_class_init_cpus_defaults(mc); 1416 }; 1417 1418 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1419 { 1420 MachineClass *mc = MACHINE_CLASS(oc); 1421 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1422 1423 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1424 amc->soc_name = "ast2600-a3"; 1425 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1426 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1427 amc->fmc_model = "mx66l1g45g"; 1428 amc->spi_model = "mx66l1g45g"; 1429 amc->num_cs = 2; 1430 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1431 amc->i2c_init = rainier_bmc_i2c_init; 1432 mc->default_ram_size = 1 * GiB; 1433 aspeed_machine_class_init_cpus_defaults(mc); 1434 }; 1435 1436 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1437 1438 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1439 { 1440 MachineClass *mc = MACHINE_CLASS(oc); 1441 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1442 1443 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1444 amc->soc_name = "ast2600-a3"; 1445 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1446 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1447 amc->fmc_model = "mx66l1g45g"; 1448 amc->spi_model = "mx66l1g45g"; 1449 amc->num_cs = 2; 1450 amc->macs_mask = ASPEED_MAC3_ON; 1451 amc->i2c_init = fuji_bmc_i2c_init; 1452 amc->uart_default = ASPEED_DEV_UART1; 1453 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1454 aspeed_machine_class_init_cpus_defaults(mc); 1455 }; 1456 1457 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1458 1459 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1460 { 1461 MachineClass *mc = MACHINE_CLASS(oc); 1462 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1463 1464 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1465 amc->soc_name = "ast2600-a3"; 1466 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1467 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1468 amc->fmc_model = "w25q01jvq"; 1469 amc->spi_model = NULL; 1470 amc->num_cs = 2; 1471 amc->macs_mask = ASPEED_MAC2_ON; 1472 amc->i2c_init = bletchley_bmc_i2c_init; 1473 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1474 aspeed_machine_class_init_cpus_defaults(mc); 1475 } 1476 1477 static void fby35_reset(MachineState *state, ShutdownCause reason) 1478 { 1479 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1480 AspeedGPIOState *gpio = &bmc->soc->gpio; 1481 1482 qemu_devices_reset(reason); 1483 1484 /* Board ID: 7 (Class-1, 4 slots) */ 1485 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1486 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1487 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1488 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1489 1490 /* Slot presence pins, inverse polarity. (False means present) */ 1491 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1492 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1493 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1494 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1495 1496 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1497 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1498 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1499 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1500 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1501 } 1502 1503 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1504 { 1505 MachineClass *mc = MACHINE_CLASS(oc); 1506 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1507 1508 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1509 mc->reset = fby35_reset; 1510 amc->fmc_model = "mx66l1g45g"; 1511 amc->num_cs = 2; 1512 amc->macs_mask = ASPEED_MAC3_ON; 1513 amc->i2c_init = fby35_i2c_init; 1514 /* FIXME: Replace this macro with something more general */ 1515 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1516 aspeed_machine_class_init_cpus_defaults(mc); 1517 } 1518 1519 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1520 /* Main SYSCLK frequency in Hz (200MHz) */ 1521 #define SYSCLK_FRQ 200000000ULL 1522 1523 static void aspeed_minibmc_machine_init(MachineState *machine) 1524 { 1525 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1526 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1527 Clock *sysclk; 1528 1529 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1530 clock_set_hz(sysclk, SYSCLK_FRQ); 1531 1532 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1533 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1534 object_unref(OBJECT(bmc->soc)); 1535 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1536 1537 object_property_set_link(OBJECT(bmc->soc), "memory", 1538 OBJECT(get_system_memory()), &error_abort); 1539 connect_serial_hds_to_uarts(bmc); 1540 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1541 1542 aspeed_board_init_flashes(&bmc->soc->fmc, 1543 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1544 amc->num_cs, 1545 0); 1546 1547 aspeed_board_init_flashes(&bmc->soc->spi[0], 1548 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1549 amc->num_cs, amc->num_cs); 1550 1551 aspeed_board_init_flashes(&bmc->soc->spi[1], 1552 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1553 amc->num_cs, (amc->num_cs * 2)); 1554 1555 if (amc->i2c_init) { 1556 amc->i2c_init(bmc); 1557 } 1558 1559 armv7m_load_kernel(ARM_CPU(first_cpu), 1560 machine->kernel_filename, 1561 0, 1562 AST1030_INTERNAL_FLASH_SIZE); 1563 } 1564 1565 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1566 { 1567 AspeedSoCState *soc = bmc->soc; 1568 1569 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1570 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1571 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1572 1573 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1575 } 1576 1577 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1578 void *data) 1579 { 1580 MachineClass *mc = MACHINE_CLASS(oc); 1581 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1582 1583 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1584 amc->soc_name = "ast1030-a1"; 1585 amc->hw_strap1 = 0; 1586 amc->hw_strap2 = 0; 1587 mc->init = aspeed_minibmc_machine_init; 1588 amc->i2c_init = ast1030_evb_i2c_init; 1589 mc->default_ram_size = 0; 1590 amc->fmc_model = "sst25vf032b"; 1591 amc->spi_model = "sst25vf032b"; 1592 amc->num_cs = 2; 1593 amc->macs_mask = 0; 1594 aspeed_machine_class_init_cpus_defaults(mc); 1595 } 1596 1597 #ifdef TARGET_AARCH64 1598 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1599 { 1600 MachineClass *mc = MACHINE_CLASS(oc); 1601 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1602 1603 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1604 amc->soc_name = "ast2700-a0"; 1605 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1606 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1607 amc->fmc_model = "w25q01jvq"; 1608 amc->spi_model = "w25q512jv"; 1609 amc->num_cs = 2; 1610 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1611 amc->uart_default = ASPEED_DEV_UART12; 1612 mc->default_ram_size = 1 * GiB; 1613 aspeed_machine_class_init_cpus_defaults(mc); 1614 } 1615 #endif 1616 1617 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1618 void *data) 1619 { 1620 MachineClass *mc = MACHINE_CLASS(oc); 1621 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1622 1623 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1624 amc->soc_name = "ast2600-a3"; 1625 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1626 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1627 amc->fmc_model = "n25q512a"; 1628 amc->spi_model = "n25q512a"; 1629 amc->num_cs = 2; 1630 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1631 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1632 mc->default_ram_size = 1 * GiB; 1633 aspeed_machine_class_init_cpus_defaults(mc); 1634 }; 1635 1636 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1637 void *data) 1638 { 1639 MachineClass *mc = MACHINE_CLASS(oc); 1640 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1641 1642 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1643 amc->soc_name = "ast2600-a3"; 1644 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1645 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1646 amc->fmc_model = "n25q512a"; 1647 amc->spi_model = "n25q512a"; 1648 amc->num_cs = 2; 1649 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1650 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1651 mc->default_ram_size = 1 * GiB; 1652 aspeed_machine_class_init_cpus_defaults(mc); 1653 }; 1654 1655 static const TypeInfo aspeed_machine_types[] = { 1656 { 1657 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1658 .parent = TYPE_ASPEED_MACHINE, 1659 .class_init = aspeed_machine_palmetto_class_init, 1660 }, { 1661 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1662 .parent = TYPE_ASPEED_MACHINE, 1663 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1664 }, { 1665 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1666 .parent = TYPE_ASPEED_MACHINE, 1667 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1668 }, { 1669 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1670 .parent = TYPE_ASPEED_MACHINE, 1671 .class_init = aspeed_machine_ast2500_evb_class_init, 1672 }, { 1673 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1674 .parent = TYPE_ASPEED_MACHINE, 1675 .class_init = aspeed_machine_romulus_class_init, 1676 }, { 1677 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1678 .parent = TYPE_ASPEED_MACHINE, 1679 .class_init = aspeed_machine_sonorapass_class_init, 1680 }, { 1681 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1682 .parent = TYPE_ASPEED_MACHINE, 1683 .class_init = aspeed_machine_witherspoon_class_init, 1684 }, { 1685 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1686 .parent = TYPE_ASPEED_MACHINE, 1687 .class_init = aspeed_machine_ast2600_evb_class_init, 1688 }, { 1689 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1690 .parent = TYPE_ASPEED_MACHINE, 1691 .class_init = aspeed_machine_yosemitev2_class_init, 1692 }, { 1693 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1694 .parent = TYPE_ASPEED_MACHINE, 1695 .class_init = aspeed_machine_tacoma_class_init, 1696 }, { 1697 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1698 .parent = TYPE_ASPEED_MACHINE, 1699 .class_init = aspeed_machine_tiogapass_class_init, 1700 }, { 1701 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1702 .parent = TYPE_ASPEED_MACHINE, 1703 .class_init = aspeed_machine_g220a_class_init, 1704 }, { 1705 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1706 .parent = TYPE_ASPEED_MACHINE, 1707 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1708 }, { 1709 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1710 .parent = TYPE_ASPEED_MACHINE, 1711 .class_init = aspeed_machine_qcom_firework_class_init, 1712 }, { 1713 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1714 .parent = TYPE_ASPEED_MACHINE, 1715 .class_init = aspeed_machine_fp5280g2_class_init, 1716 }, { 1717 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1718 .parent = TYPE_ASPEED_MACHINE, 1719 .class_init = aspeed_machine_quanta_q71l_class_init, 1720 }, { 1721 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1722 .parent = TYPE_ASPEED_MACHINE, 1723 .class_init = aspeed_machine_rainier_class_init, 1724 }, { 1725 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1726 .parent = TYPE_ASPEED_MACHINE, 1727 .class_init = aspeed_machine_fuji_class_init, 1728 }, { 1729 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1730 .parent = TYPE_ASPEED_MACHINE, 1731 .class_init = aspeed_machine_bletchley_class_init, 1732 }, { 1733 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1734 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1735 .class_init = aspeed_machine_fby35_class_init, 1736 }, { 1737 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1738 .parent = TYPE_ASPEED_MACHINE, 1739 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1740 #ifdef TARGET_AARCH64 1741 }, { 1742 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1743 .parent = TYPE_ASPEED_MACHINE, 1744 .class_init = aspeed_machine_ast2700_evb_class_init, 1745 #endif 1746 }, { 1747 .name = TYPE_ASPEED_MACHINE, 1748 .parent = TYPE_MACHINE, 1749 .instance_size = sizeof(AspeedMachineState), 1750 .instance_init = aspeed_machine_instance_init, 1751 .class_size = sizeof(AspeedMachineClass), 1752 .class_init = aspeed_machine_class_init, 1753 .abstract = true, 1754 } 1755 }; 1756 1757 DEFINE_TYPES(aspeed_machine_types) 1758