1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/gpio/pca9554.h" 23 #include "hw/nvram/eeprom_at24c.h" 24 #include "hw/sensor/tmp105.h" 25 #include "hw/misc/led.h" 26 #include "hw/qdev-properties.h" 27 #include "system/block-backend.h" 28 #include "system/reset.h" 29 #include "hw/loader.h" 30 #include "qemu/error-report.h" 31 #include "qemu/datadir.h" 32 #include "qemu/units.h" 33 #include "hw/qdev-clock.h" 34 #include "system/system.h" 35 36 static struct arm_boot_info aspeed_board_binfo = { 37 .board_id = -1, /* device-tree-only board */ 38 }; 39 40 struct AspeedMachineState { 41 /* Private */ 42 MachineState parent_obj; 43 /* Public */ 44 45 AspeedSoCState *soc; 46 MemoryRegion boot_rom; 47 bool mmio_exec; 48 uint32_t uart_chosen; 49 char *fmc_model; 50 char *spi_model; 51 uint32_t hw_strap1; 52 }; 53 54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 55 #if HOST_LONG_BITS == 32 56 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 57 #else 58 #define ASPEED_RAM_SIZE(sz) (sz) 59 #endif 60 61 /* Palmetto hardware value: 0x120CE416 */ 62 #define PALMETTO_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* TODO: Find the actual hardware value */ 76 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 77 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 78 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 79 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 80 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 81 SCU_HW_STRAP_VGA_CLASS_CODE | \ 82 SCU_HW_STRAP_LPC_RESET_PIN | \ 83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 84 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 85 SCU_HW_STRAP_SPI_WIDTH | \ 86 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 87 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 88 89 /* TODO: Find the actual hardware value */ 90 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 91 AST2500_HW_STRAP1_DEFAULTS | \ 92 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 93 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 94 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 95 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 96 SCU_HW_STRAP_SPI_WIDTH | \ 97 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 98 99 /* AST2500 evb hardware value: 0xF100C2E6 */ 100 #define AST2500_EVB_HW_STRAP1 (( \ 101 AST2500_HW_STRAP1_DEFAULTS | \ 102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 104 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 106 SCU_HW_STRAP_MAC1_RGMII | \ 107 SCU_HW_STRAP_MAC0_RGMII) & \ 108 ~SCU_HW_STRAP_2ND_BOOT_WDT) 109 110 /* Romulus hardware value: 0xF10AD206 */ 111 #define ROMULUS_BMC_HW_STRAP1 ( \ 112 AST2500_HW_STRAP1_DEFAULTS | \ 113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 115 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 /* Sonorapass hardware value: 0xF100D216 */ 121 #define SONORAPASS_BMC_HW_STRAP1 ( \ 122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 124 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 125 SCU_AST2500_HW_STRAP_RESERVED28 | \ 126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_BIOS_ROM | \ 132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 133 SCU_AST2500_HW_STRAP_RESERVED1) 134 135 #define G220A_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_2ND_BOOT_WDT | \ 142 SCU_HW_STRAP_VGA_CLASS_CODE | \ 143 SCU_HW_STRAP_LPC_RESET_PIN | \ 144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* FP5280G2 hardware value: 0XF100D286 */ 150 #define FP5280G2_BMC_HW_STRAP1 ( \ 151 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 152 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 153 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 154 SCU_AST2500_HW_STRAP_RESERVED28 | \ 155 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 156 SCU_HW_STRAP_VGA_CLASS_CODE | \ 157 SCU_HW_STRAP_LPC_RESET_PIN | \ 158 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 159 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 160 SCU_HW_STRAP_MAC1_RGMII | \ 161 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 162 SCU_AST2500_HW_STRAP_RESERVED1) 163 164 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 165 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 166 167 /* Quanta-Q71l hardware value */ 168 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 169 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 170 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 171 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 172 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 173 SCU_HW_STRAP_VGA_CLASS_CODE | \ 174 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 175 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 176 SCU_HW_STRAP_SPI_WIDTH | \ 177 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 178 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 179 180 /* AST2600 evb hardware value */ 181 #define AST2600_EVB_HW_STRAP1 0x000000C0 182 #define AST2600_EVB_HW_STRAP2 0x00000003 183 184 #ifdef TARGET_AARCH64 185 /* AST2700 evb hardware value */ 186 /* SCU HW Strap1 */ 187 #define AST2700_EVB_HW_STRAP1 0x00000800 188 /* SCUIO HW Strap1 */ 189 #define AST2700_EVB_HW_STRAP2 0x00000700 190 #endif 191 192 /* Rainier hardware value: (QEMU prototype) */ 193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 194 #define RAINIER_BMC_HW_STRAP2 0x80000848 195 196 /* Fuji hardware value */ 197 #define FUJI_BMC_HW_STRAP1 0x00000000 198 #define FUJI_BMC_HW_STRAP2 0x00000000 199 200 /* Bletchley hardware value */ 201 #define BLETCHLEY_BMC_HW_STRAP1 0x00002000 202 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801 203 204 /* Qualcomm DC-SCM hardware value */ 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 207 208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 215 216 static void aspeed_write_smpboot(ARMCPU *cpu, 217 const struct arm_boot_info *info) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 static const ARMInsnFixup poll_mailbox_ready[] = { 221 /* 222 * r2 = per-cpu go sign value 223 * r1 = AST_SMP_MBOX_FIELD_ENTRY 224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 225 */ 226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 227 { 0xe21000ff }, /* ands r0, r0, #255 */ 228 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 229 { 0xe1822000 }, /* orr r2, r2, r0 */ 230 231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 233 234 { 0xe320f002 }, /* wfe */ 235 { 0xe5904000 }, /* ldr r4, [r0] */ 236 { 0xe1520004 }, /* cmp r2, r4 */ 237 { 0x1afffffb }, /* bne <wfe> */ 238 { 0xe591f000 }, /* ldr pc, [r1] */ 239 { AST_SMP_MBOX_GOSIGN }, 240 { AST_SMP_MBOX_FIELD_ENTRY }, 241 { AST_SMP_MBOX_FIELD_GOSIGN }, 242 { 0, FIXUP_TERMINATOR } 243 }; 244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 245 246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 247 poll_mailbox_ready, fixupcontext); 248 } 249 250 static void aspeed_reset_secondary(ARMCPU *cpu, 251 const struct arm_boot_info *info) 252 { 253 AddressSpace *as = arm_boot_address_space(cpu, info); 254 CPUState *cs = CPU(cpu); 255 256 /* info->smp_bootreg_addr */ 257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 258 MEMTXATTRS_UNSPECIFIED, NULL); 259 cpu_set_pc(cs, info->smp_loader_start); 260 } 261 262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 263 Error **errp) 264 { 265 g_autofree void *storage = NULL; 266 int64_t size; 267 268 /* 269 * The block backend size should have already been 'validated' by 270 * the creation of the m25p80 object. 271 */ 272 size = blk_getlength(blk); 273 if (size <= 0) { 274 error_setg(errp, "failed to get flash size"); 275 return; 276 } 277 278 if (rom_size > size) { 279 rom_size = size; 280 } 281 282 storage = g_malloc0(rom_size); 283 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 284 error_setg(errp, "failed to read the initial flash content"); 285 return; 286 } 287 288 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 289 } 290 291 /* 292 * Create a ROM and copy the flash contents at the expected address 293 * (0x0). Boots faster than execute-in-place. 294 */ 295 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 296 uint64_t rom_size) 297 { 298 AspeedSoCState *soc = bmc->soc; 299 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 300 301 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 302 &error_abort); 303 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 304 &bmc->boot_rom, 1); 305 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 306 rom_size, &error_abort); 307 } 308 309 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" 310 311 /* 312 * This function locates the vbootrom image file specified via the command line 313 * using the -bios option. It loads the specified image into the vbootrom 314 * memory region and handles errors if the file cannot be found or loaded. 315 */ 316 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name, 317 Error **errp) 318 { 319 g_autofree char *filename = NULL; 320 AspeedSoCState *soc = bmc->soc; 321 int ret; 322 323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 324 if (!filename) { 325 error_setg(errp, "Could not find vbootrom image '%s'", bios_name); 326 return; 327 } 328 329 ret = load_image_mr(filename, &soc->vbootrom); 330 if (ret < 0) { 331 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); 332 return; 333 } 334 } 335 336 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 337 unsigned int count, int unit0) 338 { 339 int i; 340 341 if (!flashtype) { 342 return; 343 } 344 345 for (i = 0; i < count; ++i) { 346 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 347 DeviceState *dev; 348 349 dev = qdev_new(flashtype); 350 if (dinfo) { 351 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 352 } 353 qdev_prop_set_uint8(dev, "cs", i); 354 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 355 } 356 } 357 358 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 359 bool boot_emmc) 360 { 361 DeviceState *card; 362 363 if (!dinfo) { 364 return; 365 } 366 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 367 368 /* 369 * Force the boot properties of the eMMC device only when the 370 * machine is strapped to boot from eMMC. Without these 371 * settings, the machine would not boot. 372 * 373 * This also allows the machine to use an eMMC device without 374 * boot areas when booting from the flash device (or -kernel) 375 * Ideally, the device and its properties should be defined on 376 * the command line. 377 */ 378 if (emmc && boot_emmc) { 379 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 380 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 381 } 382 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 383 &error_fatal); 384 qdev_realize_and_unref(card, 385 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 386 &error_fatal); 387 } 388 389 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 390 { 391 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 392 AspeedSoCState *s = bmc->soc; 393 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 394 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 395 396 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 397 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 398 if (uart == uart_chosen) { 399 continue; 400 } 401 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); 402 } 403 } 404 405 static void aspeed_machine_init(MachineState *machine) 406 { 407 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 408 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 409 AspeedSoCClass *sc; 410 int i; 411 const char *bios_name = NULL; 412 DriveInfo *emmc0 = NULL; 413 bool boot_emmc; 414 415 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 416 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 417 object_unref(OBJECT(bmc->soc)); 418 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 419 420 /* 421 * This will error out if the RAM size is not supported by the 422 * memory controller of the SoC. 423 */ 424 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 425 &error_fatal); 426 427 for (i = 0; i < sc->macs_num; i++) { 428 if ((amc->macs_mask & (1 << i)) && 429 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 430 true, NULL)) { 431 break; /* No configs left; stop asking */ 432 } 433 } 434 435 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 436 &error_abort); 437 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 438 &error_abort); 439 object_property_set_link(OBJECT(bmc->soc), "memory", 440 OBJECT(get_system_memory()), &error_abort); 441 object_property_set_link(OBJECT(bmc->soc), "dram", 442 OBJECT(machine->ram), &error_abort); 443 if (amc->sdhci_wp_inverted) { 444 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 445 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 446 "wp-inverted", true, &error_abort); 447 } 448 } 449 if (machine->kernel_filename) { 450 /* 451 * When booting with a -kernel command line there is no u-boot 452 * that runs to unlock the SCU. In this case set the default to 453 * be unlocked as the kernel expects 454 */ 455 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 456 ASPEED_SCU_PROT_KEY, &error_abort); 457 } 458 connect_serial_hds_to_uarts(bmc); 459 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 460 461 if (defaults_enabled()) { 462 aspeed_board_init_flashes(&bmc->soc->fmc, 463 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 464 amc->num_cs, 0); 465 aspeed_board_init_flashes(&bmc->soc->spi[0], 466 bmc->spi_model ? bmc->spi_model : amc->spi_model, 467 1, amc->num_cs); 468 aspeed_board_init_flashes(&bmc->soc->spi[1], 469 amc->spi2_model, 1, amc->num_cs2); 470 } 471 472 if (machine->kernel_filename && sc->num_cpus > 1) { 473 /* With no u-boot we must set up a boot stub for the secondary CPU */ 474 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 475 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 476 0x80, &error_abort); 477 memory_region_add_subregion(get_system_memory(), 478 AST_SMP_MAILBOX_BASE, smpboot); 479 480 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 481 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 482 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 483 } 484 485 aspeed_board_binfo.ram_size = machine->ram_size; 486 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 487 488 if (amc->i2c_init) { 489 amc->i2c_init(bmc); 490 } 491 492 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 493 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 494 drive_get(IF_SD, 0, i), false, false); 495 } 496 497 boot_emmc = sc->boot_from_emmc(bmc->soc); 498 499 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 500 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 501 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 502 } 503 504 if (!bmc->mmio_exec) { 505 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 506 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 507 508 if (fmc0 && !boot_emmc) { 509 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 510 aspeed_install_boot_rom(bmc, fmc0, rom_size); 511 } else if (emmc0) { 512 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 513 } 514 } 515 516 if (amc->vbootrom) { 517 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; 518 aspeed_load_vbootrom(bmc, bios_name, &error_abort); 519 } 520 521 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 522 } 523 524 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 525 { 526 AspeedSoCState *soc = bmc->soc; 527 DeviceState *dev; 528 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 529 530 /* 531 * The palmetto platform expects a ds3231 RTC but a ds1338 is 532 * enough to provide basic RTC features. Alarms will be missing 533 */ 534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 535 536 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 537 eeprom_buf); 538 539 /* add a TMP423 temperature sensor */ 540 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 541 "tmp423", 0x4c)); 542 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 543 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 544 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 545 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 546 } 547 548 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 549 { 550 AspeedSoCState *soc = bmc->soc; 551 552 /* 553 * The quanta-q71l platform expects tmp75s which are compatible with 554 * tmp105s. 555 */ 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 557 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 559 560 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 561 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 562 /* TODO: Add Memory Riser i2c mux and eeproms. */ 563 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 566 567 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 568 569 /* i2c-7 */ 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 571 /* - i2c@0: pmbus@59 */ 572 /* - i2c@1: pmbus@58 */ 573 /* - i2c@2: pmbus@58 */ 574 /* - i2c@3: pmbus@59 */ 575 576 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 577 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 578 } 579 580 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 581 { 582 AspeedSoCState *soc = bmc->soc; 583 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 584 585 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 586 eeprom_buf); 587 588 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 589 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 590 TYPE_TMP105, 0x4d); 591 } 592 593 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 594 { 595 AspeedSoCState *soc = bmc->soc; 596 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 597 598 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 599 eeprom_buf); 600 601 /* LM75 is compatible with TMP105 driver */ 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 603 TYPE_TMP105, 0x4d); 604 } 605 606 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 607 { 608 AspeedSoCState *soc = bmc->soc; 609 610 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 611 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 612 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 613 /* TMP421 */ 614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 616 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 617 618 } 619 620 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 621 { 622 AspeedSoCState *soc = bmc->soc; 623 624 /* 625 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 626 * good enough 627 */ 628 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 629 } 630 631 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 632 { 633 AspeedSoCState *soc = bmc->soc; 634 635 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 636 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 637 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 638 /* TMP421 */ 639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 640 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 641 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 642 } 643 644 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 645 { 646 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 647 TYPE_PCA9552, addr); 648 } 649 650 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 651 { 652 AspeedSoCState *soc = bmc->soc; 653 654 /* bus 2 : */ 655 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 656 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 657 /* bus 2 : pca9546 @ 0x73 */ 658 659 /* bus 3 : pca9548 @ 0x70 */ 660 661 /* bus 4 : */ 662 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 663 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 664 eeprom4_54); 665 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 666 create_pca9552(soc, 4, 0x76); 667 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 668 create_pca9552(soc, 4, 0x77); 669 670 /* bus 6 : */ 671 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 672 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 673 /* bus 6 : pca9546 @ 0x73 */ 674 675 /* bus 8 : */ 676 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 677 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 678 eeprom8_56); 679 create_pca9552(soc, 8, 0x60); 680 create_pca9552(soc, 8, 0x61); 681 /* bus 8 : adc128d818 @ 0x1d */ 682 /* bus 8 : adc128d818 @ 0x1f */ 683 684 /* 685 * bus 13 : pca9548 @ 0x71 686 * - channel 3: 687 * - tmm421 @ 0x4c 688 * - tmp421 @ 0x4e 689 * - tmp421 @ 0x4f 690 */ 691 692 } 693 694 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 695 { 696 static const struct { 697 unsigned gpio_id; 698 LEDColor color; 699 const char *description; 700 bool gpio_polarity; 701 } pca1_leds[] = { 702 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 703 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 704 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 705 }; 706 AspeedSoCState *soc = bmc->soc; 707 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 708 DeviceState *dev; 709 LEDState *led; 710 711 /* Bus 3: TODO bmp280@77 */ 712 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 713 qdev_prop_set_string(dev, "description", "pca1"); 714 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 715 aspeed_i2c_get_bus(&soc->i2c, 3), 716 &error_fatal); 717 718 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 719 led = led_create_simple(OBJECT(bmc), 720 pca1_leds[i].gpio_polarity, 721 pca1_leds[i].color, 722 pca1_leds[i].description); 723 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 724 qdev_get_gpio_in(DEVICE(led), 0)); 725 } 726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 727 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 729 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 730 731 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 733 0x4a); 734 735 /* 736 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 737 * good enough 738 */ 739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 740 741 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 742 eeprom_buf); 743 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 744 qdev_prop_set_string(dev, "description", "pca0"); 745 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 746 aspeed_i2c_get_bus(&soc->i2c, 11), 747 &error_fatal); 748 /* Bus 11: TODO ucd90160@64 */ 749 } 750 751 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 752 { 753 AspeedSoCState *soc = bmc->soc; 754 DeviceState *dev; 755 756 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 757 "emc1413", 0x4c)); 758 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 759 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 760 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 761 762 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 763 "emc1413", 0x4c)); 764 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 765 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 766 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 767 768 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 769 "emc1413", 0x4c)); 770 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 771 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 772 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 773 774 static uint8_t eeprom_buf[2 * 1024] = { 775 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 776 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 777 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 778 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 779 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 780 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 781 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 782 }; 783 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 784 eeprom_buf); 785 } 786 787 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 788 { 789 AspeedSoCState *soc = bmc->soc; 790 I2CSlave *i2c_mux; 791 792 /* The at24c256 */ 793 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 794 795 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 797 0x48); 798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 799 0x49); 800 801 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 802 "pca9546", 0x70); 803 /* It expects a TMP112 but a TMP105 is compatible */ 804 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 805 0x4a); 806 807 /* It expects a ds3232 but a ds1338 is good enough */ 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 809 810 /* It expects a pca9555 but a pca9552 is compatible */ 811 create_pca9552(soc, 8, 0x30); 812 } 813 814 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 815 { 816 AspeedSoCState *soc = bmc->soc; 817 I2CSlave *i2c_mux; 818 819 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 820 821 create_pca9552(soc, 3, 0x61); 822 823 /* The rainier expects a TMP275 but a TMP105 is compatible */ 824 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 825 0x48); 826 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 827 0x49); 828 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 829 0x4a); 830 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 831 "pca9546", 0x70); 832 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 833 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 834 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 835 create_pca9552(soc, 4, 0x60); 836 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 838 0x48); 839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 840 0x49); 841 create_pca9552(soc, 5, 0x60); 842 create_pca9552(soc, 5, 0x61); 843 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 844 "pca9546", 0x70); 845 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 846 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 847 848 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 849 0x48); 850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 851 0x4a); 852 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 853 0x4b); 854 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 855 "pca9546", 0x70); 856 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 857 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 858 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 859 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 860 861 create_pca9552(soc, 7, 0x30); 862 create_pca9552(soc, 7, 0x31); 863 create_pca9552(soc, 7, 0x32); 864 create_pca9552(soc, 7, 0x33); 865 create_pca9552(soc, 7, 0x60); 866 create_pca9552(soc, 7, 0x61); 867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 868 /* Bus 7: TODO si7021-a20@20 */ 869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 870 0x48); 871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 872 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 873 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 874 875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 876 0x48); 877 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 878 0x4a); 879 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 880 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 881 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 882 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 883 create_pca9552(soc, 8, 0x60); 884 create_pca9552(soc, 8, 0x61); 885 /* Bus 8: ucd90320@11 */ 886 /* Bus 8: ucd90320@b */ 887 /* Bus 8: ucd90320@c */ 888 889 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 890 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 891 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 892 893 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 894 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 895 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 896 897 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 898 0x48); 899 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 900 0x49); 901 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 902 "pca9546", 0x70); 903 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 904 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 905 create_pca9552(soc, 11, 0x60); 906 907 908 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 909 create_pca9552(soc, 13, 0x60); 910 911 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 912 create_pca9552(soc, 14, 0x60); 913 914 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 915 create_pca9552(soc, 15, 0x60); 916 } 917 918 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 919 I2CBus **channels) 920 { 921 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 922 for (int i = 0; i < 8; i++) { 923 channels[i] = pca954x_i2c_get_bus(mux, i); 924 } 925 } 926 927 #define TYPE_LM75 TYPE_TMP105 928 #define TYPE_TMP75 TYPE_TMP105 929 #define TYPE_TMP422 "tmp422" 930 931 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 932 { 933 AspeedSoCState *soc = bmc->soc; 934 I2CBus *i2c[144] = {}; 935 936 for (int i = 0; i < 16; i++) { 937 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 938 } 939 I2CBus *i2c180 = i2c[2]; 940 I2CBus *i2c480 = i2c[8]; 941 I2CBus *i2c600 = i2c[11]; 942 943 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 944 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 945 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 946 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 947 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 948 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 949 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 950 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 951 for (int i = 0; i < 8; i++) { 952 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 953 } 954 955 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 956 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 957 958 /* 959 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 960 * 24c02 size is 2Kbits or 256 bytes 961 */ 962 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 963 at24c_eeprom_init(i2c[20], 0x50, 256); 964 at24c_eeprom_init(i2c[22], 0x52, 256); 965 966 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 967 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 968 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 969 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 970 971 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 972 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 973 974 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 975 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 976 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 977 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 978 979 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 980 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 981 982 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 983 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 984 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 985 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 986 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 987 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 988 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 989 990 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 991 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 992 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 993 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 994 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 995 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 996 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 997 at24c_eeprom_init(i2c[28], 0x50, 256); 998 999 for (int i = 0; i < 8; i++) { 1000 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 1001 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 1002 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 1003 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 1004 } 1005 } 1006 1007 #define TYPE_TMP421 "tmp421" 1008 #define TYPE_DS1338 "ds1338" 1009 1010 /* Catalina hardware value */ 1011 #define CATALINA_BMC_HW_STRAP1 0x00002002 1012 #define CATALINA_BMC_HW_STRAP2 0x00000800 1013 1014 #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1015 1016 static void catalina_bmc_i2c_init(AspeedMachineState *bmc) 1017 { 1018 /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ 1019 1020 AspeedSoCState *soc = bmc->soc; 1021 I2CBus *i2c[16] = {}; 1022 I2CSlave *i2c_mux; 1023 1024 /* busses 0-15 are all used. */ 1025 for (int i = 0; i < ARRAY_SIZE(i2c); i++) { 1026 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1027 } 1028 1029 /* &i2c0 */ 1030 /* i2c-mux@71 (PCA9546) on i2c0 */ 1031 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); 1032 1033 /* i2c-mux@72 (PCA9546) on i2c0 */ 1034 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); 1035 1036 /* i2c0mux1ch1 */ 1037 /* io_expander7 - pca9535@20 */ 1038 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1039 TYPE_PCA9552, 0x20); 1040 /* eeprom@50 */ 1041 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1042 1043 /* i2c-mux@73 (PCA9546) on i2c0 */ 1044 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); 1045 1046 /* i2c-mux@75 (PCA9546) on i2c0 */ 1047 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); 1048 1049 /* i2c-mux@76 (PCA9546) on i2c0 */ 1050 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); 1051 1052 /* i2c0mux4ch1 */ 1053 /* io_expander8 - pca9535@21 */ 1054 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1055 TYPE_PCA9552, 0x21); 1056 /* eeprom@50 */ 1057 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1058 1059 /* i2c-mux@77 (PCA9546) on i2c0 */ 1060 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); 1061 1062 1063 /* &i2c1 */ 1064 /* i2c-mux@70 (PCA9548) on i2c1 */ 1065 i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); 1066 /* i2c1mux0ch0 */ 1067 /* ina238@41 - no model */ 1068 /* ina238@42 - no model */ 1069 /* ina238@44 - no model */ 1070 /* i2c1mux0ch1 */ 1071 /* ina238@41 - no model */ 1072 /* ina238@43 - no model */ 1073 /* i2c1mux0ch4 */ 1074 /* ltc4287@42 - no model */ 1075 /* ltc4287@43 - no model */ 1076 1077 /* i2c1mux0ch5 */ 1078 /* eeprom@54 */ 1079 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); 1080 /* tpm75@4f */ 1081 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); 1082 1083 /* i2c1mux0ch6 */ 1084 /* io_expander5 - pca9554@27 */ 1085 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1086 TYPE_PCA9554, 0x27); 1087 /* io_expander6 - pca9555@25 */ 1088 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1089 TYPE_PCA9552, 0x25); 1090 /* eeprom@51 */ 1091 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); 1092 1093 /* i2c1mux0ch7 */ 1094 /* eeprom@53 */ 1095 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); 1096 /* temperature-sensor@4b - tmp75 */ 1097 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); 1098 1099 /* &i2c2 */ 1100 /* io_expander0 - pca9555@20 */ 1101 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); 1102 /* io_expander0 - pca9555@21 */ 1103 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); 1104 /* io_expander0 - pca9555@27 */ 1105 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); 1106 /* eeprom@50 */ 1107 at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); 1108 /* eeprom@51 */ 1109 at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); 1110 1111 /* &i2c5 */ 1112 /* i2c-mux@70 (PCA9548) on i2c5 */ 1113 i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); 1114 /* i2c5mux0ch6 */ 1115 /* eeprom@52 */ 1116 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); 1117 /* i2c5mux0ch7 */ 1118 /* ina230@40 - no model */ 1119 /* ina230@41 - no model */ 1120 /* ina230@44 - no model */ 1121 /* ina230@45 - no model */ 1122 1123 /* &i2c6 */ 1124 /* io_expander3 - pca9555@21 */ 1125 i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); 1126 /* rtc@6f - nct3018y */ 1127 i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); 1128 1129 /* &i2c9 */ 1130 /* io_expander4 - pca9555@4f */ 1131 i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); 1132 /* temperature-sensor@4b - tpm75 */ 1133 i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); 1134 /* eeprom@50 */ 1135 at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); 1136 /* eeprom@56 */ 1137 at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); 1138 1139 /* &i2c10 */ 1140 /* temperature-sensor@1f - tpm421 */ 1141 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); 1142 /* eeprom@50 */ 1143 at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); 1144 1145 /* &i2c11 */ 1146 /* ssif-bmc@10 - no model */ 1147 1148 /* &i2c12 */ 1149 /* eeprom@50 */ 1150 at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); 1151 1152 /* &i2c13 */ 1153 /* eeprom@50 */ 1154 at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); 1155 /* eeprom@54 */ 1156 at24c_eeprom_init(i2c[13], 0x54, 256); 1157 /* eeprom@55 */ 1158 at24c_eeprom_init(i2c[13], 0x55, 256); 1159 /* eeprom@57 */ 1160 at24c_eeprom_init(i2c[13], 0x57, 256); 1161 1162 /* &i2c14 */ 1163 /* io_expander9 - pca9555@10 */ 1164 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); 1165 /* io_expander10 - pca9555@11 */ 1166 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); 1167 /* io_expander11 - pca9555@12 */ 1168 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); 1169 /* io_expander12 - pca9555@13 */ 1170 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); 1171 /* io_expander13 - pca9555@14 */ 1172 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); 1173 /* io_expander14 - pca9555@15 */ 1174 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); 1175 1176 /* &i2c15 */ 1177 /* temperature-sensor@1f - tmp421 */ 1178 i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); 1179 /* eeprom@52 */ 1180 at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); 1181 } 1182 1183 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1184 { 1185 AspeedSoCState *soc = bmc->soc; 1186 I2CBus *i2c[13] = {}; 1187 for (int i = 0; i < 13; i++) { 1188 if ((i == 8) || (i == 11)) { 1189 continue; 1190 } 1191 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1192 } 1193 1194 /* Bus 0 - 5 all have the same config. */ 1195 for (int i = 0; i < 6; i++) { 1196 /* Missing model: ti,ina230 @ 0x45 */ 1197 /* Missing model: mps,mp5023 @ 0x40 */ 1198 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1199 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1200 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1201 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1202 /* Missing model: fsc,fusb302 @ 0x22 */ 1203 } 1204 1205 /* Bus 6 */ 1206 at24c_eeprom_init(i2c[6], 0x56, 65536); 1207 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1208 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1209 1210 1211 /* Bus 7 */ 1212 at24c_eeprom_init(i2c[7], 0x54, 65536); 1213 1214 /* Bus 9 */ 1215 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1216 1217 /* Bus 10 */ 1218 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1219 /* Missing model: ti,hdc1080 @ 0x40 */ 1220 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1221 1222 /* Bus 12 */ 1223 /* Missing model: adi,adm1278 @ 0x11 */ 1224 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1225 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1226 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1227 } 1228 1229 static void fby35_i2c_init(AspeedMachineState *bmc) 1230 { 1231 AspeedSoCState *soc = bmc->soc; 1232 I2CBus *i2c[16]; 1233 1234 for (int i = 0; i < 16; i++) { 1235 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1236 } 1237 1238 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1239 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1240 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1241 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1242 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1243 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1244 1245 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1246 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1247 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1248 fby35_nic_fruid_len); 1249 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1250 fby35_bb_fruid_len); 1251 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1252 fby35_bmc_fruid_len); 1253 1254 /* 1255 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1256 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1257 * each. 1258 */ 1259 } 1260 1261 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1262 { 1263 AspeedSoCState *soc = bmc->soc; 1264 1265 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1266 } 1267 1268 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1269 { 1270 AspeedSoCState *soc = bmc->soc; 1271 I2CSlave *therm_mux, *cpuvr_mux; 1272 1273 /* Create the generic DC-SCM hardware */ 1274 qcom_dc_scm_bmc_i2c_init(bmc); 1275 1276 /* Now create the Firework specific hardware */ 1277 1278 /* I2C7 CPUVR MUX */ 1279 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1280 "pca9546", 0x70); 1281 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1282 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1283 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1284 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1285 1286 /* I2C8 Thermal Diodes*/ 1287 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1288 "pca9548", 0x70); 1289 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1290 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1291 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1292 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1293 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1294 1295 /* I2C9 Fan Controller (MAX31785) */ 1296 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1297 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1298 } 1299 1300 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1301 { 1302 return ASPEED_MACHINE(obj)->mmio_exec; 1303 } 1304 1305 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1306 { 1307 ASPEED_MACHINE(obj)->mmio_exec = value; 1308 } 1309 1310 static void aspeed_machine_instance_init(Object *obj) 1311 { 1312 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1313 1314 ASPEED_MACHINE(obj)->mmio_exec = false; 1315 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1316 } 1317 1318 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1319 { 1320 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1321 return g_strdup(bmc->fmc_model); 1322 } 1323 1324 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1325 { 1326 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1327 1328 g_free(bmc->fmc_model); 1329 bmc->fmc_model = g_strdup(value); 1330 } 1331 1332 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1333 { 1334 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1335 return g_strdup(bmc->spi_model); 1336 } 1337 1338 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1339 { 1340 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1341 1342 g_free(bmc->spi_model); 1343 bmc->spi_model = g_strdup(value); 1344 } 1345 1346 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1347 { 1348 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1349 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1350 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1351 1352 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1353 } 1354 1355 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1356 { 1357 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1358 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1359 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1360 int val; 1361 int uart_first = aspeed_uart_first(sc); 1362 int uart_last = aspeed_uart_last(sc); 1363 1364 if (sscanf(value, "uart%u", &val) != 1) { 1365 error_setg(errp, "Bad value for \"uart\" property"); 1366 return; 1367 } 1368 1369 /* The number of UART depends on the SoC */ 1370 if (val < uart_first || val > uart_last) { 1371 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1372 uart_first, uart_last); 1373 return; 1374 } 1375 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1376 } 1377 1378 static void aspeed_machine_class_props_init(ObjectClass *oc) 1379 { 1380 object_class_property_add_bool(oc, "execute-in-place", 1381 aspeed_get_mmio_exec, 1382 aspeed_set_mmio_exec); 1383 object_class_property_set_description(oc, "execute-in-place", 1384 "boot directly from CE0 flash device"); 1385 1386 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1387 aspeed_set_bmc_console); 1388 object_class_property_set_description(oc, "bmc-console", 1389 "Change the default UART to \"uartX\""); 1390 1391 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1392 aspeed_set_fmc_model); 1393 object_class_property_set_description(oc, "fmc-model", 1394 "Change the FMC Flash model"); 1395 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1396 aspeed_set_spi_model); 1397 object_class_property_set_description(oc, "spi-model", 1398 "Change the SPI Flash model"); 1399 } 1400 1401 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1402 { 1403 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1404 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1405 1406 mc->default_cpus = sc->num_cpus; 1407 mc->min_cpus = sc->num_cpus; 1408 mc->max_cpus = sc->num_cpus; 1409 mc->valid_cpu_types = sc->valid_cpu_types; 1410 } 1411 1412 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1413 { 1414 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1415 1416 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1417 } 1418 1419 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1420 Error **errp) 1421 { 1422 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1423 1424 if (value) { 1425 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1426 } else { 1427 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1428 } 1429 } 1430 1431 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1432 { 1433 object_class_property_add_bool(oc, "boot-emmc", 1434 aspeed_machine_ast2600_get_boot_from_emmc, 1435 aspeed_machine_ast2600_set_boot_from_emmc); 1436 object_class_property_set_description(oc, "boot-emmc", 1437 "Set or unset boot from EMMC"); 1438 } 1439 1440 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 1441 { 1442 MachineClass *mc = MACHINE_CLASS(oc); 1443 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1444 1445 mc->init = aspeed_machine_init; 1446 mc->no_floppy = 1; 1447 mc->no_cdrom = 1; 1448 mc->no_parallel = 1; 1449 mc->default_ram_id = "ram"; 1450 amc->macs_mask = ASPEED_MAC0_ON; 1451 amc->uart_default = ASPEED_DEV_UART5; 1452 1453 aspeed_machine_class_props_init(oc); 1454 } 1455 1456 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, 1457 const void *data) 1458 { 1459 MachineClass *mc = MACHINE_CLASS(oc); 1460 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1461 1462 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1463 amc->soc_name = "ast2400-a1"; 1464 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1465 amc->fmc_model = "n25q256a"; 1466 amc->spi_model = "mx25l25635f"; 1467 amc->num_cs = 1; 1468 amc->i2c_init = palmetto_bmc_i2c_init; 1469 mc->auto_create_sdcard = true; 1470 mc->default_ram_size = 256 * MiB; 1471 aspeed_machine_class_init_cpus_defaults(mc); 1472 }; 1473 1474 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, 1475 const void *data) 1476 { 1477 MachineClass *mc = MACHINE_CLASS(oc); 1478 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1479 1480 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1481 amc->soc_name = "ast2400-a1"; 1482 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1483 amc->fmc_model = "n25q256a"; 1484 amc->spi_model = "mx25l25635e"; 1485 amc->num_cs = 1; 1486 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1487 mc->auto_create_sdcard = true; 1488 mc->default_ram_size = 128 * MiB; 1489 aspeed_machine_class_init_cpus_defaults(mc); 1490 } 1491 1492 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1493 const void *data) 1494 { 1495 MachineClass *mc = MACHINE_CLASS(oc); 1496 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1497 1498 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1499 amc->soc_name = "ast2400-a1"; 1500 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1501 amc->fmc_model = "mx25l25635e"; 1502 amc->spi_model = "mx25l25635e"; 1503 amc->num_cs = 1; 1504 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1505 amc->i2c_init = palmetto_bmc_i2c_init; 1506 mc->auto_create_sdcard = true; 1507 mc->default_ram_size = 256 * MiB; 1508 aspeed_machine_class_init_cpus_defaults(mc); 1509 } 1510 1511 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1512 const void *data) 1513 { 1514 MachineClass *mc = MACHINE_CLASS(oc); 1515 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1516 1517 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1518 amc->soc_name = "ast2500-a1"; 1519 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1520 amc->fmc_model = "mx25l25635e"; 1521 amc->spi_model = "mx25l25635e"; 1522 amc->num_cs = 1; 1523 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1524 amc->i2c_init = palmetto_bmc_i2c_init; 1525 mc->auto_create_sdcard = true; 1526 mc->default_ram_size = 512 * MiB; 1527 aspeed_machine_class_init_cpus_defaults(mc); 1528 } 1529 1530 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, 1531 const void *data) 1532 { 1533 MachineClass *mc = MACHINE_CLASS(oc); 1534 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1535 1536 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1537 amc->soc_name = "ast2500-a1"; 1538 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1539 amc->fmc_model = "mx25l25635e"; 1540 amc->spi_model = "mx25l25635f"; 1541 amc->num_cs = 1; 1542 amc->i2c_init = ast2500_evb_i2c_init; 1543 mc->auto_create_sdcard = true; 1544 mc->default_ram_size = 512 * MiB; 1545 aspeed_machine_class_init_cpus_defaults(mc); 1546 }; 1547 1548 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, 1549 const void *data) 1550 { 1551 MachineClass *mc = MACHINE_CLASS(oc); 1552 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1553 1554 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1555 amc->soc_name = "ast2500-a1"; 1556 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1557 amc->hw_strap2 = 0; 1558 amc->fmc_model = "n25q256a"; 1559 amc->spi_model = "mx25l25635e"; 1560 amc->num_cs = 2; 1561 amc->i2c_init = yosemitev2_bmc_i2c_init; 1562 mc->auto_create_sdcard = true; 1563 mc->default_ram_size = 512 * MiB; 1564 aspeed_machine_class_init_cpus_defaults(mc); 1565 }; 1566 1567 static void aspeed_machine_romulus_class_init(ObjectClass *oc, 1568 const void *data) 1569 { 1570 MachineClass *mc = MACHINE_CLASS(oc); 1571 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1572 1573 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1574 amc->soc_name = "ast2500-a1"; 1575 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1576 amc->fmc_model = "n25q256a"; 1577 amc->spi_model = "mx66l1g45g"; 1578 amc->num_cs = 2; 1579 amc->i2c_init = romulus_bmc_i2c_init; 1580 mc->auto_create_sdcard = true; 1581 mc->default_ram_size = 512 * MiB; 1582 aspeed_machine_class_init_cpus_defaults(mc); 1583 }; 1584 1585 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, 1586 const void *data) 1587 { 1588 MachineClass *mc = MACHINE_CLASS(oc); 1589 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1590 1591 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1592 amc->soc_name = "ast2500-a1"; 1593 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1594 amc->hw_strap2 = 0; 1595 amc->fmc_model = "n25q256a"; 1596 amc->spi_model = "mx25l25635e"; 1597 amc->num_cs = 2; 1598 amc->i2c_init = tiogapass_bmc_i2c_init; 1599 mc->auto_create_sdcard = true; 1600 mc->default_ram_size = 1 * GiB; 1601 aspeed_machine_class_init_cpus_defaults(mc); 1602 }; 1603 1604 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, 1605 const void *data) 1606 { 1607 MachineClass *mc = MACHINE_CLASS(oc); 1608 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1609 1610 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1611 amc->soc_name = "ast2500-a1"; 1612 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1613 amc->fmc_model = "mx66l1g45g"; 1614 amc->spi_model = "mx66l1g45g"; 1615 amc->num_cs = 2; 1616 amc->i2c_init = sonorapass_bmc_i2c_init; 1617 mc->auto_create_sdcard = true; 1618 mc->default_ram_size = 512 * MiB; 1619 aspeed_machine_class_init_cpus_defaults(mc); 1620 }; 1621 1622 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, 1623 const void *data) 1624 { 1625 MachineClass *mc = MACHINE_CLASS(oc); 1626 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1627 1628 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1629 amc->soc_name = "ast2500-a1"; 1630 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1631 amc->fmc_model = "mx25l25635f"; 1632 amc->spi_model = "mx66l1g45g"; 1633 amc->num_cs = 2; 1634 amc->i2c_init = witherspoon_bmc_i2c_init; 1635 mc->auto_create_sdcard = true; 1636 mc->default_ram_size = 512 * MiB; 1637 aspeed_machine_class_init_cpus_defaults(mc); 1638 }; 1639 1640 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, 1641 const void *data) 1642 { 1643 MachineClass *mc = MACHINE_CLASS(oc); 1644 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1645 1646 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1647 amc->soc_name = "ast2600-a3"; 1648 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1649 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1650 amc->fmc_model = "mx66u51235f"; 1651 amc->spi_model = "mx66u51235f"; 1652 amc->num_cs = 1; 1653 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1654 ASPEED_MAC3_ON; 1655 amc->sdhci_wp_inverted = true; 1656 amc->i2c_init = ast2600_evb_i2c_init; 1657 mc->auto_create_sdcard = true; 1658 mc->default_ram_size = 1 * GiB; 1659 aspeed_machine_class_init_cpus_defaults(mc); 1660 aspeed_machine_ast2600_class_emmc_init(oc); 1661 }; 1662 1663 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data) 1664 { 1665 MachineClass *mc = MACHINE_CLASS(oc); 1666 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1667 1668 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1669 amc->soc_name = "ast2500-a1"; 1670 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1671 amc->fmc_model = "n25q512a"; 1672 amc->spi_model = "mx25l25635e"; 1673 amc->num_cs = 2; 1674 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1675 amc->i2c_init = g220a_bmc_i2c_init; 1676 mc->auto_create_sdcard = true; 1677 mc->default_ram_size = 1024 * MiB; 1678 aspeed_machine_class_init_cpus_defaults(mc); 1679 }; 1680 1681 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, 1682 const void *data) 1683 { 1684 MachineClass *mc = MACHINE_CLASS(oc); 1685 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1686 1687 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1688 amc->soc_name = "ast2500-a1"; 1689 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1690 amc->fmc_model = "n25q512a"; 1691 amc->spi_model = "mx25l25635e"; 1692 amc->num_cs = 2; 1693 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1694 amc->i2c_init = fp5280g2_bmc_i2c_init; 1695 mc->auto_create_sdcard = true; 1696 mc->default_ram_size = 512 * MiB; 1697 aspeed_machine_class_init_cpus_defaults(mc); 1698 }; 1699 1700 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) 1701 { 1702 MachineClass *mc = MACHINE_CLASS(oc); 1703 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1704 1705 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1706 amc->soc_name = "ast2600-a3"; 1707 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1708 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1709 amc->fmc_model = "mx66l1g45g"; 1710 amc->spi_model = "mx66l1g45g"; 1711 amc->num_cs = 2; 1712 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1713 amc->i2c_init = rainier_bmc_i2c_init; 1714 mc->auto_create_sdcard = true; 1715 mc->default_ram_size = 1 * GiB; 1716 aspeed_machine_class_init_cpus_defaults(mc); 1717 aspeed_machine_ast2600_class_emmc_init(oc); 1718 }; 1719 1720 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1721 1722 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data) 1723 { 1724 MachineClass *mc = MACHINE_CLASS(oc); 1725 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1726 1727 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1728 amc->soc_name = "ast2600-a3"; 1729 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1730 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1731 amc->fmc_model = "mx66l1g45g"; 1732 amc->spi_model = "mx66l1g45g"; 1733 amc->num_cs = 2; 1734 amc->macs_mask = ASPEED_MAC3_ON; 1735 amc->i2c_init = fuji_bmc_i2c_init; 1736 amc->uart_default = ASPEED_DEV_UART1; 1737 mc->auto_create_sdcard = true; 1738 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1739 aspeed_machine_class_init_cpus_defaults(mc); 1740 }; 1741 1742 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1743 1744 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, 1745 const void *data) 1746 { 1747 MachineClass *mc = MACHINE_CLASS(oc); 1748 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1749 1750 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1751 amc->soc_name = "ast2600-a3"; 1752 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1753 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1754 amc->fmc_model = "w25q01jvq"; 1755 amc->spi_model = NULL; 1756 amc->num_cs = 2; 1757 amc->macs_mask = ASPEED_MAC2_ON; 1758 amc->i2c_init = bletchley_bmc_i2c_init; 1759 mc->auto_create_sdcard = true; 1760 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1761 aspeed_machine_class_init_cpus_defaults(mc); 1762 } 1763 1764 static void aspeed_machine_catalina_class_init(ObjectClass *oc, 1765 const void *data) 1766 { 1767 MachineClass *mc = MACHINE_CLASS(oc); 1768 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1769 1770 mc->desc = "Facebook Catalina BMC (Cortex-A7)"; 1771 amc->soc_name = "ast2600-a3"; 1772 amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; 1773 amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; 1774 amc->fmc_model = "w25q01jvq"; 1775 amc->spi_model = NULL; 1776 amc->num_cs = 2; 1777 amc->macs_mask = ASPEED_MAC2_ON; 1778 amc->i2c_init = catalina_bmc_i2c_init; 1779 mc->auto_create_sdcard = true; 1780 mc->default_ram_size = CATALINA_BMC_RAM_SIZE; 1781 aspeed_machine_class_init_cpus_defaults(mc); 1782 aspeed_machine_ast2600_class_emmc_init(oc); 1783 } 1784 1785 static void fby35_reset(MachineState *state, ResetType type) 1786 { 1787 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1788 AspeedGPIOState *gpio = &bmc->soc->gpio; 1789 1790 qemu_devices_reset(type); 1791 1792 /* Board ID: 7 (Class-1, 4 slots) */ 1793 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1794 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1795 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1796 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1797 1798 /* Slot presence pins, inverse polarity. (False means present) */ 1799 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1800 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1801 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1802 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1803 1804 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1805 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1806 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1807 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1808 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1809 } 1810 1811 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data) 1812 { 1813 MachineClass *mc = MACHINE_CLASS(oc); 1814 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1815 1816 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1817 mc->reset = fby35_reset; 1818 amc->fmc_model = "mx66l1g45g"; 1819 amc->num_cs = 2; 1820 amc->macs_mask = ASPEED_MAC3_ON; 1821 amc->i2c_init = fby35_i2c_init; 1822 mc->auto_create_sdcard = true; 1823 /* FIXME: Replace this macro with something more general */ 1824 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1825 aspeed_machine_class_init_cpus_defaults(mc); 1826 } 1827 1828 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1829 /* Main SYSCLK frequency in Hz (200MHz) */ 1830 #define SYSCLK_FRQ 200000000ULL 1831 1832 static void aspeed_minibmc_machine_init(MachineState *machine) 1833 { 1834 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1835 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1836 Clock *sysclk; 1837 1838 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1839 clock_set_hz(sysclk, SYSCLK_FRQ); 1840 1841 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1842 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1843 object_unref(OBJECT(bmc->soc)); 1844 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1845 1846 object_property_set_link(OBJECT(bmc->soc), "memory", 1847 OBJECT(get_system_memory()), &error_abort); 1848 connect_serial_hds_to_uarts(bmc); 1849 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1850 1851 if (defaults_enabled()) { 1852 aspeed_board_init_flashes(&bmc->soc->fmc, 1853 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1854 amc->num_cs, 1855 0); 1856 1857 aspeed_board_init_flashes(&bmc->soc->spi[0], 1858 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1859 amc->num_cs, amc->num_cs); 1860 1861 aspeed_board_init_flashes(&bmc->soc->spi[1], 1862 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1863 amc->num_cs, (amc->num_cs * 2)); 1864 } 1865 1866 if (amc->i2c_init) { 1867 amc->i2c_init(bmc); 1868 } 1869 1870 armv7m_load_kernel(ARM_CPU(first_cpu), 1871 machine->kernel_filename, 1872 0, 1873 AST1030_INTERNAL_FLASH_SIZE); 1874 } 1875 1876 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1877 { 1878 AspeedSoCState *soc = bmc->soc; 1879 1880 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1881 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1882 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1883 1884 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1885 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1886 } 1887 1888 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1889 const void *data) 1890 { 1891 MachineClass *mc = MACHINE_CLASS(oc); 1892 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1893 1894 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1895 amc->soc_name = "ast1030-a1"; 1896 amc->hw_strap1 = 0; 1897 amc->hw_strap2 = 0; 1898 mc->init = aspeed_minibmc_machine_init; 1899 amc->i2c_init = ast1030_evb_i2c_init; 1900 mc->default_ram_size = 0; 1901 amc->fmc_model = "w25q80bl"; 1902 amc->spi_model = "w25q256"; 1903 amc->num_cs = 2; 1904 amc->macs_mask = 0; 1905 aspeed_machine_class_init_cpus_defaults(mc); 1906 } 1907 1908 #ifdef TARGET_AARCH64 1909 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1910 { 1911 AspeedSoCState *soc = bmc->soc; 1912 1913 /* LM75 is compatible with TMP105 driver */ 1914 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1915 TYPE_TMP105, 0x4d); 1916 } 1917 1918 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, 1919 const void *data) 1920 { 1921 MachineClass *mc = MACHINE_CLASS(oc); 1922 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1923 1924 mc->alias = "ast2700-evb"; 1925 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; 1926 amc->soc_name = "ast2700-a0"; 1927 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1928 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1929 amc->fmc_model = "w25q01jvq"; 1930 amc->spi_model = "w25q512jv"; 1931 amc->num_cs = 2; 1932 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1933 amc->uart_default = ASPEED_DEV_UART12; 1934 amc->i2c_init = ast2700_evb_i2c_init; 1935 amc->vbootrom = true; 1936 mc->auto_create_sdcard = true; 1937 mc->default_ram_size = 1 * GiB; 1938 aspeed_machine_class_init_cpus_defaults(mc); 1939 } 1940 1941 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, 1942 const void *data) 1943 { 1944 MachineClass *mc = MACHINE_CLASS(oc); 1945 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1946 1947 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; 1948 amc->soc_name = "ast2700-a1"; 1949 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1950 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1951 amc->fmc_model = "w25q01jvq"; 1952 amc->spi_model = "w25q512jv"; 1953 amc->num_cs = 2; 1954 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1955 amc->uart_default = ASPEED_DEV_UART12; 1956 amc->i2c_init = ast2700_evb_i2c_init; 1957 amc->vbootrom = true; 1958 mc->auto_create_sdcard = true; 1959 mc->default_ram_size = 1 * GiB; 1960 aspeed_machine_class_init_cpus_defaults(mc); 1961 } 1962 #endif 1963 1964 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1965 const void *data) 1966 { 1967 MachineClass *mc = MACHINE_CLASS(oc); 1968 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1969 1970 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1971 amc->soc_name = "ast2600-a3"; 1972 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1973 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1974 amc->fmc_model = "n25q512a"; 1975 amc->spi_model = "n25q512a"; 1976 amc->num_cs = 2; 1977 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1978 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1979 mc->auto_create_sdcard = true; 1980 mc->default_ram_size = 1 * GiB; 1981 aspeed_machine_class_init_cpus_defaults(mc); 1982 }; 1983 1984 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1985 const void *data) 1986 { 1987 MachineClass *mc = MACHINE_CLASS(oc); 1988 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1989 1990 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1991 amc->soc_name = "ast2600-a3"; 1992 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1993 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1994 amc->fmc_model = "n25q512a"; 1995 amc->spi_model = "n25q512a"; 1996 amc->num_cs = 2; 1997 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1998 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1999 mc->auto_create_sdcard = true; 2000 mc->default_ram_size = 1 * GiB; 2001 aspeed_machine_class_init_cpus_defaults(mc); 2002 }; 2003 2004 static const TypeInfo aspeed_machine_types[] = { 2005 { 2006 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 2007 .parent = TYPE_ASPEED_MACHINE, 2008 .class_init = aspeed_machine_palmetto_class_init, 2009 }, { 2010 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 2011 .parent = TYPE_ASPEED_MACHINE, 2012 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 2013 }, { 2014 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 2015 .parent = TYPE_ASPEED_MACHINE, 2016 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 2017 }, { 2018 .name = MACHINE_TYPE_NAME("ast2500-evb"), 2019 .parent = TYPE_ASPEED_MACHINE, 2020 .class_init = aspeed_machine_ast2500_evb_class_init, 2021 }, { 2022 .name = MACHINE_TYPE_NAME("romulus-bmc"), 2023 .parent = TYPE_ASPEED_MACHINE, 2024 .class_init = aspeed_machine_romulus_class_init, 2025 }, { 2026 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 2027 .parent = TYPE_ASPEED_MACHINE, 2028 .class_init = aspeed_machine_sonorapass_class_init, 2029 }, { 2030 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 2031 .parent = TYPE_ASPEED_MACHINE, 2032 .class_init = aspeed_machine_witherspoon_class_init, 2033 }, { 2034 .name = MACHINE_TYPE_NAME("ast2600-evb"), 2035 .parent = TYPE_ASPEED_MACHINE, 2036 .class_init = aspeed_machine_ast2600_evb_class_init, 2037 }, { 2038 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 2039 .parent = TYPE_ASPEED_MACHINE, 2040 .class_init = aspeed_machine_yosemitev2_class_init, 2041 }, { 2042 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 2043 .parent = TYPE_ASPEED_MACHINE, 2044 .class_init = aspeed_machine_tiogapass_class_init, 2045 }, { 2046 .name = MACHINE_TYPE_NAME("g220a-bmc"), 2047 .parent = TYPE_ASPEED_MACHINE, 2048 .class_init = aspeed_machine_g220a_class_init, 2049 }, { 2050 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 2051 .parent = TYPE_ASPEED_MACHINE, 2052 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 2053 }, { 2054 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 2055 .parent = TYPE_ASPEED_MACHINE, 2056 .class_init = aspeed_machine_qcom_firework_class_init, 2057 }, { 2058 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 2059 .parent = TYPE_ASPEED_MACHINE, 2060 .class_init = aspeed_machine_fp5280g2_class_init, 2061 }, { 2062 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 2063 .parent = TYPE_ASPEED_MACHINE, 2064 .class_init = aspeed_machine_quanta_q71l_class_init, 2065 }, { 2066 .name = MACHINE_TYPE_NAME("rainier-bmc"), 2067 .parent = TYPE_ASPEED_MACHINE, 2068 .class_init = aspeed_machine_rainier_class_init, 2069 }, { 2070 .name = MACHINE_TYPE_NAME("fuji-bmc"), 2071 .parent = TYPE_ASPEED_MACHINE, 2072 .class_init = aspeed_machine_fuji_class_init, 2073 }, { 2074 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 2075 .parent = TYPE_ASPEED_MACHINE, 2076 .class_init = aspeed_machine_bletchley_class_init, 2077 }, { 2078 .name = MACHINE_TYPE_NAME("catalina-bmc"), 2079 .parent = TYPE_ASPEED_MACHINE, 2080 .class_init = aspeed_machine_catalina_class_init, 2081 }, { 2082 .name = MACHINE_TYPE_NAME("fby35-bmc"), 2083 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 2084 .class_init = aspeed_machine_fby35_class_init, 2085 }, { 2086 .name = MACHINE_TYPE_NAME("ast1030-evb"), 2087 .parent = TYPE_ASPEED_MACHINE, 2088 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 2089 #ifdef TARGET_AARCH64 2090 }, { 2091 .name = MACHINE_TYPE_NAME("ast2700a0-evb"), 2092 .parent = TYPE_ASPEED_MACHINE, 2093 .class_init = aspeed_machine_ast2700a0_evb_class_init, 2094 }, { 2095 .name = MACHINE_TYPE_NAME("ast2700a1-evb"), 2096 .parent = TYPE_ASPEED_MACHINE, 2097 .class_init = aspeed_machine_ast2700a1_evb_class_init, 2098 #endif 2099 }, { 2100 .name = TYPE_ASPEED_MACHINE, 2101 .parent = TYPE_MACHINE, 2102 .instance_size = sizeof(AspeedMachineState), 2103 .instance_init = aspeed_machine_instance_init, 2104 .class_size = sizeof(AspeedMachineClass), 2105 .class_init = aspeed_machine_class_init, 2106 .abstract = true, 2107 } 2108 }; 2109 2110 DEFINE_TYPES(aspeed_machine_types) 2111