1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/smbus_eeprom.h" 18 #include "hw/misc/pca9552.h" 19 #include "hw/misc/tmp105.h" 20 #include "hw/misc/led.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/block-backend.h" 23 #include "hw/loader.h" 24 #include "qemu/error-report.h" 25 #include "qemu/units.h" 26 27 static struct arm_boot_info aspeed_board_binfo = { 28 .board_id = -1, /* device-tree-only board */ 29 }; 30 31 struct AspeedMachineState { 32 /* Private */ 33 MachineState parent_obj; 34 /* Public */ 35 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 bool mmio_exec; 40 char *fmc_model; 41 char *spi_model; 42 }; 43 44 /* Palmetto hardware value: 0x120CE416 */ 45 #define PALMETTO_BMC_HW_STRAP1 ( \ 46 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 47 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 48 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 49 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 50 SCU_HW_STRAP_VGA_CLASS_CODE | \ 51 SCU_HW_STRAP_LPC_RESET_PIN | \ 52 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 53 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 54 SCU_HW_STRAP_SPI_WIDTH | \ 55 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 56 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 57 58 /* TODO: Find the actual hardware value */ 59 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* AST2500 evb hardware value: 0xF100C2E6 */ 73 #define AST2500_EVB_HW_STRAP1 (( \ 74 AST2500_HW_STRAP1_DEFAULTS | \ 75 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 76 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 77 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 78 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 79 SCU_HW_STRAP_MAC1_RGMII | \ 80 SCU_HW_STRAP_MAC0_RGMII) & \ 81 ~SCU_HW_STRAP_2ND_BOOT_WDT) 82 83 /* Romulus hardware value: 0xF10AD206 */ 84 #define ROMULUS_BMC_HW_STRAP1 ( \ 85 AST2500_HW_STRAP1_DEFAULTS | \ 86 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 87 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 88 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 89 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 90 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 91 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 92 93 /* Sonorapass hardware value: 0xF100D216 */ 94 #define SONORAPASS_BMC_HW_STRAP1 ( \ 95 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 96 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 97 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 98 SCU_AST2500_HW_STRAP_RESERVED28 | \ 99 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 100 SCU_HW_STRAP_VGA_CLASS_CODE | \ 101 SCU_HW_STRAP_LPC_RESET_PIN | \ 102 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 103 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 104 SCU_HW_STRAP_VGA_BIOS_ROM | \ 105 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 106 SCU_AST2500_HW_STRAP_RESERVED1) 107 108 /* Swift hardware value: 0xF11AD206 */ 109 #define SWIFT_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_H_PLL_BYPASS_EN | \ 116 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 117 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 118 119 #define G220A_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_2ND_BOOT_WDT | \ 126 SCU_HW_STRAP_VGA_CLASS_CODE | \ 127 SCU_HW_STRAP_LPC_RESET_PIN | \ 128 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 129 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 134 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 135 136 /* Quanta-Q71l hardware value */ 137 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 138 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 139 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 140 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 141 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 142 SCU_HW_STRAP_VGA_CLASS_CODE | \ 143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 144 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 145 SCU_HW_STRAP_SPI_WIDTH | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 147 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 148 149 /* AST2600 evb hardware value */ 150 #define AST2600_EVB_HW_STRAP1 0x000000C0 151 #define AST2600_EVB_HW_STRAP2 0x00000003 152 153 /* Tacoma hardware value */ 154 #define TACOMA_BMC_HW_STRAP1 0x00000000 155 #define TACOMA_BMC_HW_STRAP2 0x00000040 156 157 /* Rainier hardware value: (QEMU prototype) */ 158 #define RAINIER_BMC_HW_STRAP1 0x00000000 159 #define RAINIER_BMC_HW_STRAP2 0x00000000 160 161 /* 162 * The max ram region is for firmwares that scan the address space 163 * with load/store to guess how much RAM the SoC has. 164 */ 165 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 166 { 167 return 0; 168 } 169 170 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 171 unsigned size) 172 { 173 /* Discard writes */ 174 } 175 176 static const MemoryRegionOps max_ram_ops = { 177 .read = max_ram_read, 178 .write = max_ram_write, 179 .endianness = DEVICE_NATIVE_ENDIAN, 180 }; 181 182 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 183 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 184 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 185 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 186 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 187 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 188 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 189 190 static void aspeed_write_smpboot(ARMCPU *cpu, 191 const struct arm_boot_info *info) 192 { 193 static const uint32_t poll_mailbox_ready[] = { 194 /* 195 * r2 = per-cpu go sign value 196 * r1 = AST_SMP_MBOX_FIELD_ENTRY 197 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 198 */ 199 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 200 0xe21000ff, /* ands r0, r0, #255 */ 201 0xe59f201c, /* ldr r2, [pc, #28] */ 202 0xe1822000, /* orr r2, r2, r0 */ 203 204 0xe59f1018, /* ldr r1, [pc, #24] */ 205 0xe59f0018, /* ldr r0, [pc, #24] */ 206 207 0xe320f002, /* wfe */ 208 0xe5904000, /* ldr r4, [r0] */ 209 0xe1520004, /* cmp r2, r4 */ 210 0x1afffffb, /* bne <wfe> */ 211 0xe591f000, /* ldr pc, [r1] */ 212 AST_SMP_MBOX_GOSIGN, 213 AST_SMP_MBOX_FIELD_ENTRY, 214 AST_SMP_MBOX_FIELD_GOSIGN, 215 }; 216 217 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 218 sizeof(poll_mailbox_ready), 219 info->smp_loader_start); 220 } 221 222 static void aspeed_reset_secondary(ARMCPU *cpu, 223 const struct arm_boot_info *info) 224 { 225 AddressSpace *as = arm_boot_address_space(cpu, info); 226 CPUState *cs = CPU(cpu); 227 228 /* info->smp_bootreg_addr */ 229 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 230 MEMTXATTRS_UNSPECIFIED, NULL); 231 cpu_set_pc(cs, info->smp_loader_start); 232 } 233 234 #define FIRMWARE_ADDR 0x0 235 236 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 237 Error **errp) 238 { 239 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 240 uint8_t *storage; 241 int64_t size; 242 243 /* The block backend size should have already been 'validated' by 244 * the creation of the m25p80 object. 245 */ 246 size = blk_getlength(blk); 247 if (size <= 0) { 248 error_setg(errp, "failed to get flash size"); 249 return; 250 } 251 252 if (rom_size > size) { 253 rom_size = size; 254 } 255 256 storage = g_new0(uint8_t, rom_size); 257 if (blk_pread(blk, 0, storage, rom_size) < 0) { 258 error_setg(errp, "failed to read the initial flash content"); 259 return; 260 } 261 262 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 263 g_free(storage); 264 } 265 266 static void aspeed_board_init_flashes(AspeedSMCState *s, 267 const char *flashtype) 268 { 269 int i ; 270 271 for (i = 0; i < s->num_cs; ++i) { 272 AspeedSMCFlash *fl = &s->flashes[i]; 273 DriveInfo *dinfo = drive_get_next(IF_MTD); 274 qemu_irq cs_line; 275 276 fl->flash = qdev_new(flashtype); 277 if (dinfo) { 278 qdev_prop_set_drive(fl->flash, "drive", 279 blk_by_legacy_dinfo(dinfo)); 280 } 281 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 282 283 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 284 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 285 } 286 } 287 288 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 289 { 290 DeviceState *card; 291 292 if (!dinfo) { 293 return; 294 } 295 card = qdev_new(TYPE_SD_CARD); 296 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 297 &error_fatal); 298 qdev_realize_and_unref(card, 299 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 300 &error_fatal); 301 } 302 303 static void aspeed_machine_init(MachineState *machine) 304 { 305 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 306 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 307 AspeedSoCClass *sc; 308 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 309 ram_addr_t max_ram_size; 310 int i; 311 NICInfo *nd = &nd_table[0]; 312 313 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 314 4 * GiB); 315 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 316 317 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 318 319 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 320 321 /* 322 * This will error out if isize is not supported by memory controller. 323 */ 324 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 325 &error_fatal); 326 327 for (i = 0; i < sc->macs_num; i++) { 328 if ((amc->macs_mask & (1 << i)) && nd->used) { 329 qemu_check_nic_model(nd, TYPE_FTGMAC100); 330 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 331 nd++; 332 } 333 } 334 335 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 336 &error_abort); 337 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 338 &error_abort); 339 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 340 &error_abort); 341 object_property_set_link(OBJECT(&bmc->soc), "dram", 342 OBJECT(machine->ram), &error_abort); 343 if (machine->kernel_filename) { 344 /* 345 * When booting with a -kernel command line there is no u-boot 346 * that runs to unlock the SCU. In this case set the default to 347 * be unlocked as the kernel expects 348 */ 349 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 350 ASPEED_SCU_PROT_KEY, &error_abort); 351 } 352 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 353 354 memory_region_add_subregion(get_system_memory(), 355 sc->memmap[ASPEED_DEV_SDRAM], 356 &bmc->ram_container); 357 358 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 359 &error_abort); 360 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 361 "max_ram", max_ram_size - machine->ram_size); 362 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 363 364 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? 365 bmc->fmc_model : amc->fmc_model); 366 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? 367 bmc->spi_model : amc->spi_model); 368 369 /* Install first FMC flash content as a boot rom. */ 370 if (drive0) { 371 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 372 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 373 374 /* 375 * create a ROM region using the default mapping window size of 376 * the flash module. The window size is 64MB for the AST2400 377 * SoC and 128MB for the AST2500 SoC, which is twice as big as 378 * needed by the flash modules of the Aspeed machines. 379 */ 380 if (ASPEED_MACHINE(machine)->mmio_exec) { 381 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 382 &fl->mmio, 0, fl->size); 383 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 384 boot_rom); 385 } else { 386 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 387 fl->size, &error_abort); 388 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 389 boot_rom); 390 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 391 } 392 } 393 394 if (machine->kernel_filename && sc->num_cpus > 1) { 395 /* With no u-boot we must set up a boot stub for the secondary CPU */ 396 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 397 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 398 0x80, &error_abort); 399 memory_region_add_subregion(get_system_memory(), 400 AST_SMP_MAILBOX_BASE, smpboot); 401 402 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 403 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 404 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 405 } 406 407 aspeed_board_binfo.ram_size = machine->ram_size; 408 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 409 aspeed_board_binfo.nb_cpus = sc->num_cpus; 410 411 if (amc->i2c_init) { 412 amc->i2c_init(bmc); 413 } 414 415 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 416 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 417 } 418 419 if (bmc->soc.emmc.num_slots) { 420 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 421 } 422 423 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 424 } 425 426 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 427 { 428 AspeedSoCState *soc = &bmc->soc; 429 DeviceState *dev; 430 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 431 432 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 433 * enough to provide basic RTC features. Alarms will be missing */ 434 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 435 436 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 437 eeprom_buf); 438 439 /* add a TMP423 temperature sensor */ 440 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 441 "tmp423", 0x4c)); 442 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 443 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 444 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 445 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 446 } 447 448 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 449 { 450 AspeedSoCState *soc = &bmc->soc; 451 452 /* 453 * The quanta-q71l platform expects tmp75s which are compatible with 454 * tmp105s. 455 */ 456 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 457 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 458 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 459 460 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 461 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 462 /* TODO: Add Memory Riser i2c mux and eeproms. */ 463 464 /* TODO: i2c-2: pca9546@74 */ 465 /* TODO: i2c-2: pca9548@77 */ 466 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 467 /* TODO: i2c-7: Add pca9546@70 */ 468 /* - i2c@0: pmbus@59 */ 469 /* - i2c@1: pmbus@58 */ 470 /* - i2c@2: pmbus@58 */ 471 /* - i2c@3: pmbus@59 */ 472 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 473 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 474 } 475 476 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 477 { 478 AspeedSoCState *soc = &bmc->soc; 479 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 480 481 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 482 eeprom_buf); 483 484 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 486 TYPE_TMP105, 0x4d); 487 488 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 489 * plugged on the I2C bus header */ 490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 491 } 492 493 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 494 { 495 /* Start with some devices on our I2C busses */ 496 ast2500_evb_i2c_init(bmc); 497 } 498 499 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 500 { 501 AspeedSoCState *soc = &bmc->soc; 502 503 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 504 * good enough */ 505 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 506 } 507 508 static void swift_bmc_i2c_init(AspeedMachineState *bmc) 509 { 510 AspeedSoCState *soc = &bmc->soc; 511 512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); 513 514 /* The swift board expects a TMP275 but a TMP105 is compatible */ 515 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); 516 /* The swift board expects a pca9551 but a pca9552 is compatible */ 517 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); 518 519 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); 521 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 522 523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 524 /* The swift board expects a pca9539 but a pca9552 is compatible */ 525 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); 526 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 528 /* The swift board expects a pca9539 but a pca9552 is compatible */ 529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", 530 0x74); 531 532 /* The swift board expects a TMP275 but a TMP105 is compatible */ 533 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); 534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); 535 } 536 537 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 538 { 539 AspeedSoCState *soc = &bmc->soc; 540 541 /* bus 2 : */ 542 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 544 /* bus 2 : pca9546 @ 0x73 */ 545 546 /* bus 3 : pca9548 @ 0x70 */ 547 548 /* bus 4 : */ 549 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 550 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 551 eeprom4_54); 552 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); 554 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); 556 557 /* bus 6 : */ 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 559 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 560 /* bus 6 : pca9546 @ 0x73 */ 561 562 /* bus 8 : */ 563 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 564 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 565 eeprom8_56); 566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); 567 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 568 /* bus 8 : adc128d818 @ 0x1d */ 569 /* bus 8 : adc128d818 @ 0x1f */ 570 571 /* 572 * bus 13 : pca9548 @ 0x71 573 * - channel 3: 574 * - tmm421 @ 0x4c 575 * - tmp421 @ 0x4e 576 * - tmp421 @ 0x4f 577 */ 578 579 } 580 581 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 582 { 583 static const struct { 584 unsigned gpio_id; 585 LEDColor color; 586 const char *description; 587 bool gpio_polarity; 588 } pca1_leds[] = { 589 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 590 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 591 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 592 }; 593 AspeedSoCState *soc = &bmc->soc; 594 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 595 DeviceState *dev; 596 LEDState *led; 597 598 /* Bus 3: TODO bmp280@77 */ 599 /* Bus 3: TODO max31785@52 */ 600 /* Bus 3: TODO dps310@76 */ 601 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 602 qdev_prop_set_string(dev, "description", "pca1"); 603 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 604 aspeed_i2c_get_bus(&soc->i2c, 3), 605 &error_fatal); 606 607 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 608 led = led_create_simple(OBJECT(bmc), 609 pca1_leds[i].gpio_polarity, 610 pca1_leds[i].color, 611 pca1_leds[i].description); 612 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 613 qdev_get_gpio_in(DEVICE(led), 0)); 614 } 615 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 616 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 617 618 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 620 0x4a); 621 622 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 623 * good enough */ 624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 625 626 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 627 eeprom_buf); 628 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 629 qdev_prop_set_string(dev, "description", "pca0"); 630 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 631 aspeed_i2c_get_bus(&soc->i2c, 11), 632 &error_fatal); 633 /* Bus 11: TODO ucd90160@64 */ 634 } 635 636 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 637 { 638 AspeedSoCState *soc = &bmc->soc; 639 DeviceState *dev; 640 641 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 642 "emc1413", 0x4c)); 643 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 644 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 645 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 646 647 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 648 "emc1413", 0x4c)); 649 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 650 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 651 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 652 653 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 654 "emc1413", 0x4c)); 655 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 656 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 657 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 658 659 static uint8_t eeprom_buf[2 * 1024] = { 660 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 661 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 662 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 663 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 664 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 665 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 666 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 667 }; 668 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 669 eeprom_buf); 670 } 671 672 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 673 { 674 AspeedSoCState *soc = &bmc->soc; 675 676 /* The rainier expects a TMP275 but a TMP105 is compatible */ 677 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 678 0x48); 679 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 680 0x49); 681 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 682 0x4a); 683 684 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 685 0x48); 686 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 687 0x49); 688 689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 690 0x48); 691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 692 0x4a); 693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 694 0x4b); 695 696 /* Bus 7: TODO dps310@76 */ 697 /* Bus 7: TODO max31785@52 */ 698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); 699 /* Bus 7: TODO si7021-a20@20 */ 700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 701 0x48); 702 703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 704 0x48); 705 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 706 0x4a); 707 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); 708 /* Bus 8: ucd90320@11 */ 709 /* Bus 8: ucd90320@b */ 710 /* Bus 8: ucd90320@c */ 711 712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 713 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 714 715 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 716 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 717 718 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 719 0x48); 720 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 721 0x49); 722 } 723 724 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 725 { 726 return ASPEED_MACHINE(obj)->mmio_exec; 727 } 728 729 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 730 { 731 ASPEED_MACHINE(obj)->mmio_exec = value; 732 } 733 734 static void aspeed_machine_instance_init(Object *obj) 735 { 736 ASPEED_MACHINE(obj)->mmio_exec = false; 737 } 738 739 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 740 { 741 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 742 return g_strdup(bmc->fmc_model); 743 } 744 745 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 746 { 747 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 748 749 g_free(bmc->fmc_model); 750 bmc->fmc_model = g_strdup(value); 751 } 752 753 static char *aspeed_get_spi_model(Object *obj, Error **errp) 754 { 755 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 756 return g_strdup(bmc->spi_model); 757 } 758 759 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 760 { 761 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 762 763 g_free(bmc->spi_model); 764 bmc->spi_model = g_strdup(value); 765 } 766 767 static void aspeed_machine_class_props_init(ObjectClass *oc) 768 { 769 object_class_property_add_bool(oc, "execute-in-place", 770 aspeed_get_mmio_exec, 771 aspeed_set_mmio_exec); 772 object_class_property_set_description(oc, "execute-in-place", 773 "boot directly from CE0 flash device"); 774 775 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 776 aspeed_set_fmc_model); 777 object_class_property_set_description(oc, "fmc-model", 778 "Change the FMC Flash model"); 779 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 780 aspeed_set_spi_model); 781 object_class_property_set_description(oc, "spi-model", 782 "Change the SPI Flash model"); 783 } 784 785 static int aspeed_soc_num_cpus(const char *soc_name) 786 { 787 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 788 return sc->num_cpus; 789 } 790 791 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 792 { 793 MachineClass *mc = MACHINE_CLASS(oc); 794 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 795 796 mc->init = aspeed_machine_init; 797 mc->no_floppy = 1; 798 mc->no_cdrom = 1; 799 mc->no_parallel = 1; 800 mc->default_ram_id = "ram"; 801 amc->macs_mask = ASPEED_MAC0_ON; 802 803 aspeed_machine_class_props_init(oc); 804 } 805 806 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 807 { 808 MachineClass *mc = MACHINE_CLASS(oc); 809 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 810 811 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 812 amc->soc_name = "ast2400-a1"; 813 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 814 amc->fmc_model = "n25q256a"; 815 amc->spi_model = "mx25l25635e"; 816 amc->num_cs = 1; 817 amc->i2c_init = palmetto_bmc_i2c_init; 818 mc->default_ram_size = 256 * MiB; 819 mc->default_cpus = mc->min_cpus = mc->max_cpus = 820 aspeed_soc_num_cpus(amc->soc_name); 821 }; 822 823 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 824 { 825 MachineClass *mc = MACHINE_CLASS(oc); 826 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 827 828 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 829 amc->soc_name = "ast2400-a1"; 830 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 831 amc->fmc_model = "n25q256a"; 832 amc->spi_model = "mx25l25635e"; 833 amc->num_cs = 1; 834 amc->i2c_init = quanta_q71l_bmc_i2c_init; 835 mc->default_ram_size = 128 * MiB; 836 mc->default_cpus = mc->min_cpus = mc->max_cpus = 837 aspeed_soc_num_cpus(amc->soc_name); 838 } 839 840 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 841 void *data) 842 { 843 MachineClass *mc = MACHINE_CLASS(oc); 844 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 845 846 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 847 amc->soc_name = "ast2400-a1"; 848 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 849 amc->fmc_model = "mx25l25635e"; 850 amc->spi_model = "mx25l25635e"; 851 amc->num_cs = 1; 852 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 853 amc->i2c_init = palmetto_bmc_i2c_init; 854 mc->default_ram_size = 256 * MiB; 855 } 856 857 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 858 { 859 MachineClass *mc = MACHINE_CLASS(oc); 860 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 861 862 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 863 amc->soc_name = "ast2500-a1"; 864 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 865 amc->fmc_model = "w25q256"; 866 amc->spi_model = "mx25l25635e"; 867 amc->num_cs = 1; 868 amc->i2c_init = ast2500_evb_i2c_init; 869 mc->default_ram_size = 512 * MiB; 870 mc->default_cpus = mc->min_cpus = mc->max_cpus = 871 aspeed_soc_num_cpus(amc->soc_name); 872 }; 873 874 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 875 { 876 MachineClass *mc = MACHINE_CLASS(oc); 877 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 878 879 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 880 amc->soc_name = "ast2500-a1"; 881 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 882 amc->fmc_model = "n25q256a"; 883 amc->spi_model = "mx66l1g45g"; 884 amc->num_cs = 2; 885 amc->i2c_init = romulus_bmc_i2c_init; 886 mc->default_ram_size = 512 * MiB; 887 mc->default_cpus = mc->min_cpus = mc->max_cpus = 888 aspeed_soc_num_cpus(amc->soc_name); 889 }; 890 891 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 892 { 893 MachineClass *mc = MACHINE_CLASS(oc); 894 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 895 896 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 897 amc->soc_name = "ast2500-a1"; 898 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 899 amc->fmc_model = "mx66l1g45g"; 900 amc->spi_model = "mx66l1g45g"; 901 amc->num_cs = 2; 902 amc->i2c_init = sonorapass_bmc_i2c_init; 903 mc->default_ram_size = 512 * MiB; 904 mc->default_cpus = mc->min_cpus = mc->max_cpus = 905 aspeed_soc_num_cpus(amc->soc_name); 906 }; 907 908 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 909 { 910 MachineClass *mc = MACHINE_CLASS(oc); 911 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 912 913 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 914 amc->soc_name = "ast2500-a1"; 915 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 916 amc->fmc_model = "mx66l1g45g"; 917 amc->spi_model = "mx66l1g45g"; 918 amc->num_cs = 2; 919 amc->i2c_init = swift_bmc_i2c_init; 920 mc->default_ram_size = 512 * MiB; 921 mc->default_cpus = mc->min_cpus = mc->max_cpus = 922 aspeed_soc_num_cpus(amc->soc_name); 923 924 mc->deprecation_reason = "redundant system. Please use a similar " 925 "OpenPOWER BMC, Witherspoon or Romulus."; 926 }; 927 928 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 929 { 930 MachineClass *mc = MACHINE_CLASS(oc); 931 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 932 933 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 934 amc->soc_name = "ast2500-a1"; 935 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 936 amc->fmc_model = "mx25l25635e"; 937 amc->spi_model = "mx66l1g45g"; 938 amc->num_cs = 2; 939 amc->i2c_init = witherspoon_bmc_i2c_init; 940 mc->default_ram_size = 512 * MiB; 941 mc->default_cpus = mc->min_cpus = mc->max_cpus = 942 aspeed_soc_num_cpus(amc->soc_name); 943 }; 944 945 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 946 { 947 MachineClass *mc = MACHINE_CLASS(oc); 948 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 949 950 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 951 amc->soc_name = "ast2600-a1"; 952 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 953 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 954 amc->fmc_model = "w25q512jv"; 955 amc->spi_model = "mx66u51235f"; 956 amc->num_cs = 1; 957 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 958 amc->i2c_init = ast2600_evb_i2c_init; 959 mc->default_ram_size = 1 * GiB; 960 mc->default_cpus = mc->min_cpus = mc->max_cpus = 961 aspeed_soc_num_cpus(amc->soc_name); 962 }; 963 964 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 965 { 966 MachineClass *mc = MACHINE_CLASS(oc); 967 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 968 969 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 970 amc->soc_name = "ast2600-a1"; 971 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 972 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 973 amc->fmc_model = "mx66l1g45g"; 974 amc->spi_model = "mx66l1g45g"; 975 amc->num_cs = 2; 976 amc->macs_mask = ASPEED_MAC2_ON; 977 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 978 mc->default_ram_size = 1 * GiB; 979 mc->default_cpus = mc->min_cpus = mc->max_cpus = 980 aspeed_soc_num_cpus(amc->soc_name); 981 }; 982 983 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 984 { 985 MachineClass *mc = MACHINE_CLASS(oc); 986 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 987 988 mc->desc = "Bytedance G220A BMC (ARM1176)"; 989 amc->soc_name = "ast2500-a1"; 990 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 991 amc->fmc_model = "n25q512a"; 992 amc->spi_model = "mx25l25635e"; 993 amc->num_cs = 2; 994 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON; 995 amc->i2c_init = g220a_bmc_i2c_init; 996 mc->default_ram_size = 1024 * MiB; 997 mc->default_cpus = mc->min_cpus = mc->max_cpus = 998 aspeed_soc_num_cpus(amc->soc_name); 999 }; 1000 1001 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1002 { 1003 MachineClass *mc = MACHINE_CLASS(oc); 1004 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1005 1006 mc->desc = "IBM Rainier BMC (Cortex A7)"; 1007 amc->soc_name = "ast2600-a1"; 1008 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1009 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1010 amc->fmc_model = "mx66l1g45g"; 1011 amc->spi_model = "mx66l1g45g"; 1012 amc->num_cs = 2; 1013 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1014 amc->i2c_init = rainier_bmc_i2c_init; 1015 mc->default_ram_size = 1 * GiB; 1016 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1017 aspeed_soc_num_cpus(amc->soc_name); 1018 }; 1019 1020 static const TypeInfo aspeed_machine_types[] = { 1021 { 1022 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1023 .parent = TYPE_ASPEED_MACHINE, 1024 .class_init = aspeed_machine_palmetto_class_init, 1025 }, { 1026 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1027 .parent = TYPE_ASPEED_MACHINE, 1028 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1029 }, { 1030 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1031 .parent = TYPE_ASPEED_MACHINE, 1032 .class_init = aspeed_machine_ast2500_evb_class_init, 1033 }, { 1034 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1035 .parent = TYPE_ASPEED_MACHINE, 1036 .class_init = aspeed_machine_romulus_class_init, 1037 }, { 1038 .name = MACHINE_TYPE_NAME("swift-bmc"), 1039 .parent = TYPE_ASPEED_MACHINE, 1040 .class_init = aspeed_machine_swift_class_init, 1041 }, { 1042 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1043 .parent = TYPE_ASPEED_MACHINE, 1044 .class_init = aspeed_machine_sonorapass_class_init, 1045 }, { 1046 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1047 .parent = TYPE_ASPEED_MACHINE, 1048 .class_init = aspeed_machine_witherspoon_class_init, 1049 }, { 1050 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1051 .parent = TYPE_ASPEED_MACHINE, 1052 .class_init = aspeed_machine_ast2600_evb_class_init, 1053 }, { 1054 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1055 .parent = TYPE_ASPEED_MACHINE, 1056 .class_init = aspeed_machine_tacoma_class_init, 1057 }, { 1058 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1059 .parent = TYPE_ASPEED_MACHINE, 1060 .class_init = aspeed_machine_g220a_class_init, 1061 }, { 1062 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1063 .parent = TYPE_ASPEED_MACHINE, 1064 .class_init = aspeed_machine_quanta_q71l_class_init, 1065 }, { 1066 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1067 .parent = TYPE_ASPEED_MACHINE, 1068 .class_init = aspeed_machine_rainier_class_init, 1069 }, { 1070 .name = TYPE_ASPEED_MACHINE, 1071 .parent = TYPE_MACHINE, 1072 .instance_size = sizeof(AspeedMachineState), 1073 .instance_init = aspeed_machine_instance_init, 1074 .class_size = sizeof(AspeedMachineClass), 1075 .class_init = aspeed_machine_class_init, 1076 .abstract = true, 1077 } 1078 }; 1079 1080 DEFINE_TYPES(aspeed_machine_types) 1081