1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/i2c/i2c_mux_pca954x.h" 18 #include "hw/i2c/smbus_eeprom.h" 19 #include "hw/misc/pca9552.h" 20 #include "hw/sensor/tmp105.h" 21 #include "hw/misc/led.h" 22 #include "hw/qdev-properties.h" 23 #include "sysemu/block-backend.h" 24 #include "hw/loader.h" 25 #include "qemu/error-report.h" 26 #include "qemu/units.h" 27 28 static struct arm_boot_info aspeed_board_binfo = { 29 .board_id = -1, /* device-tree-only board */ 30 }; 31 32 struct AspeedMachineState { 33 /* Private */ 34 MachineState parent_obj; 35 /* Public */ 36 37 AspeedSoCState soc; 38 MemoryRegion ram_container; 39 MemoryRegion max_ram; 40 bool mmio_exec; 41 char *fmc_model; 42 char *spi_model; 43 }; 44 45 /* Palmetto hardware value: 0x120CE416 */ 46 #define PALMETTO_BMC_HW_STRAP1 ( \ 47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 49 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 51 SCU_HW_STRAP_VGA_CLASS_CODE | \ 52 SCU_HW_STRAP_LPC_RESET_PIN | \ 53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 55 SCU_HW_STRAP_SPI_WIDTH | \ 56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 58 59 /* TODO: Find the actual hardware value */ 60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* AST2500 evb hardware value: 0xF100C2E6 */ 74 #define AST2500_EVB_HW_STRAP1 (( \ 75 AST2500_HW_STRAP1_DEFAULTS | \ 76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 78 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 80 SCU_HW_STRAP_MAC1_RGMII | \ 81 SCU_HW_STRAP_MAC0_RGMII) & \ 82 ~SCU_HW_STRAP_2ND_BOOT_WDT) 83 84 /* Romulus hardware value: 0xF10AD206 */ 85 #define ROMULUS_BMC_HW_STRAP1 ( \ 86 AST2500_HW_STRAP1_DEFAULTS | \ 87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 89 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 93 94 /* Sonorapass hardware value: 0xF100D216 */ 95 #define SONORAPASS_BMC_HW_STRAP1 ( \ 96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 98 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 99 SCU_AST2500_HW_STRAP_RESERVED28 | \ 100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 101 SCU_HW_STRAP_VGA_CLASS_CODE | \ 102 SCU_HW_STRAP_LPC_RESET_PIN | \ 103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 105 SCU_HW_STRAP_VGA_BIOS_ROM | \ 106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 107 SCU_AST2500_HW_STRAP_RESERVED1) 108 109 #define G220A_BMC_HW_STRAP1 ( \ 110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 112 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 113 SCU_AST2500_HW_STRAP_RESERVED28 | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_HW_STRAP_2ND_BOOT_WDT | \ 116 SCU_HW_STRAP_VGA_CLASS_CODE | \ 117 SCU_HW_STRAP_LPC_RESET_PIN | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 119 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 120 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 121 SCU_AST2500_HW_STRAP_RESERVED1) 122 123 /* FP5280G2 hardware value: 0XF100D286 */ 124 #define FP5280G2_BMC_HW_STRAP1 ( \ 125 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 126 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 127 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 128 SCU_AST2500_HW_STRAP_RESERVED28 | \ 129 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 130 SCU_HW_STRAP_VGA_CLASS_CODE | \ 131 SCU_HW_STRAP_LPC_RESET_PIN | \ 132 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 133 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 134 SCU_HW_STRAP_MAC1_RGMII | \ 135 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 136 SCU_AST2500_HW_STRAP_RESERVED1) 137 138 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 139 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 140 141 /* Quanta-Q71l hardware value */ 142 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 143 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 144 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 145 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 146 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 147 SCU_HW_STRAP_VGA_CLASS_CODE | \ 148 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 149 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 150 SCU_HW_STRAP_SPI_WIDTH | \ 151 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 152 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 153 154 /* AST2600 evb hardware value */ 155 #define AST2600_EVB_HW_STRAP1 0x000000C0 156 #define AST2600_EVB_HW_STRAP2 0x00000003 157 158 /* Tacoma hardware value */ 159 #define TACOMA_BMC_HW_STRAP1 0x00000000 160 #define TACOMA_BMC_HW_STRAP2 0x00000040 161 162 /* Rainier hardware value: (QEMU prototype) */ 163 #define RAINIER_BMC_HW_STRAP1 0x00422016 164 #define RAINIER_BMC_HW_STRAP2 0x80000848 165 166 /* Fuji hardware value */ 167 #define FUJI_BMC_HW_STRAP1 0x00000000 168 #define FUJI_BMC_HW_STRAP2 0x00000000 169 170 /* Bletchley hardware value */ 171 /* TODO: Leave same as EVB for now. */ 172 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 173 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 174 175 /* 176 * The max ram region is for firmwares that scan the address space 177 * with load/store to guess how much RAM the SoC has. 178 */ 179 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 180 { 181 return 0; 182 } 183 184 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 185 unsigned size) 186 { 187 /* Discard writes */ 188 } 189 190 static const MemoryRegionOps max_ram_ops = { 191 .read = max_ram_read, 192 .write = max_ram_write, 193 .endianness = DEVICE_NATIVE_ENDIAN, 194 }; 195 196 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 197 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 198 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 199 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 200 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 201 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 202 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 203 204 static void aspeed_write_smpboot(ARMCPU *cpu, 205 const struct arm_boot_info *info) 206 { 207 static const uint32_t poll_mailbox_ready[] = { 208 /* 209 * r2 = per-cpu go sign value 210 * r1 = AST_SMP_MBOX_FIELD_ENTRY 211 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 212 */ 213 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 214 0xe21000ff, /* ands r0, r0, #255 */ 215 0xe59f201c, /* ldr r2, [pc, #28] */ 216 0xe1822000, /* orr r2, r2, r0 */ 217 218 0xe59f1018, /* ldr r1, [pc, #24] */ 219 0xe59f0018, /* ldr r0, [pc, #24] */ 220 221 0xe320f002, /* wfe */ 222 0xe5904000, /* ldr r4, [r0] */ 223 0xe1520004, /* cmp r2, r4 */ 224 0x1afffffb, /* bne <wfe> */ 225 0xe591f000, /* ldr pc, [r1] */ 226 AST_SMP_MBOX_GOSIGN, 227 AST_SMP_MBOX_FIELD_ENTRY, 228 AST_SMP_MBOX_FIELD_GOSIGN, 229 }; 230 231 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 232 sizeof(poll_mailbox_ready), 233 info->smp_loader_start); 234 } 235 236 static void aspeed_reset_secondary(ARMCPU *cpu, 237 const struct arm_boot_info *info) 238 { 239 AddressSpace *as = arm_boot_address_space(cpu, info); 240 CPUState *cs = CPU(cpu); 241 242 /* info->smp_bootreg_addr */ 243 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 244 MEMTXATTRS_UNSPECIFIED, NULL); 245 cpu_set_pc(cs, info->smp_loader_start); 246 } 247 248 #define FIRMWARE_ADDR 0x0 249 250 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 251 Error **errp) 252 { 253 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 254 g_autofree void *storage = NULL; 255 int64_t size; 256 257 /* The block backend size should have already been 'validated' by 258 * the creation of the m25p80 object. 259 */ 260 size = blk_getlength(blk); 261 if (size <= 0) { 262 error_setg(errp, "failed to get flash size"); 263 return; 264 } 265 266 if (rom_size > size) { 267 rom_size = size; 268 } 269 270 storage = g_malloc0(rom_size); 271 if (blk_pread(blk, 0, storage, rom_size) < 0) { 272 error_setg(errp, "failed to read the initial flash content"); 273 return; 274 } 275 276 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 277 } 278 279 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 280 unsigned int count, int unit0) 281 { 282 int i; 283 284 if (!flashtype) { 285 return; 286 } 287 288 for (i = 0; i < count; ++i) { 289 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 290 qemu_irq cs_line; 291 DeviceState *dev; 292 293 dev = qdev_new(flashtype); 294 if (dinfo) { 295 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 296 } 297 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 298 299 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 300 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 301 } 302 } 303 304 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 305 { 306 DeviceState *card; 307 308 if (!dinfo) { 309 return; 310 } 311 card = qdev_new(TYPE_SD_CARD); 312 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 313 &error_fatal); 314 qdev_realize_and_unref(card, 315 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 316 &error_fatal); 317 } 318 319 static void aspeed_machine_init(MachineState *machine) 320 { 321 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 322 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 323 AspeedSoCClass *sc; 324 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 325 ram_addr_t max_ram_size; 326 int i; 327 NICInfo *nd = &nd_table[0]; 328 329 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 330 4 * GiB); 331 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 332 333 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 334 335 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 336 337 /* 338 * This will error out if isize is not supported by memory controller. 339 */ 340 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size, 341 &error_fatal); 342 343 for (i = 0; i < sc->macs_num; i++) { 344 if ((amc->macs_mask & (1 << i)) && nd->used) { 345 qemu_check_nic_model(nd, TYPE_FTGMAC100); 346 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 347 nd++; 348 } 349 } 350 351 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 352 &error_abort); 353 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 354 &error_abort); 355 object_property_set_link(OBJECT(&bmc->soc), "dram", 356 OBJECT(machine->ram), &error_abort); 357 if (machine->kernel_filename) { 358 /* 359 * When booting with a -kernel command line there is no u-boot 360 * that runs to unlock the SCU. In this case set the default to 361 * be unlocked as the kernel expects 362 */ 363 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 364 ASPEED_SCU_PROT_KEY, &error_abort); 365 } 366 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", 367 amc->uart_default); 368 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 369 370 memory_region_add_subregion(get_system_memory(), 371 sc->memmap[ASPEED_DEV_SDRAM], 372 &bmc->ram_container); 373 374 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 375 &error_abort); 376 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 377 "max_ram", max_ram_size - machine->ram_size); 378 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); 379 380 aspeed_board_init_flashes(&bmc->soc.fmc, 381 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 382 amc->num_cs, 0); 383 aspeed_board_init_flashes(&bmc->soc.spi[0], 384 bmc->spi_model ? bmc->spi_model : amc->spi_model, 385 1, amc->num_cs); 386 387 /* Install first FMC flash content as a boot rom. */ 388 if (drive0) { 389 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 390 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 391 uint64_t size = memory_region_size(&fl->mmio); 392 393 /* 394 * create a ROM region using the default mapping window size of 395 * the flash module. The window size is 64MB for the AST2400 396 * SoC and 128MB for the AST2500 SoC, which is twice as big as 397 * needed by the flash modules of the Aspeed machines. 398 */ 399 if (ASPEED_MACHINE(machine)->mmio_exec) { 400 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", 401 &fl->mmio, 0, size); 402 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 403 boot_rom); 404 } else { 405 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", 406 size, &error_abort); 407 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 408 boot_rom); 409 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort); 410 } 411 } 412 413 if (machine->kernel_filename && sc->num_cpus > 1) { 414 /* With no u-boot we must set up a boot stub for the secondary CPU */ 415 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 416 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 417 0x80, &error_abort); 418 memory_region_add_subregion(get_system_memory(), 419 AST_SMP_MAILBOX_BASE, smpboot); 420 421 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 422 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 423 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 424 } 425 426 aspeed_board_binfo.ram_size = machine->ram_size; 427 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 428 429 if (amc->i2c_init) { 430 amc->i2c_init(bmc); 431 } 432 433 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 434 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], 435 drive_get(IF_SD, 0, i)); 436 } 437 438 if (bmc->soc.emmc.num_slots) { 439 sdhci_attach_drive(&bmc->soc.emmc.slots[0], 440 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); 441 } 442 443 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 444 } 445 446 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 447 { 448 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 449 DeviceState *dev = DEVICE(i2c_dev); 450 451 qdev_prop_set_uint32(dev, "rom-size", rsize); 452 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 453 } 454 455 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 456 { 457 AspeedSoCState *soc = &bmc->soc; 458 DeviceState *dev; 459 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 460 461 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 462 * enough to provide basic RTC features. Alarms will be missing */ 463 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 464 465 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 466 eeprom_buf); 467 468 /* add a TMP423 temperature sensor */ 469 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 470 "tmp423", 0x4c)); 471 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 472 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 473 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 474 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 475 } 476 477 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 478 { 479 AspeedSoCState *soc = &bmc->soc; 480 481 /* 482 * The quanta-q71l platform expects tmp75s which are compatible with 483 * tmp105s. 484 */ 485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 488 489 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 490 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 491 /* TODO: Add Memory Riser i2c mux and eeproms. */ 492 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 495 496 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 497 498 /* i2c-7 */ 499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 500 /* - i2c@0: pmbus@59 */ 501 /* - i2c@1: pmbus@58 */ 502 /* - i2c@2: pmbus@58 */ 503 /* - i2c@3: pmbus@59 */ 504 505 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 506 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 507 } 508 509 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 510 { 511 AspeedSoCState *soc = &bmc->soc; 512 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 513 514 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 515 eeprom_buf); 516 517 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 519 TYPE_TMP105, 0x4d); 520 521 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 522 * plugged on the I2C bus header */ 523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 524 } 525 526 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 527 { 528 /* Start with some devices on our I2C busses */ 529 ast2500_evb_i2c_init(bmc); 530 } 531 532 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 533 { 534 AspeedSoCState *soc = &bmc->soc; 535 536 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 537 * good enough */ 538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 539 } 540 541 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 542 { 543 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 544 TYPE_PCA9552, addr); 545 } 546 547 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 548 { 549 AspeedSoCState *soc = &bmc->soc; 550 551 /* bus 2 : */ 552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 554 /* bus 2 : pca9546 @ 0x73 */ 555 556 /* bus 3 : pca9548 @ 0x70 */ 557 558 /* bus 4 : */ 559 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 560 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 561 eeprom4_54); 562 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 563 create_pca9552(soc, 4, 0x76); 564 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 565 create_pca9552(soc, 4, 0x77); 566 567 /* bus 6 : */ 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 570 /* bus 6 : pca9546 @ 0x73 */ 571 572 /* bus 8 : */ 573 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 574 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 575 eeprom8_56); 576 create_pca9552(soc, 8, 0x60); 577 create_pca9552(soc, 8, 0x61); 578 /* bus 8 : adc128d818 @ 0x1d */ 579 /* bus 8 : adc128d818 @ 0x1f */ 580 581 /* 582 * bus 13 : pca9548 @ 0x71 583 * - channel 3: 584 * - tmm421 @ 0x4c 585 * - tmp421 @ 0x4e 586 * - tmp421 @ 0x4f 587 */ 588 589 } 590 591 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 592 { 593 static const struct { 594 unsigned gpio_id; 595 LEDColor color; 596 const char *description; 597 bool gpio_polarity; 598 } pca1_leds[] = { 599 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 600 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 601 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 602 }; 603 AspeedSoCState *soc = &bmc->soc; 604 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 605 DeviceState *dev; 606 LEDState *led; 607 608 /* Bus 3: TODO bmp280@77 */ 609 /* Bus 3: TODO max31785@52 */ 610 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 611 qdev_prop_set_string(dev, "description", "pca1"); 612 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 613 aspeed_i2c_get_bus(&soc->i2c, 3), 614 &error_fatal); 615 616 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 617 led = led_create_simple(OBJECT(bmc), 618 pca1_leds[i].gpio_polarity, 619 pca1_leds[i].color, 620 pca1_leds[i].description); 621 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 622 qdev_get_gpio_in(DEVICE(led), 0)); 623 } 624 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 625 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 627 628 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 629 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 630 0x4a); 631 632 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 633 * good enough */ 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 635 636 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 637 eeprom_buf); 638 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 639 qdev_prop_set_string(dev, "description", "pca0"); 640 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 641 aspeed_i2c_get_bus(&soc->i2c, 11), 642 &error_fatal); 643 /* Bus 11: TODO ucd90160@64 */ 644 } 645 646 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 647 { 648 AspeedSoCState *soc = &bmc->soc; 649 DeviceState *dev; 650 651 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 652 "emc1413", 0x4c)); 653 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 654 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 655 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 656 657 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 658 "emc1413", 0x4c)); 659 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 660 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 661 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 662 663 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 664 "emc1413", 0x4c)); 665 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 666 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 667 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 668 669 static uint8_t eeprom_buf[2 * 1024] = { 670 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 671 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 672 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 673 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 674 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 675 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 677 }; 678 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 679 eeprom_buf); 680 } 681 682 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize) 683 { 684 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr); 685 DeviceState *dev = DEVICE(i2c_dev); 686 687 qdev_prop_set_uint32(dev, "rom-size", rsize); 688 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); 689 } 690 691 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 692 { 693 AspeedSoCState *soc = &bmc->soc; 694 I2CSlave *i2c_mux; 695 696 /* The at24c256 */ 697 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 698 699 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 701 0x48); 702 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 703 0x49); 704 705 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 706 "pca9546", 0x70); 707 /* It expects a TMP112 but a TMP105 is compatible */ 708 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 709 0x4a); 710 711 /* It expects a ds3232 but a ds1338 is good enough */ 712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 713 714 /* It expects a pca9555 but a pca9552 is compatible */ 715 create_pca9552(soc, 8, 0x30); 716 } 717 718 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 719 { 720 AspeedSoCState *soc = &bmc->soc; 721 I2CSlave *i2c_mux; 722 723 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 724 725 create_pca9552(soc, 3, 0x61); 726 727 /* The rainier expects a TMP275 but a TMP105 is compatible */ 728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 729 0x48); 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 731 0x49); 732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 733 0x4a); 734 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 735 "pca9546", 0x70); 736 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 737 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 738 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 739 create_pca9552(soc, 4, 0x60); 740 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 742 0x48); 743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 744 0x49); 745 create_pca9552(soc, 5, 0x60); 746 create_pca9552(soc, 5, 0x61); 747 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 748 "pca9546", 0x70); 749 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 750 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 751 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 753 0x48); 754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 755 0x4a); 756 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 757 0x4b); 758 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 759 "pca9546", 0x70); 760 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 761 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 762 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 763 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 764 765 create_pca9552(soc, 7, 0x30); 766 create_pca9552(soc, 7, 0x31); 767 create_pca9552(soc, 7, 0x32); 768 create_pca9552(soc, 7, 0x33); 769 /* Bus 7: TODO max31785@52 */ 770 create_pca9552(soc, 7, 0x60); 771 create_pca9552(soc, 7, 0x61); 772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 773 /* Bus 7: TODO si7021-a20@20 */ 774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 775 0x48); 776 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 777 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 778 779 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 780 0x48); 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 782 0x4a); 783 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); 784 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); 785 create_pca9552(soc, 8, 0x60); 786 create_pca9552(soc, 8, 0x61); 787 /* Bus 8: ucd90320@11 */ 788 /* Bus 8: ucd90320@b */ 789 /* Bus 8: ucd90320@c */ 790 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 793 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 794 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 797 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 798 799 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 800 0x48); 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 802 0x49); 803 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 804 "pca9546", 0x70); 805 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 806 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 807 create_pca9552(soc, 11, 0x60); 808 809 810 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 811 create_pca9552(soc, 13, 0x60); 812 813 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 814 create_pca9552(soc, 14, 0x60); 815 816 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 817 create_pca9552(soc, 15, 0x60); 818 } 819 820 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 821 I2CBus **channels) 822 { 823 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 824 for (int i = 0; i < 8; i++) { 825 channels[i] = pca954x_i2c_get_bus(mux, i); 826 } 827 } 828 829 #define TYPE_LM75 TYPE_TMP105 830 #define TYPE_TMP75 TYPE_TMP105 831 #define TYPE_TMP422 "tmp422" 832 833 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 834 { 835 AspeedSoCState *soc = &bmc->soc; 836 I2CBus *i2c[144] = {}; 837 838 for (int i = 0; i < 16; i++) { 839 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 840 } 841 I2CBus *i2c180 = i2c[2]; 842 I2CBus *i2c480 = i2c[8]; 843 I2CBus *i2c600 = i2c[11]; 844 845 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 846 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 847 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 848 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 849 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 850 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 851 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 852 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 853 for (int i = 0; i < 8; i++) { 854 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 855 } 856 857 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 858 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 859 860 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB); 861 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB); 862 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB); 863 864 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 865 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 866 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 867 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 868 869 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB); 870 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 871 872 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 873 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB); 874 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 875 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 876 877 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 878 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 879 880 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB); 881 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 882 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 883 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB); 884 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB); 885 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB); 886 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB); 887 888 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB); 889 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 890 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 891 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB); 892 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB); 893 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB); 894 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB); 895 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB); 896 897 for (int i = 0; i < 8; i++) { 898 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 899 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 900 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 901 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 902 } 903 } 904 905 #define TYPE_TMP421 "tmp421" 906 907 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 908 { 909 AspeedSoCState *soc = &bmc->soc; 910 I2CBus *i2c[13] = {}; 911 for (int i = 0; i < 13; i++) { 912 if ((i == 8) || (i == 11)) { 913 continue; 914 } 915 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 916 } 917 918 /* Bus 0 - 5 all have the same config. */ 919 for (int i = 0; i < 6; i++) { 920 /* Missing model: ti,ina230 @ 0x45 */ 921 /* Missing model: mps,mp5023 @ 0x40 */ 922 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 923 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 924 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 925 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 926 /* Missing model: fsc,fusb302 @ 0x22 */ 927 } 928 929 /* Bus 6 */ 930 at24c_eeprom_init(i2c[6], 0x56, 65536); 931 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 932 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 933 934 935 /* Bus 7 */ 936 at24c_eeprom_init(i2c[7], 0x54, 65536); 937 938 /* Bus 9 */ 939 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 940 941 /* Bus 10 */ 942 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 943 /* Missing model: ti,hdc1080 @ 0x40 */ 944 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 945 946 /* Bus 12 */ 947 /* Missing model: adi,adm1278 @ 0x11 */ 948 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 949 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 950 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 951 } 952 953 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 954 { 955 return ASPEED_MACHINE(obj)->mmio_exec; 956 } 957 958 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 959 { 960 ASPEED_MACHINE(obj)->mmio_exec = value; 961 } 962 963 static void aspeed_machine_instance_init(Object *obj) 964 { 965 ASPEED_MACHINE(obj)->mmio_exec = false; 966 } 967 968 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 969 { 970 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 971 return g_strdup(bmc->fmc_model); 972 } 973 974 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 975 { 976 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 977 978 g_free(bmc->fmc_model); 979 bmc->fmc_model = g_strdup(value); 980 } 981 982 static char *aspeed_get_spi_model(Object *obj, Error **errp) 983 { 984 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 985 return g_strdup(bmc->spi_model); 986 } 987 988 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 989 { 990 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 991 992 g_free(bmc->spi_model); 993 bmc->spi_model = g_strdup(value); 994 } 995 996 static void aspeed_machine_class_props_init(ObjectClass *oc) 997 { 998 object_class_property_add_bool(oc, "execute-in-place", 999 aspeed_get_mmio_exec, 1000 aspeed_set_mmio_exec); 1001 object_class_property_set_description(oc, "execute-in-place", 1002 "boot directly from CE0 flash device"); 1003 1004 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1005 aspeed_set_fmc_model); 1006 object_class_property_set_description(oc, "fmc-model", 1007 "Change the FMC Flash model"); 1008 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1009 aspeed_set_spi_model); 1010 object_class_property_set_description(oc, "spi-model", 1011 "Change the SPI Flash model"); 1012 } 1013 1014 static int aspeed_soc_num_cpus(const char *soc_name) 1015 { 1016 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 1017 return sc->num_cpus; 1018 } 1019 1020 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1021 { 1022 MachineClass *mc = MACHINE_CLASS(oc); 1023 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1024 1025 mc->init = aspeed_machine_init; 1026 mc->no_floppy = 1; 1027 mc->no_cdrom = 1; 1028 mc->no_parallel = 1; 1029 mc->default_ram_id = "ram"; 1030 amc->macs_mask = ASPEED_MAC0_ON; 1031 amc->uart_default = ASPEED_DEV_UART5; 1032 1033 aspeed_machine_class_props_init(oc); 1034 } 1035 1036 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1037 { 1038 MachineClass *mc = MACHINE_CLASS(oc); 1039 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1040 1041 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1042 amc->soc_name = "ast2400-a1"; 1043 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1044 amc->fmc_model = "n25q256a"; 1045 amc->spi_model = "mx25l25635e"; 1046 amc->num_cs = 1; 1047 amc->i2c_init = palmetto_bmc_i2c_init; 1048 mc->default_ram_size = 256 * MiB; 1049 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1050 aspeed_soc_num_cpus(amc->soc_name); 1051 }; 1052 1053 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1054 { 1055 MachineClass *mc = MACHINE_CLASS(oc); 1056 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1057 1058 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1059 amc->soc_name = "ast2400-a1"; 1060 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1061 amc->fmc_model = "n25q256a"; 1062 amc->spi_model = "mx25l25635e"; 1063 amc->num_cs = 1; 1064 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1065 mc->default_ram_size = 128 * MiB; 1066 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1067 aspeed_soc_num_cpus(amc->soc_name); 1068 } 1069 1070 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1071 void *data) 1072 { 1073 MachineClass *mc = MACHINE_CLASS(oc); 1074 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1075 1076 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1077 amc->soc_name = "ast2400-a1"; 1078 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1079 amc->fmc_model = "mx25l25635e"; 1080 amc->spi_model = "mx25l25635e"; 1081 amc->num_cs = 1; 1082 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1083 amc->i2c_init = palmetto_bmc_i2c_init; 1084 mc->default_ram_size = 256 * MiB; 1085 } 1086 1087 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1088 { 1089 MachineClass *mc = MACHINE_CLASS(oc); 1090 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1091 1092 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1093 amc->soc_name = "ast2500-a1"; 1094 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1095 amc->fmc_model = "w25q256"; 1096 amc->spi_model = "mx25l25635e"; 1097 amc->num_cs = 1; 1098 amc->i2c_init = ast2500_evb_i2c_init; 1099 mc->default_ram_size = 512 * MiB; 1100 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1101 aspeed_soc_num_cpus(amc->soc_name); 1102 }; 1103 1104 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1105 { 1106 MachineClass *mc = MACHINE_CLASS(oc); 1107 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1108 1109 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1110 amc->soc_name = "ast2500-a1"; 1111 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1112 amc->fmc_model = "n25q256a"; 1113 amc->spi_model = "mx66l1g45g"; 1114 amc->num_cs = 2; 1115 amc->i2c_init = romulus_bmc_i2c_init; 1116 mc->default_ram_size = 512 * MiB; 1117 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1118 aspeed_soc_num_cpus(amc->soc_name); 1119 }; 1120 1121 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1122 { 1123 MachineClass *mc = MACHINE_CLASS(oc); 1124 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1125 1126 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1127 amc->soc_name = "ast2500-a1"; 1128 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1129 amc->fmc_model = "mx66l1g45g"; 1130 amc->spi_model = "mx66l1g45g"; 1131 amc->num_cs = 2; 1132 amc->i2c_init = sonorapass_bmc_i2c_init; 1133 mc->default_ram_size = 512 * MiB; 1134 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1135 aspeed_soc_num_cpus(amc->soc_name); 1136 }; 1137 1138 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1139 { 1140 MachineClass *mc = MACHINE_CLASS(oc); 1141 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1142 1143 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1144 amc->soc_name = "ast2500-a1"; 1145 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1146 amc->fmc_model = "mx25l25635e"; 1147 amc->spi_model = "mx66l1g45g"; 1148 amc->num_cs = 2; 1149 amc->i2c_init = witherspoon_bmc_i2c_init; 1150 mc->default_ram_size = 512 * MiB; 1151 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1152 aspeed_soc_num_cpus(amc->soc_name); 1153 }; 1154 1155 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1156 { 1157 MachineClass *mc = MACHINE_CLASS(oc); 1158 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1159 1160 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1161 amc->soc_name = "ast2600-a3"; 1162 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1163 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1164 amc->fmc_model = "w25q512jv"; 1165 amc->spi_model = "mx66u51235f"; 1166 amc->num_cs = 1; 1167 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1168 ASPEED_MAC3_ON; 1169 amc->i2c_init = ast2600_evb_i2c_init; 1170 mc->default_ram_size = 1 * GiB; 1171 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1172 aspeed_soc_num_cpus(amc->soc_name); 1173 }; 1174 1175 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1176 { 1177 MachineClass *mc = MACHINE_CLASS(oc); 1178 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1179 1180 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1181 amc->soc_name = "ast2600-a3"; 1182 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1183 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1184 amc->fmc_model = "mx66l1g45g"; 1185 amc->spi_model = "mx66l1g45g"; 1186 amc->num_cs = 2; 1187 amc->macs_mask = ASPEED_MAC2_ON; 1188 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1189 mc->default_ram_size = 1 * GiB; 1190 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1191 aspeed_soc_num_cpus(amc->soc_name); 1192 }; 1193 1194 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1195 { 1196 MachineClass *mc = MACHINE_CLASS(oc); 1197 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1198 1199 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1200 amc->soc_name = "ast2500-a1"; 1201 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1202 amc->fmc_model = "n25q512a"; 1203 amc->spi_model = "mx25l25635e"; 1204 amc->num_cs = 2; 1205 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1206 amc->i2c_init = g220a_bmc_i2c_init; 1207 mc->default_ram_size = 1024 * MiB; 1208 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1209 aspeed_soc_num_cpus(amc->soc_name); 1210 }; 1211 1212 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1213 { 1214 MachineClass *mc = MACHINE_CLASS(oc); 1215 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1216 1217 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1218 amc->soc_name = "ast2500-a1"; 1219 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1220 amc->fmc_model = "n25q512a"; 1221 amc->spi_model = "mx25l25635e"; 1222 amc->num_cs = 2; 1223 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1224 amc->i2c_init = fp5280g2_bmc_i2c_init; 1225 mc->default_ram_size = 512 * MiB; 1226 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1227 aspeed_soc_num_cpus(amc->soc_name); 1228 }; 1229 1230 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1231 { 1232 MachineClass *mc = MACHINE_CLASS(oc); 1233 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1234 1235 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1236 amc->soc_name = "ast2600-a3"; 1237 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1238 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1239 amc->fmc_model = "mx66l1g45g"; 1240 amc->spi_model = "mx66l1g45g"; 1241 amc->num_cs = 2; 1242 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1243 amc->i2c_init = rainier_bmc_i2c_init; 1244 mc->default_ram_size = 1 * GiB; 1245 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1246 aspeed_soc_num_cpus(amc->soc_name); 1247 }; 1248 1249 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 1250 #if HOST_LONG_BITS == 32 1251 #define FUJI_BMC_RAM_SIZE (1 * GiB) 1252 #else 1253 #define FUJI_BMC_RAM_SIZE (2 * GiB) 1254 #endif 1255 1256 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1257 { 1258 MachineClass *mc = MACHINE_CLASS(oc); 1259 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1260 1261 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1262 amc->soc_name = "ast2600-a3"; 1263 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1264 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1265 amc->fmc_model = "mx66l1g45g"; 1266 amc->spi_model = "mx66l1g45g"; 1267 amc->num_cs = 2; 1268 amc->macs_mask = ASPEED_MAC3_ON; 1269 amc->i2c_init = fuji_bmc_i2c_init; 1270 amc->uart_default = ASPEED_DEV_UART1; 1271 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1272 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1273 aspeed_soc_num_cpus(amc->soc_name); 1274 }; 1275 1276 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(oc); 1279 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1280 1281 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1282 amc->soc_name = "ast2600-a3"; 1283 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1284 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1285 amc->fmc_model = "w25q01jvq"; 1286 amc->spi_model = NULL; 1287 amc->num_cs = 2; 1288 amc->macs_mask = ASPEED_MAC2_ON; 1289 amc->i2c_init = bletchley_bmc_i2c_init; 1290 mc->default_ram_size = 512 * MiB; 1291 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1292 aspeed_soc_num_cpus(amc->soc_name); 1293 } 1294 1295 static const TypeInfo aspeed_machine_types[] = { 1296 { 1297 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1298 .parent = TYPE_ASPEED_MACHINE, 1299 .class_init = aspeed_machine_palmetto_class_init, 1300 }, { 1301 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1302 .parent = TYPE_ASPEED_MACHINE, 1303 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1304 }, { 1305 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1306 .parent = TYPE_ASPEED_MACHINE, 1307 .class_init = aspeed_machine_ast2500_evb_class_init, 1308 }, { 1309 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1310 .parent = TYPE_ASPEED_MACHINE, 1311 .class_init = aspeed_machine_romulus_class_init, 1312 }, { 1313 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1314 .parent = TYPE_ASPEED_MACHINE, 1315 .class_init = aspeed_machine_sonorapass_class_init, 1316 }, { 1317 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1318 .parent = TYPE_ASPEED_MACHINE, 1319 .class_init = aspeed_machine_witherspoon_class_init, 1320 }, { 1321 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1322 .parent = TYPE_ASPEED_MACHINE, 1323 .class_init = aspeed_machine_ast2600_evb_class_init, 1324 }, { 1325 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1326 .parent = TYPE_ASPEED_MACHINE, 1327 .class_init = aspeed_machine_tacoma_class_init, 1328 }, { 1329 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1330 .parent = TYPE_ASPEED_MACHINE, 1331 .class_init = aspeed_machine_g220a_class_init, 1332 }, { 1333 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1334 .parent = TYPE_ASPEED_MACHINE, 1335 .class_init = aspeed_machine_fp5280g2_class_init, 1336 }, { 1337 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1338 .parent = TYPE_ASPEED_MACHINE, 1339 .class_init = aspeed_machine_quanta_q71l_class_init, 1340 }, { 1341 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1342 .parent = TYPE_ASPEED_MACHINE, 1343 .class_init = aspeed_machine_rainier_class_init, 1344 }, { 1345 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1346 .parent = TYPE_ASPEED_MACHINE, 1347 .class_init = aspeed_machine_fuji_class_init, 1348 }, { 1349 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1350 .parent = TYPE_ASPEED_MACHINE, 1351 .class_init = aspeed_machine_bletchley_class_init, 1352 }, { 1353 .name = TYPE_ASPEED_MACHINE, 1354 .parent = TYPE_MACHINE, 1355 .instance_size = sizeof(AspeedMachineState), 1356 .instance_init = aspeed_machine_instance_init, 1357 .class_size = sizeof(AspeedMachineClass), 1358 .class_init = aspeed_machine_class_init, 1359 .abstract = true, 1360 } 1361 }; 1362 1363 DEFINE_TYPES(aspeed_machine_types) 1364