1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 }; 40 41 /* Palmetto hardware value: 0x120CE416 */ 42 #define PALMETTO_BMC_HW_STRAP1 ( \ 43 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 44 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 45 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 46 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 47 SCU_HW_STRAP_VGA_CLASS_CODE | \ 48 SCU_HW_STRAP_LPC_RESET_PIN | \ 49 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 50 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 51 SCU_HW_STRAP_SPI_WIDTH | \ 52 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 53 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 54 55 /* AST2500 evb hardware value: 0xF100C2E6 */ 56 #define AST2500_EVB_HW_STRAP1 (( \ 57 AST2500_HW_STRAP1_DEFAULTS | \ 58 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 59 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 60 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 61 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 62 SCU_HW_STRAP_MAC1_RGMII | \ 63 SCU_HW_STRAP_MAC0_RGMII) & \ 64 ~SCU_HW_STRAP_2ND_BOOT_WDT) 65 66 /* Romulus hardware value: 0xF10AD206 */ 67 #define ROMULUS_BMC_HW_STRAP1 ( \ 68 AST2500_HW_STRAP1_DEFAULTS | \ 69 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 70 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 71 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 72 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 73 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 74 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 75 76 /* Sonorapass hardware value: 0xF100D216 */ 77 #define SONORAPASS_BMC_HW_STRAP1 ( \ 78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 80 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 81 SCU_AST2500_HW_STRAP_RESERVED28 | \ 82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 83 SCU_HW_STRAP_VGA_CLASS_CODE | \ 84 SCU_HW_STRAP_LPC_RESET_PIN | \ 85 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 86 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 87 SCU_HW_STRAP_VGA_BIOS_ROM | \ 88 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 89 SCU_AST2500_HW_STRAP_RESERVED1) 90 91 /* Swift hardware value: 0xF11AD206 */ 92 #define SWIFT_BMC_HW_STRAP1 ( \ 93 AST2500_HW_STRAP1_DEFAULTS | \ 94 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 95 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 96 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 97 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 98 SCU_H_PLL_BYPASS_EN | \ 99 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 100 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 101 102 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 103 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 104 105 /* AST2600 evb hardware value */ 106 #define AST2600_EVB_HW_STRAP1 0x000000C0 107 #define AST2600_EVB_HW_STRAP2 0x00000003 108 109 /* Tacoma hardware value */ 110 #define TACOMA_BMC_HW_STRAP1 0x00000000 111 #define TACOMA_BMC_HW_STRAP2 0x00000040 112 113 /* 114 * The max ram region is for firmwares that scan the address space 115 * with load/store to guess how much RAM the SoC has. 116 */ 117 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 118 { 119 return 0; 120 } 121 122 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 123 unsigned size) 124 { 125 /* Discard writes */ 126 } 127 128 static const MemoryRegionOps max_ram_ops = { 129 .read = max_ram_read, 130 .write = max_ram_write, 131 .endianness = DEVICE_NATIVE_ENDIAN, 132 }; 133 134 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 135 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 136 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 137 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 138 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 139 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 140 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 141 142 static void aspeed_write_smpboot(ARMCPU *cpu, 143 const struct arm_boot_info *info) 144 { 145 static const uint32_t poll_mailbox_ready[] = { 146 /* 147 * r2 = per-cpu go sign value 148 * r1 = AST_SMP_MBOX_FIELD_ENTRY 149 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 150 */ 151 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 152 0xe21000ff, /* ands r0, r0, #255 */ 153 0xe59f201c, /* ldr r2, [pc, #28] */ 154 0xe1822000, /* orr r2, r2, r0 */ 155 156 0xe59f1018, /* ldr r1, [pc, #24] */ 157 0xe59f0018, /* ldr r0, [pc, #24] */ 158 159 0xe320f002, /* wfe */ 160 0xe5904000, /* ldr r4, [r0] */ 161 0xe1520004, /* cmp r2, r4 */ 162 0x1afffffb, /* bne <wfe> */ 163 0xe591f000, /* ldr pc, [r1] */ 164 AST_SMP_MBOX_GOSIGN, 165 AST_SMP_MBOX_FIELD_ENTRY, 166 AST_SMP_MBOX_FIELD_GOSIGN, 167 }; 168 169 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 170 sizeof(poll_mailbox_ready), 171 info->smp_loader_start); 172 } 173 174 static void aspeed_reset_secondary(ARMCPU *cpu, 175 const struct arm_boot_info *info) 176 { 177 AddressSpace *as = arm_boot_address_space(cpu, info); 178 CPUState *cs = CPU(cpu); 179 180 /* info->smp_bootreg_addr */ 181 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 182 MEMTXATTRS_UNSPECIFIED, NULL); 183 cpu_set_pc(cs, info->smp_loader_start); 184 } 185 186 #define FIRMWARE_ADDR 0x0 187 188 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 189 Error **errp) 190 { 191 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 192 uint8_t *storage; 193 int64_t size; 194 195 /* The block backend size should have already been 'validated' by 196 * the creation of the m25p80 object. 197 */ 198 size = blk_getlength(blk); 199 if (size <= 0) { 200 error_setg(errp, "failed to get flash size"); 201 return; 202 } 203 204 if (rom_size > size) { 205 rom_size = size; 206 } 207 208 storage = g_new0(uint8_t, rom_size); 209 if (blk_pread(blk, 0, storage, rom_size) < 0) { 210 error_setg(errp, "failed to read the initial flash content"); 211 return; 212 } 213 214 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 215 g_free(storage); 216 } 217 218 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 219 Error **errp) 220 { 221 int i ; 222 223 for (i = 0; i < s->num_cs; ++i) { 224 AspeedSMCFlash *fl = &s->flashes[i]; 225 DriveInfo *dinfo = drive_get_next(IF_MTD); 226 qemu_irq cs_line; 227 228 fl->flash = qdev_new(flashtype); 229 if (dinfo) { 230 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 231 errp); 232 } 233 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); 234 235 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 236 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 237 } 238 } 239 240 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 241 { 242 DeviceState *card; 243 244 card = qdev_new(TYPE_SD_CARD); 245 if (dinfo) { 246 qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), 247 &error_fatal); 248 } 249 qdev_realize_and_unref(card, 250 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 251 &error_fatal); 252 } 253 254 static void aspeed_machine_init(MachineState *machine) 255 { 256 AspeedBoardState *bmc; 257 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 258 AspeedSoCClass *sc; 259 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 260 ram_addr_t max_ram_size; 261 int i; 262 NICInfo *nd = &nd_table[0]; 263 264 bmc = g_new0(AspeedBoardState, 1); 265 266 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 267 4 * GiB); 268 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 269 270 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); 271 272 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 273 274 /* 275 * This will error out if isize is not supported by memory controller. 276 */ 277 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 278 &error_fatal); 279 280 for (i = 0; i < sc->macs_num; i++) { 281 if ((amc->macs_mask & (1 << i)) && nd->used) { 282 qemu_check_nic_model(nd, TYPE_FTGMAC100); 283 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); 284 nd++; 285 } 286 } 287 288 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 289 &error_abort); 290 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", 291 &error_abort); 292 object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", 293 &error_abort); 294 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 295 "dram", &error_abort); 296 if (machine->kernel_filename) { 297 /* 298 * When booting with a -kernel command line there is no u-boot 299 * that runs to unlock the SCU. In this case set the default to 300 * be unlocked as the kernel expects 301 */ 302 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 303 "hw-prot-key", &error_abort); 304 } 305 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 306 307 memory_region_add_subregion(get_system_memory(), 308 sc->memmap[ASPEED_SDRAM], 309 &bmc->ram_container); 310 311 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 312 &error_abort); 313 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 314 "max_ram", max_ram_size - ram_size); 315 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 316 317 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model, &error_abort); 318 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model, &error_abort); 319 320 /* Install first FMC flash content as a boot rom. */ 321 if (drive0) { 322 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 323 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 324 325 /* 326 * create a ROM region using the default mapping window size of 327 * the flash module. The window size is 64MB for the AST2400 328 * SoC and 128MB for the AST2500 SoC, which is twice as big as 329 * needed by the flash modules of the Aspeed machines. 330 */ 331 if (ASPEED_MACHINE(machine)->mmio_exec) { 332 memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 333 &fl->mmio, 0, fl->size); 334 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 335 boot_rom); 336 } else { 337 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 338 fl->size, &error_abort); 339 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 340 boot_rom); 341 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 342 } 343 } 344 345 if (machine->kernel_filename && sc->num_cpus > 1) { 346 /* With no u-boot we must set up a boot stub for the secondary CPU */ 347 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 348 memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", 349 0x80, &error_abort); 350 memory_region_add_subregion(get_system_memory(), 351 AST_SMP_MAILBOX_BASE, smpboot); 352 353 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 354 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 355 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 356 } 357 358 aspeed_board_binfo.ram_size = ram_size; 359 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 360 aspeed_board_binfo.nb_cpus = sc->num_cpus; 361 362 if (amc->i2c_init) { 363 amc->i2c_init(bmc); 364 } 365 366 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 367 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 368 } 369 370 if (bmc->soc.emmc.num_slots) { 371 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 372 } 373 374 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 375 } 376 377 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 378 { 379 AspeedSoCState *soc = &bmc->soc; 380 DeviceState *dev; 381 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 382 383 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 384 * enough to provide basic RTC features. Alarms will be missing */ 385 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 386 387 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 388 eeprom_buf); 389 390 /* add a TMP423 temperature sensor */ 391 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 392 "tmp423", 0x4c); 393 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 394 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 395 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 396 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 397 } 398 399 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 400 { 401 AspeedSoCState *soc = &bmc->soc; 402 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 403 404 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 405 eeprom_buf); 406 407 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 408 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 409 TYPE_TMP105, 0x4d); 410 411 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 412 * plugged on the I2C bus header */ 413 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 414 } 415 416 static void ast2600_evb_i2c_init(AspeedBoardState *bmc) 417 { 418 /* Start with some devices on our I2C busses */ 419 ast2500_evb_i2c_init(bmc); 420 } 421 422 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 423 { 424 AspeedSoCState *soc = &bmc->soc; 425 426 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 427 * good enough */ 428 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 429 } 430 431 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 432 { 433 AspeedSoCState *soc = &bmc->soc; 434 435 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 436 437 /* The swift board expects a TMP275 but a TMP105 is compatible */ 438 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 439 /* The swift board expects a pca9551 but a pca9552 is compatible */ 440 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 441 442 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 443 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 444 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 445 446 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 447 /* The swift board expects a pca9539 but a pca9552 is compatible */ 448 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 449 450 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 451 /* The swift board expects a pca9539 but a pca9552 is compatible */ 452 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 453 0x74); 454 455 /* The swift board expects a TMP275 but a TMP105 is compatible */ 456 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 457 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 458 } 459 460 static void sonorapass_bmc_i2c_init(AspeedBoardState *bmc) 461 { 462 AspeedSoCState *soc = &bmc->soc; 463 464 /* bus 2 : */ 465 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x48); 466 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), "tmp105", 0x49); 467 /* bus 2 : pca9546 @ 0x73 */ 468 469 /* bus 3 : pca9548 @ 0x70 */ 470 471 /* bus 4 : */ 472 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 473 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), 0x54, 474 eeprom4_54); 475 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 476 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x76); 477 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 478 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "pca9552", 0x77); 479 480 /* bus 6 : */ 481 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x48); 482 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 6), "tmp105", 0x49); 483 /* bus 6 : pca9546 @ 0x73 */ 484 485 /* bus 8 : */ 486 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 487 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), 0x56, 488 eeprom8_56); 489 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 490 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x61); 491 /* bus 8 : adc128d818 @ 0x1d */ 492 /* bus 8 : adc128d818 @ 0x1f */ 493 494 /* 495 * bus 13 : pca9548 @ 0x71 496 * - channel 3: 497 * - tmm421 @ 0x4c 498 * - tmp421 @ 0x4e 499 * - tmp421 @ 0x4f 500 */ 501 502 } 503 504 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 505 { 506 AspeedSoCState *soc = &bmc->soc; 507 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 508 509 /* Bus 3: TODO bmp280@77 */ 510 /* Bus 3: TODO max31785@52 */ 511 /* Bus 3: TODO dps310@76 */ 512 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 513 0x60); 514 515 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 516 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 517 518 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 519 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 520 0x4a); 521 522 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 523 * good enough */ 524 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 525 526 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 527 eeprom_buf); 528 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 529 0x60); 530 /* Bus 11: TODO ucd90160@64 */ 531 } 532 533 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 534 { 535 return ASPEED_MACHINE(obj)->mmio_exec; 536 } 537 538 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 539 { 540 ASPEED_MACHINE(obj)->mmio_exec = value; 541 } 542 543 static void aspeed_machine_instance_init(Object *obj) 544 { 545 ASPEED_MACHINE(obj)->mmio_exec = false; 546 } 547 548 static void aspeed_machine_class_props_init(ObjectClass *oc) 549 { 550 object_class_property_add_bool(oc, "execute-in-place", 551 aspeed_get_mmio_exec, 552 aspeed_set_mmio_exec); 553 object_class_property_set_description(oc, "execute-in-place", 554 "boot directly from CE0 flash device"); 555 } 556 557 static int aspeed_soc_num_cpus(const char *soc_name) 558 { 559 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); 560 return sc->num_cpus; 561 } 562 563 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 564 { 565 MachineClass *mc = MACHINE_CLASS(oc); 566 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 567 568 mc->init = aspeed_machine_init; 569 mc->no_floppy = 1; 570 mc->no_cdrom = 1; 571 mc->no_parallel = 1; 572 mc->default_ram_id = "ram"; 573 amc->macs_mask = ASPEED_MAC0_ON; 574 575 aspeed_machine_class_props_init(oc); 576 } 577 578 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 579 { 580 MachineClass *mc = MACHINE_CLASS(oc); 581 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 582 583 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 584 amc->soc_name = "ast2400-a1"; 585 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 586 amc->fmc_model = "n25q256a"; 587 amc->spi_model = "mx25l25635e"; 588 amc->num_cs = 1; 589 amc->i2c_init = palmetto_bmc_i2c_init; 590 mc->default_ram_size = 256 * MiB; 591 mc->default_cpus = mc->min_cpus = mc->max_cpus = 592 aspeed_soc_num_cpus(amc->soc_name); 593 }; 594 595 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 596 { 597 MachineClass *mc = MACHINE_CLASS(oc); 598 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 599 600 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 601 amc->soc_name = "ast2500-a1"; 602 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 603 amc->fmc_model = "w25q256"; 604 amc->spi_model = "mx25l25635e"; 605 amc->num_cs = 1; 606 amc->i2c_init = ast2500_evb_i2c_init; 607 mc->default_ram_size = 512 * MiB; 608 mc->default_cpus = mc->min_cpus = mc->max_cpus = 609 aspeed_soc_num_cpus(amc->soc_name); 610 }; 611 612 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 613 { 614 MachineClass *mc = MACHINE_CLASS(oc); 615 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 616 617 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 618 amc->soc_name = "ast2500-a1"; 619 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 620 amc->fmc_model = "n25q256a"; 621 amc->spi_model = "mx66l1g45g"; 622 amc->num_cs = 2; 623 amc->i2c_init = romulus_bmc_i2c_init; 624 mc->default_ram_size = 512 * MiB; 625 mc->default_cpus = mc->min_cpus = mc->max_cpus = 626 aspeed_soc_num_cpus(amc->soc_name); 627 }; 628 629 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 630 { 631 MachineClass *mc = MACHINE_CLASS(oc); 632 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 633 634 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 635 amc->soc_name = "ast2500-a1"; 636 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 637 amc->fmc_model = "mx66l1g45g"; 638 amc->spi_model = "mx66l1g45g"; 639 amc->num_cs = 2; 640 amc->i2c_init = sonorapass_bmc_i2c_init; 641 mc->default_ram_size = 512 * MiB; 642 mc->default_cpus = mc->min_cpus = mc->max_cpus = 643 aspeed_soc_num_cpus(amc->soc_name); 644 }; 645 646 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 647 { 648 MachineClass *mc = MACHINE_CLASS(oc); 649 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 650 651 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 652 amc->soc_name = "ast2500-a1"; 653 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 654 amc->fmc_model = "mx66l1g45g"; 655 amc->spi_model = "mx66l1g45g"; 656 amc->num_cs = 2; 657 amc->i2c_init = swift_bmc_i2c_init; 658 mc->default_ram_size = 512 * MiB; 659 mc->default_cpus = mc->min_cpus = mc->max_cpus = 660 aspeed_soc_num_cpus(amc->soc_name); 661 }; 662 663 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 664 { 665 MachineClass *mc = MACHINE_CLASS(oc); 666 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 667 668 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 669 amc->soc_name = "ast2500-a1"; 670 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 671 amc->fmc_model = "mx25l25635e"; 672 amc->spi_model = "mx66l1g45g"; 673 amc->num_cs = 2; 674 amc->i2c_init = witherspoon_bmc_i2c_init; 675 mc->default_ram_size = 512 * MiB; 676 mc->default_cpus = mc->min_cpus = mc->max_cpus = 677 aspeed_soc_num_cpus(amc->soc_name); 678 }; 679 680 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 681 { 682 MachineClass *mc = MACHINE_CLASS(oc); 683 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 684 685 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 686 amc->soc_name = "ast2600-a1"; 687 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 688 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 689 amc->fmc_model = "w25q512jv"; 690 amc->spi_model = "mx66u51235f"; 691 amc->num_cs = 1; 692 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; 693 amc->i2c_init = ast2600_evb_i2c_init; 694 mc->default_ram_size = 1 * GiB; 695 mc->default_cpus = mc->min_cpus = mc->max_cpus = 696 aspeed_soc_num_cpus(amc->soc_name); 697 }; 698 699 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 700 { 701 MachineClass *mc = MACHINE_CLASS(oc); 702 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 703 704 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 705 amc->soc_name = "ast2600-a1"; 706 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 707 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 708 amc->fmc_model = "mx66l1g45g"; 709 amc->spi_model = "mx66l1g45g"; 710 amc->num_cs = 2; 711 amc->macs_mask = ASPEED_MAC2_ON; 712 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 713 mc->default_ram_size = 1 * GiB; 714 mc->default_cpus = mc->min_cpus = mc->max_cpus = 715 aspeed_soc_num_cpus(amc->soc_name); 716 }; 717 718 static const TypeInfo aspeed_machine_types[] = { 719 { 720 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 721 .parent = TYPE_ASPEED_MACHINE, 722 .class_init = aspeed_machine_palmetto_class_init, 723 }, { 724 .name = MACHINE_TYPE_NAME("ast2500-evb"), 725 .parent = TYPE_ASPEED_MACHINE, 726 .class_init = aspeed_machine_ast2500_evb_class_init, 727 }, { 728 .name = MACHINE_TYPE_NAME("romulus-bmc"), 729 .parent = TYPE_ASPEED_MACHINE, 730 .class_init = aspeed_machine_romulus_class_init, 731 }, { 732 .name = MACHINE_TYPE_NAME("swift-bmc"), 733 .parent = TYPE_ASPEED_MACHINE, 734 .class_init = aspeed_machine_swift_class_init, 735 }, { 736 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 737 .parent = TYPE_ASPEED_MACHINE, 738 .class_init = aspeed_machine_sonorapass_class_init, 739 }, { 740 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 741 .parent = TYPE_ASPEED_MACHINE, 742 .class_init = aspeed_machine_witherspoon_class_init, 743 }, { 744 .name = MACHINE_TYPE_NAME("ast2600-evb"), 745 .parent = TYPE_ASPEED_MACHINE, 746 .class_init = aspeed_machine_ast2600_evb_class_init, 747 }, { 748 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 749 .parent = TYPE_ASPEED_MACHINE, 750 .class_init = aspeed_machine_tacoma_class_init, 751 }, { 752 .name = TYPE_ASPEED_MACHINE, 753 .parent = TYPE_MACHINE, 754 .instance_size = sizeof(AspeedMachine), 755 .instance_init = aspeed_machine_instance_init, 756 .class_size = sizeof(AspeedMachineClass), 757 .class_init = aspeed_machine_class_init, 758 .abstract = true, 759 } 760 }; 761 762 DEFINE_TYPES(aspeed_machine_types) 763