1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/gpio/pca9554.h" 23 #include "hw/nvram/eeprom_at24c.h" 24 #include "hw/sensor/tmp105.h" 25 #include "hw/misc/led.h" 26 #include "hw/qdev-properties.h" 27 #include "system/block-backend.h" 28 #include "system/reset.h" 29 #include "hw/loader.h" 30 #include "qemu/error-report.h" 31 #include "qemu/datadir.h" 32 #include "qemu/units.h" 33 #include "hw/qdev-clock.h" 34 #include "system/system.h" 35 36 static struct arm_boot_info aspeed_board_binfo = { 37 .board_id = -1, /* device-tree-only board */ 38 }; 39 40 struct AspeedMachineState { 41 /* Private */ 42 MachineState parent_obj; 43 /* Public */ 44 45 AspeedSoCState *soc; 46 MemoryRegion boot_rom; 47 bool mmio_exec; 48 uint32_t uart_chosen; 49 char *fmc_model; 50 char *spi_model; 51 uint32_t hw_strap1; 52 }; 53 54 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 55 #if HOST_LONG_BITS == 32 56 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 57 #else 58 #define ASPEED_RAM_SIZE(sz) (sz) 59 #endif 60 61 /* Palmetto hardware value: 0x120CE416 */ 62 #define PALMETTO_BMC_HW_STRAP1 ( \ 63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 65 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 67 SCU_HW_STRAP_VGA_CLASS_CODE | \ 68 SCU_HW_STRAP_LPC_RESET_PIN | \ 69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 71 SCU_HW_STRAP_SPI_WIDTH | \ 72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 74 75 /* TODO: Find the actual hardware value */ 76 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 77 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 78 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 79 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 80 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 81 SCU_HW_STRAP_VGA_CLASS_CODE | \ 82 SCU_HW_STRAP_LPC_RESET_PIN | \ 83 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 84 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 85 SCU_HW_STRAP_SPI_WIDTH | \ 86 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 87 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 88 89 /* TODO: Find the actual hardware value */ 90 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 91 AST2500_HW_STRAP1_DEFAULTS | \ 92 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 93 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 94 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 95 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 96 SCU_HW_STRAP_SPI_WIDTH | \ 97 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 98 99 /* AST2500 evb hardware value: 0xF100C2E6 */ 100 #define AST2500_EVB_HW_STRAP1 (( \ 101 AST2500_HW_STRAP1_DEFAULTS | \ 102 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 103 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 104 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 105 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 106 SCU_HW_STRAP_MAC1_RGMII | \ 107 SCU_HW_STRAP_MAC0_RGMII) & \ 108 ~SCU_HW_STRAP_2ND_BOOT_WDT) 109 110 /* Romulus hardware value: 0xF10AD206 */ 111 #define ROMULUS_BMC_HW_STRAP1 ( \ 112 AST2500_HW_STRAP1_DEFAULTS | \ 113 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 114 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 115 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 119 120 /* Sonorapass hardware value: 0xF100D216 */ 121 #define SONORAPASS_BMC_HW_STRAP1 ( \ 122 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 123 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 124 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 125 SCU_AST2500_HW_STRAP_RESERVED28 | \ 126 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 127 SCU_HW_STRAP_VGA_CLASS_CODE | \ 128 SCU_HW_STRAP_LPC_RESET_PIN | \ 129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 131 SCU_HW_STRAP_VGA_BIOS_ROM | \ 132 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 133 SCU_AST2500_HW_STRAP_RESERVED1) 134 135 #define G220A_BMC_HW_STRAP1 ( \ 136 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 137 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 138 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 139 SCU_AST2500_HW_STRAP_RESERVED28 | \ 140 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 141 SCU_HW_STRAP_2ND_BOOT_WDT | \ 142 SCU_HW_STRAP_VGA_CLASS_CODE | \ 143 SCU_HW_STRAP_LPC_RESET_PIN | \ 144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 145 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 146 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 147 SCU_AST2500_HW_STRAP_RESERVED1) 148 149 /* FP5280G2 hardware value: 0XF100D286 */ 150 #define FP5280G2_BMC_HW_STRAP1 ( \ 151 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 152 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 153 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 154 SCU_AST2500_HW_STRAP_RESERVED28 | \ 155 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 156 SCU_HW_STRAP_VGA_CLASS_CODE | \ 157 SCU_HW_STRAP_LPC_RESET_PIN | \ 158 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 159 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 160 SCU_HW_STRAP_MAC1_RGMII | \ 161 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 162 SCU_AST2500_HW_STRAP_RESERVED1) 163 164 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 165 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 166 167 /* Quanta-Q71l hardware value */ 168 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 169 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 170 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 171 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 172 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 173 SCU_HW_STRAP_VGA_CLASS_CODE | \ 174 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 175 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 176 SCU_HW_STRAP_SPI_WIDTH | \ 177 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 178 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 179 180 /* AST2600 evb hardware value */ 181 #define AST2600_EVB_HW_STRAP1 0x000000C0 182 #define AST2600_EVB_HW_STRAP2 0x00000003 183 184 #ifdef TARGET_AARCH64 185 /* AST2700 evb hardware value */ 186 /* SCU HW Strap1 */ 187 #define AST2700_EVB_HW_STRAP1 0x00000800 188 /* SCUIO HW Strap1 */ 189 #define AST2700_EVB_HW_STRAP2 0x00000700 190 #endif 191 192 /* Rainier hardware value: (QEMU prototype) */ 193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 194 #define RAINIER_BMC_HW_STRAP2 0x80000848 195 196 /* Fuji hardware value */ 197 #define FUJI_BMC_HW_STRAP1 0x00000000 198 #define FUJI_BMC_HW_STRAP2 0x00000000 199 200 /* Bletchley hardware value */ 201 #define BLETCHLEY_BMC_HW_STRAP1 0x00002000 202 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801 203 204 /* GB200NVL hardware value */ 205 #define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 206 #define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 207 208 /* Qualcomm DC-SCM hardware value */ 209 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 210 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 211 212 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 213 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 214 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 215 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 216 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 217 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 218 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 219 220 static void aspeed_write_smpboot(ARMCPU *cpu, 221 const struct arm_boot_info *info) 222 { 223 AddressSpace *as = arm_boot_address_space(cpu, info); 224 static const ARMInsnFixup poll_mailbox_ready[] = { 225 /* 226 * r2 = per-cpu go sign value 227 * r1 = AST_SMP_MBOX_FIELD_ENTRY 228 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 229 */ 230 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 231 { 0xe21000ff }, /* ands r0, r0, #255 */ 232 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 233 { 0xe1822000 }, /* orr r2, r2, r0 */ 234 235 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 236 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 237 238 { 0xe320f002 }, /* wfe */ 239 { 0xe5904000 }, /* ldr r4, [r0] */ 240 { 0xe1520004 }, /* cmp r2, r4 */ 241 { 0x1afffffb }, /* bne <wfe> */ 242 { 0xe591f000 }, /* ldr pc, [r1] */ 243 { AST_SMP_MBOX_GOSIGN }, 244 { AST_SMP_MBOX_FIELD_ENTRY }, 245 { AST_SMP_MBOX_FIELD_GOSIGN }, 246 { 0, FIXUP_TERMINATOR } 247 }; 248 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 249 250 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 251 poll_mailbox_ready, fixupcontext); 252 } 253 254 static void aspeed_reset_secondary(ARMCPU *cpu, 255 const struct arm_boot_info *info) 256 { 257 AddressSpace *as = arm_boot_address_space(cpu, info); 258 CPUState *cs = CPU(cpu); 259 260 /* info->smp_bootreg_addr */ 261 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 262 MEMTXATTRS_UNSPECIFIED, NULL); 263 cpu_set_pc(cs, info->smp_loader_start); 264 } 265 266 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 267 Error **errp) 268 { 269 g_autofree void *storage = NULL; 270 int64_t size; 271 272 /* 273 * The block backend size should have already been 'validated' by 274 * the creation of the m25p80 object. 275 */ 276 size = blk_getlength(blk); 277 if (size <= 0) { 278 error_setg(errp, "failed to get flash size"); 279 return; 280 } 281 282 if (rom_size > size) { 283 rom_size = size; 284 } 285 286 storage = g_malloc0(rom_size); 287 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 288 error_setg(errp, "failed to read the initial flash content"); 289 return; 290 } 291 292 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 293 } 294 295 /* 296 * Create a ROM and copy the flash contents at the expected address 297 * (0x0). Boots faster than execute-in-place. 298 */ 299 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 300 uint64_t rom_size) 301 { 302 AspeedSoCState *soc = bmc->soc; 303 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 304 305 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 306 &error_abort); 307 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 308 &bmc->boot_rom, 1); 309 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 310 rom_size, &error_abort); 311 } 312 313 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" 314 315 /* 316 * This function locates the vbootrom image file specified via the command line 317 * using the -bios option. It loads the specified image into the vbootrom 318 * memory region and handles errors if the file cannot be found or loaded. 319 */ 320 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name, 321 Error **errp) 322 { 323 g_autofree char *filename = NULL; 324 AspeedSoCState *soc = bmc->soc; 325 int ret; 326 327 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 328 if (!filename) { 329 error_setg(errp, "Could not find vbootrom image '%s'", bios_name); 330 return; 331 } 332 333 ret = load_image_mr(filename, &soc->vbootrom); 334 if (ret < 0) { 335 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); 336 return; 337 } 338 } 339 340 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 341 unsigned int count, int unit0) 342 { 343 int i; 344 345 if (!flashtype) { 346 return; 347 } 348 349 for (i = 0; i < count; ++i) { 350 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 351 DeviceState *dev; 352 353 dev = qdev_new(flashtype); 354 if (dinfo) { 355 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 356 } 357 qdev_prop_set_uint8(dev, "cs", i); 358 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 359 } 360 } 361 362 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 363 bool boot_emmc) 364 { 365 DeviceState *card; 366 367 if (!dinfo) { 368 return; 369 } 370 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 371 372 /* 373 * Force the boot properties of the eMMC device only when the 374 * machine is strapped to boot from eMMC. Without these 375 * settings, the machine would not boot. 376 * 377 * This also allows the machine to use an eMMC device without 378 * boot areas when booting from the flash device (or -kernel) 379 * Ideally, the device and its properties should be defined on 380 * the command line. 381 */ 382 if (emmc && boot_emmc) { 383 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 384 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 385 } 386 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 387 &error_fatal); 388 qdev_realize_and_unref(card, 389 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 390 &error_fatal); 391 } 392 393 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 394 { 395 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 396 AspeedSoCState *s = bmc->soc; 397 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 398 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 399 400 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 401 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 402 if (uart == uart_chosen) { 403 continue; 404 } 405 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); 406 } 407 } 408 409 static void aspeed_machine_init(MachineState *machine) 410 { 411 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 412 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 413 AspeedSoCClass *sc; 414 int i; 415 const char *bios_name = NULL; 416 DriveInfo *emmc0 = NULL; 417 bool boot_emmc; 418 419 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 420 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 421 object_unref(OBJECT(bmc->soc)); 422 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 423 424 /* 425 * This will error out if the RAM size is not supported by the 426 * memory controller of the SoC. 427 */ 428 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 429 &error_fatal); 430 431 for (i = 0; i < sc->macs_num; i++) { 432 if ((amc->macs_mask & (1 << i)) && 433 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 434 true, NULL)) { 435 break; /* No configs left; stop asking */ 436 } 437 } 438 439 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 440 &error_abort); 441 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 442 &error_abort); 443 object_property_set_link(OBJECT(bmc->soc), "memory", 444 OBJECT(get_system_memory()), &error_abort); 445 object_property_set_link(OBJECT(bmc->soc), "dram", 446 OBJECT(machine->ram), &error_abort); 447 if (amc->sdhci_wp_inverted) { 448 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 449 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 450 "wp-inverted", true, &error_abort); 451 } 452 } 453 if (machine->kernel_filename) { 454 /* 455 * When booting with a -kernel command line there is no u-boot 456 * that runs to unlock the SCU. In this case set the default to 457 * be unlocked as the kernel expects 458 */ 459 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 460 ASPEED_SCU_PROT_KEY, &error_abort); 461 } 462 connect_serial_hds_to_uarts(bmc); 463 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 464 465 if (defaults_enabled()) { 466 aspeed_board_init_flashes(&bmc->soc->fmc, 467 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 468 amc->num_cs, 0); 469 aspeed_board_init_flashes(&bmc->soc->spi[0], 470 bmc->spi_model ? bmc->spi_model : amc->spi_model, 471 1, amc->num_cs); 472 aspeed_board_init_flashes(&bmc->soc->spi[1], 473 amc->spi2_model, 1, amc->num_cs2); 474 } 475 476 if (machine->kernel_filename && sc->num_cpus > 1) { 477 /* With no u-boot we must set up a boot stub for the secondary CPU */ 478 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 479 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 480 0x80, &error_abort); 481 memory_region_add_subregion(get_system_memory(), 482 AST_SMP_MAILBOX_BASE, smpboot); 483 484 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 485 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 486 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 487 } 488 489 aspeed_board_binfo.ram_size = machine->ram_size; 490 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 491 492 if (amc->i2c_init) { 493 amc->i2c_init(bmc); 494 } 495 496 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 497 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 498 drive_get(IF_SD, 0, i), false, false); 499 } 500 501 boot_emmc = sc->boot_from_emmc(bmc->soc); 502 503 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 504 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 505 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 506 } 507 508 if (!bmc->mmio_exec) { 509 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 510 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 511 512 if (fmc0 && !boot_emmc) { 513 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 514 aspeed_install_boot_rom(bmc, fmc0, rom_size); 515 } else if (emmc0) { 516 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 517 } 518 } 519 520 if (amc->vbootrom) { 521 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; 522 aspeed_load_vbootrom(bmc, bios_name, &error_abort); 523 } 524 525 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 526 } 527 528 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 529 { 530 AspeedSoCState *soc = bmc->soc; 531 DeviceState *dev; 532 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 533 534 /* 535 * The palmetto platform expects a ds3231 RTC but a ds1338 is 536 * enough to provide basic RTC features. Alarms will be missing 537 */ 538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 539 540 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 541 eeprom_buf); 542 543 /* add a TMP423 temperature sensor */ 544 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 545 "tmp423", 0x4c)); 546 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 547 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 548 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 549 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 550 } 551 552 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 553 { 554 AspeedSoCState *soc = bmc->soc; 555 556 /* 557 * The quanta-q71l platform expects tmp75s which are compatible with 558 * tmp105s. 559 */ 560 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 561 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 563 564 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 565 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 566 /* TODO: Add Memory Riser i2c mux and eeproms. */ 567 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 570 571 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 572 573 /* i2c-7 */ 574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 575 /* - i2c@0: pmbus@59 */ 576 /* - i2c@1: pmbus@58 */ 577 /* - i2c@2: pmbus@58 */ 578 /* - i2c@3: pmbus@59 */ 579 580 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 581 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 582 } 583 584 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 585 { 586 AspeedSoCState *soc = bmc->soc; 587 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 588 589 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 590 eeprom_buf); 591 592 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 593 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 594 TYPE_TMP105, 0x4d); 595 } 596 597 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 598 { 599 AspeedSoCState *soc = bmc->soc; 600 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 601 602 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 603 eeprom_buf); 604 605 /* LM75 is compatible with TMP105 driver */ 606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 607 TYPE_TMP105, 0x4d); 608 } 609 610 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 611 { 612 AspeedSoCState *soc = bmc->soc; 613 614 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 615 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 616 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 617 /* TMP421 */ 618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 619 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 620 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 621 622 } 623 624 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 625 { 626 AspeedSoCState *soc = bmc->soc; 627 628 /* 629 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 630 * good enough 631 */ 632 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 633 } 634 635 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 636 { 637 AspeedSoCState *soc = bmc->soc; 638 639 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 640 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 641 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 642 /* TMP421 */ 643 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 645 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 646 } 647 648 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 649 { 650 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 651 TYPE_PCA9552, addr); 652 } 653 654 static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr) 655 { 656 return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 657 TYPE_PCA9554, addr); 658 } 659 660 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 661 { 662 AspeedSoCState *soc = bmc->soc; 663 664 /* bus 2 : */ 665 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 666 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 667 /* bus 2 : pca9546 @ 0x73 */ 668 669 /* bus 3 : pca9548 @ 0x70 */ 670 671 /* bus 4 : */ 672 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 673 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 674 eeprom4_54); 675 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 676 create_pca9552(soc, 4, 0x76); 677 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 678 create_pca9552(soc, 4, 0x77); 679 680 /* bus 6 : */ 681 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 683 /* bus 6 : pca9546 @ 0x73 */ 684 685 /* bus 8 : */ 686 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 687 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 688 eeprom8_56); 689 create_pca9552(soc, 8, 0x60); 690 create_pca9552(soc, 8, 0x61); 691 /* bus 8 : adc128d818 @ 0x1d */ 692 /* bus 8 : adc128d818 @ 0x1f */ 693 694 /* 695 * bus 13 : pca9548 @ 0x71 696 * - channel 3: 697 * - tmm421 @ 0x4c 698 * - tmp421 @ 0x4e 699 * - tmp421 @ 0x4f 700 */ 701 702 } 703 704 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 705 { 706 static const struct { 707 unsigned gpio_id; 708 LEDColor color; 709 const char *description; 710 bool gpio_polarity; 711 } pca1_leds[] = { 712 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 713 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 714 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 715 }; 716 AspeedSoCState *soc = bmc->soc; 717 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 718 DeviceState *dev; 719 LEDState *led; 720 721 /* Bus 3: TODO bmp280@77 */ 722 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 723 qdev_prop_set_string(dev, "description", "pca1"); 724 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 725 aspeed_i2c_get_bus(&soc->i2c, 3), 726 &error_fatal); 727 728 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 729 led = led_create_simple(OBJECT(bmc), 730 pca1_leds[i].gpio_polarity, 731 pca1_leds[i].color, 732 pca1_leds[i].description); 733 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 734 qdev_get_gpio_in(DEVICE(led), 0)); 735 } 736 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 738 0x68); 739 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 740 0x69); 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 742 743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 746 747 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 749 0x4a); 750 751 /* 752 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 753 * good enough 754 */ 755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 756 757 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 758 eeprom_buf); 759 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 760 qdev_prop_set_string(dev, "description", "pca0"); 761 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 762 aspeed_i2c_get_bus(&soc->i2c, 11), 763 &error_fatal); 764 /* Bus 11: TODO ucd90160@64 */ 765 } 766 767 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 768 { 769 AspeedSoCState *soc = bmc->soc; 770 DeviceState *dev; 771 772 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 773 "emc1413", 0x4c)); 774 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 775 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 776 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 777 778 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 779 "emc1413", 0x4c)); 780 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 781 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 782 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 783 784 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 785 "emc1413", 0x4c)); 786 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 787 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 788 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 789 790 static uint8_t eeprom_buf[2 * 1024] = { 791 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 792 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 793 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 794 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 795 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 796 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 797 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 798 }; 799 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 800 eeprom_buf); 801 } 802 803 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 804 { 805 AspeedSoCState *soc = bmc->soc; 806 I2CSlave *i2c_mux; 807 808 /* The at24c256 */ 809 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 810 811 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 812 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 813 0x48); 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 815 0x49); 816 817 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 818 "pca9546", 0x70); 819 /* It expects a TMP112 but a TMP105 is compatible */ 820 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 821 0x4a); 822 823 /* It expects a ds3232 but a ds1338 is good enough */ 824 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 825 826 /* It expects a pca9555 but a pca9552 is compatible */ 827 create_pca9552(soc, 8, 0x30); 828 } 829 830 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 831 { 832 AspeedSoCState *soc = bmc->soc; 833 I2CSlave *i2c_mux; 834 835 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 836 837 create_pca9552(soc, 3, 0x61); 838 839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 840 0x68); 841 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 842 0x69); 843 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 844 0x6a); 845 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 846 0x6b); 847 848 /* The rainier expects a TMP275 but a TMP105 is compatible */ 849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 850 0x48); 851 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 852 0x49); 853 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 854 0x4a); 855 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 856 "pca9546", 0x70); 857 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 858 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 859 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 860 create_pca9552(soc, 4, 0x60); 861 862 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 863 0x48); 864 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 865 0x49); 866 create_pca9552(soc, 5, 0x60); 867 create_pca9552(soc, 5, 0x61); 868 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 869 "pca9546", 0x70); 870 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 871 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 872 873 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 874 0x48); 875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 876 0x4a); 877 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 878 0x4b); 879 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 880 "pca9546", 0x70); 881 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 882 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 883 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 884 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 885 886 create_pca9552(soc, 7, 0x30); 887 create_pca9552(soc, 7, 0x31); 888 create_pca9552(soc, 7, 0x32); 889 create_pca9552(soc, 7, 0x33); 890 create_pca9552(soc, 7, 0x60); 891 create_pca9552(soc, 7, 0x61); 892 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 893 /* Bus 7: TODO si7021-a20@20 */ 894 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 895 0x48); 896 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 897 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 898 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 899 900 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 901 0x48); 902 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 903 0x4a); 904 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 905 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 906 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 907 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 908 create_pca9552(soc, 8, 0x60); 909 create_pca9552(soc, 8, 0x61); 910 /* Bus 8: ucd90320@11 */ 911 /* Bus 8: ucd90320@b */ 912 /* Bus 8: ucd90320@c */ 913 914 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 915 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 916 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 917 918 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 919 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 920 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 921 922 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 923 0x48); 924 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 925 0x49); 926 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 927 "pca9546", 0x70); 928 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 929 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 930 create_pca9552(soc, 11, 0x60); 931 932 933 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 934 create_pca9552(soc, 13, 0x60); 935 936 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 937 create_pca9552(soc, 14, 0x60); 938 939 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 940 create_pca9552(soc, 15, 0x60); 941 } 942 943 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 944 I2CBus **channels) 945 { 946 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 947 for (int i = 0; i < 8; i++) { 948 channels[i] = pca954x_i2c_get_bus(mux, i); 949 } 950 } 951 952 #define TYPE_LM75 TYPE_TMP105 953 #define TYPE_TMP75 TYPE_TMP105 954 #define TYPE_TMP422 "tmp422" 955 956 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 957 { 958 AspeedSoCState *soc = bmc->soc; 959 I2CBus *i2c[144] = {}; 960 961 for (int i = 0; i < 16; i++) { 962 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 963 } 964 I2CBus *i2c180 = i2c[2]; 965 I2CBus *i2c480 = i2c[8]; 966 I2CBus *i2c600 = i2c[11]; 967 968 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 969 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 970 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 971 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 972 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 973 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 974 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 975 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 976 for (int i = 0; i < 8; i++) { 977 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 978 } 979 980 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 981 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 982 983 /* 984 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 985 * 24c02 size is 2Kbits or 256 bytes 986 */ 987 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 988 at24c_eeprom_init(i2c[20], 0x50, 256); 989 at24c_eeprom_init(i2c[22], 0x52, 256); 990 991 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 992 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 993 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 994 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 995 996 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 997 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 998 999 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 1000 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 1001 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 1002 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 1003 1004 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 1005 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 1006 1007 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 1008 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 1009 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 1010 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 1011 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 1012 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 1013 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 1014 1015 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 1016 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 1017 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 1018 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 1019 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 1020 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 1021 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 1022 at24c_eeprom_init(i2c[28], 0x50, 256); 1023 1024 for (int i = 0; i < 8; i++) { 1025 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 1026 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 1027 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 1028 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 1029 } 1030 } 1031 1032 #define TYPE_TMP421 "tmp421" 1033 #define TYPE_DS1338 "ds1338" 1034 1035 /* Catalina hardware value */ 1036 #define CATALINA_BMC_HW_STRAP1 0x00002002 1037 #define CATALINA_BMC_HW_STRAP2 0x00000800 1038 1039 #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1040 1041 static void catalina_bmc_i2c_init(AspeedMachineState *bmc) 1042 { 1043 /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ 1044 1045 AspeedSoCState *soc = bmc->soc; 1046 I2CBus *i2c[16] = {}; 1047 I2CSlave *i2c_mux; 1048 1049 /* busses 0-15 are all used. */ 1050 for (int i = 0; i < ARRAY_SIZE(i2c); i++) { 1051 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1052 } 1053 1054 /* &i2c0 */ 1055 /* i2c-mux@71 (PCA9546) on i2c0 */ 1056 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); 1057 1058 /* i2c-mux@72 (PCA9546) on i2c0 */ 1059 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); 1060 1061 /* i2c0mux1ch1 */ 1062 /* io_expander7 - pca9535@20 */ 1063 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1064 TYPE_PCA9552, 0x20); 1065 /* eeprom@50 */ 1066 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1067 1068 /* i2c-mux@73 (PCA9546) on i2c0 */ 1069 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); 1070 1071 /* i2c-mux@75 (PCA9546) on i2c0 */ 1072 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); 1073 1074 /* i2c-mux@76 (PCA9546) on i2c0 */ 1075 i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); 1076 1077 /* i2c0mux4ch1 */ 1078 /* io_expander8 - pca9535@21 */ 1079 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), 1080 TYPE_PCA9552, 0x21); 1081 /* eeprom@50 */ 1082 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); 1083 1084 /* i2c-mux@77 (PCA9546) on i2c0 */ 1085 i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); 1086 1087 1088 /* &i2c1 */ 1089 /* i2c-mux@70 (PCA9548) on i2c1 */ 1090 i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); 1091 /* i2c1mux0ch0 */ 1092 /* ina238@41 - no model */ 1093 /* ina238@42 - no model */ 1094 /* ina238@44 - no model */ 1095 /* i2c1mux0ch1 */ 1096 /* ina238@41 - no model */ 1097 /* ina238@43 - no model */ 1098 /* i2c1mux0ch4 */ 1099 /* ltc4287@42 - no model */ 1100 /* ltc4287@43 - no model */ 1101 1102 /* i2c1mux0ch5 */ 1103 /* eeprom@54 */ 1104 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); 1105 /* tpm75@4f */ 1106 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); 1107 1108 /* i2c1mux0ch6 */ 1109 /* io_expander5 - pca9554@27 */ 1110 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1111 TYPE_PCA9554, 0x27); 1112 /* io_expander6 - pca9555@25 */ 1113 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), 1114 TYPE_PCA9552, 0x25); 1115 /* eeprom@51 */ 1116 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); 1117 1118 /* i2c1mux0ch7 */ 1119 /* eeprom@53 */ 1120 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); 1121 /* temperature-sensor@4b - tmp75 */ 1122 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); 1123 1124 /* &i2c2 */ 1125 /* io_expander0 - pca9555@20 */ 1126 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); 1127 /* io_expander0 - pca9555@21 */ 1128 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); 1129 /* io_expander0 - pca9555@27 */ 1130 i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); 1131 /* eeprom@50 */ 1132 at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); 1133 /* eeprom@51 */ 1134 at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); 1135 1136 /* &i2c5 */ 1137 /* i2c-mux@70 (PCA9548) on i2c5 */ 1138 i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); 1139 /* i2c5mux0ch6 */ 1140 /* eeprom@52 */ 1141 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); 1142 /* i2c5mux0ch7 */ 1143 /* ina230@40 - no model */ 1144 /* ina230@41 - no model */ 1145 /* ina230@44 - no model */ 1146 /* ina230@45 - no model */ 1147 1148 /* &i2c6 */ 1149 /* io_expander3 - pca9555@21 */ 1150 i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); 1151 /* rtc@6f - nct3018y */ 1152 i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); 1153 1154 /* &i2c9 */ 1155 /* io_expander4 - pca9555@4f */ 1156 i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); 1157 /* temperature-sensor@4b - tpm75 */ 1158 i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); 1159 /* eeprom@50 */ 1160 at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); 1161 /* eeprom@56 */ 1162 at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); 1163 1164 /* &i2c10 */ 1165 /* temperature-sensor@1f - tpm421 */ 1166 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); 1167 /* eeprom@50 */ 1168 at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); 1169 1170 /* &i2c11 */ 1171 /* ssif-bmc@10 - no model */ 1172 1173 /* &i2c12 */ 1174 /* eeprom@50 */ 1175 at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); 1176 1177 /* &i2c13 */ 1178 /* eeprom@50 */ 1179 at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); 1180 /* eeprom@54 */ 1181 at24c_eeprom_init(i2c[13], 0x54, 256); 1182 /* eeprom@55 */ 1183 at24c_eeprom_init(i2c[13], 0x55, 256); 1184 /* eeprom@57 */ 1185 at24c_eeprom_init(i2c[13], 0x57, 256); 1186 1187 /* &i2c14 */ 1188 /* io_expander9 - pca9555@10 */ 1189 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); 1190 /* io_expander10 - pca9555@11 */ 1191 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); 1192 /* io_expander11 - pca9555@12 */ 1193 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); 1194 /* io_expander12 - pca9555@13 */ 1195 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); 1196 /* io_expander13 - pca9555@14 */ 1197 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); 1198 /* io_expander14 - pca9555@15 */ 1199 i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); 1200 1201 /* &i2c15 */ 1202 /* temperature-sensor@1f - tmp421 */ 1203 i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); 1204 /* eeprom@52 */ 1205 at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); 1206 } 1207 1208 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1209 { 1210 AspeedSoCState *soc = bmc->soc; 1211 I2CBus *i2c[13] = {}; 1212 for (int i = 0; i < 13; i++) { 1213 if ((i == 8) || (i == 11)) { 1214 continue; 1215 } 1216 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1217 } 1218 1219 /* Bus 0 - 5 all have the same config. */ 1220 for (int i = 0; i < 6; i++) { 1221 /* Missing model: ti,ina230 @ 0x45 */ 1222 /* Missing model: mps,mp5023 @ 0x40 */ 1223 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1224 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1225 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1226 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1227 /* Missing model: fsc,fusb302 @ 0x22 */ 1228 } 1229 1230 /* Bus 6 */ 1231 at24c_eeprom_init(i2c[6], 0x56, 65536); 1232 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1233 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1234 1235 1236 /* Bus 7 */ 1237 at24c_eeprom_init(i2c[7], 0x54, 65536); 1238 1239 /* Bus 9 */ 1240 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1241 1242 /* Bus 10 */ 1243 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1244 /* Missing model: ti,hdc1080 @ 0x40 */ 1245 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1246 1247 /* Bus 12 */ 1248 /* Missing model: adi,adm1278 @ 0x11 */ 1249 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1250 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1251 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1252 } 1253 1254 1255 static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc) 1256 { 1257 AspeedSoCState *soc = bmc->soc; 1258 I2CBus *i2c[15] = {}; 1259 DeviceState *dev; 1260 for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) { 1261 if ((i == 11) || (i == 12) || (i == 13)) { 1262 continue; 1263 } 1264 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1265 } 1266 1267 /* Bus 5 Expander */ 1268 create_pca9554(soc, 4, 0x21); 1269 1270 /* Mux I2c Expanders */ 1271 i2c_slave_create_simple(i2c[5], "pca9546", 0x71); 1272 i2c_slave_create_simple(i2c[5], "pca9546", 0x72); 1273 i2c_slave_create_simple(i2c[5], "pca9546", 0x73); 1274 i2c_slave_create_simple(i2c[5], "pca9546", 0x75); 1275 i2c_slave_create_simple(i2c[5], "pca9546", 0x76); 1276 i2c_slave_create_simple(i2c[5], "pca9546", 0x77); 1277 1278 /* Bus 10 */ 1279 dev = DEVICE(create_pca9554(soc, 9, 0x20)); 1280 1281 /* Set FPGA_READY */ 1282 object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal); 1283 1284 create_pca9554(soc, 9, 0x21); 1285 at24c_eeprom_init(i2c[9], 0x50, 64 * KiB); 1286 at24c_eeprom_init(i2c[9], 0x51, 64 * KiB); 1287 1288 /* Bus 11 */ 1289 at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid, 1290 gb200nvl_bmc_fruid_len); 1291 } 1292 1293 static void fby35_i2c_init(AspeedMachineState *bmc) 1294 { 1295 AspeedSoCState *soc = bmc->soc; 1296 I2CBus *i2c[16]; 1297 1298 for (int i = 0; i < 16; i++) { 1299 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1300 } 1301 1302 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1303 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1304 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1305 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1306 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1307 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1308 1309 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1310 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1311 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1312 fby35_nic_fruid_len); 1313 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1314 fby35_bb_fruid_len); 1315 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1316 fby35_bmc_fruid_len); 1317 1318 /* 1319 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1320 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1321 * each. 1322 */ 1323 } 1324 1325 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1326 { 1327 AspeedSoCState *soc = bmc->soc; 1328 1329 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1330 } 1331 1332 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1333 { 1334 AspeedSoCState *soc = bmc->soc; 1335 I2CSlave *therm_mux, *cpuvr_mux; 1336 1337 /* Create the generic DC-SCM hardware */ 1338 qcom_dc_scm_bmc_i2c_init(bmc); 1339 1340 /* Now create the Firework specific hardware */ 1341 1342 /* I2C7 CPUVR MUX */ 1343 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1344 "pca9546", 0x70); 1345 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1346 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1347 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1348 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1349 1350 /* I2C8 Thermal Diodes*/ 1351 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1352 "pca9548", 0x70); 1353 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1354 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1355 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1356 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1357 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1358 1359 /* I2C9 Fan Controller (MAX31785) */ 1360 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1361 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1362 } 1363 1364 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1365 { 1366 return ASPEED_MACHINE(obj)->mmio_exec; 1367 } 1368 1369 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1370 { 1371 ASPEED_MACHINE(obj)->mmio_exec = value; 1372 } 1373 1374 static void aspeed_machine_instance_init(Object *obj) 1375 { 1376 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1377 1378 ASPEED_MACHINE(obj)->mmio_exec = false; 1379 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1380 } 1381 1382 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1383 { 1384 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1385 return g_strdup(bmc->fmc_model); 1386 } 1387 1388 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1389 { 1390 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1391 1392 g_free(bmc->fmc_model); 1393 bmc->fmc_model = g_strdup(value); 1394 } 1395 1396 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1397 { 1398 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1399 return g_strdup(bmc->spi_model); 1400 } 1401 1402 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1403 { 1404 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1405 1406 g_free(bmc->spi_model); 1407 bmc->spi_model = g_strdup(value); 1408 } 1409 1410 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1411 { 1412 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1413 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1414 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1415 1416 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1417 } 1418 1419 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1420 { 1421 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1422 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1423 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1424 int val; 1425 int uart_first = aspeed_uart_first(sc); 1426 int uart_last = aspeed_uart_last(sc); 1427 1428 if (sscanf(value, "uart%u", &val) != 1) { 1429 error_setg(errp, "Bad value for \"uart\" property"); 1430 return; 1431 } 1432 1433 /* The number of UART depends on the SoC */ 1434 if (val < uart_first || val > uart_last) { 1435 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1436 uart_first, uart_last); 1437 return; 1438 } 1439 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1440 } 1441 1442 static void aspeed_machine_class_props_init(ObjectClass *oc) 1443 { 1444 object_class_property_add_bool(oc, "execute-in-place", 1445 aspeed_get_mmio_exec, 1446 aspeed_set_mmio_exec); 1447 object_class_property_set_description(oc, "execute-in-place", 1448 "boot directly from CE0 flash device"); 1449 1450 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1451 aspeed_set_bmc_console); 1452 object_class_property_set_description(oc, "bmc-console", 1453 "Change the default UART to \"uartX\""); 1454 1455 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1456 aspeed_set_fmc_model); 1457 object_class_property_set_description(oc, "fmc-model", 1458 "Change the FMC Flash model"); 1459 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1460 aspeed_set_spi_model); 1461 object_class_property_set_description(oc, "spi-model", 1462 "Change the SPI Flash model"); 1463 } 1464 1465 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1466 { 1467 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1468 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1469 1470 mc->default_cpus = sc->num_cpus; 1471 mc->min_cpus = sc->num_cpus; 1472 mc->max_cpus = sc->num_cpus; 1473 mc->valid_cpu_types = sc->valid_cpu_types; 1474 } 1475 1476 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1477 { 1478 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1479 1480 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1481 } 1482 1483 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1484 Error **errp) 1485 { 1486 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1487 1488 if (value) { 1489 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1490 } else { 1491 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1492 } 1493 } 1494 1495 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1496 { 1497 object_class_property_add_bool(oc, "boot-emmc", 1498 aspeed_machine_ast2600_get_boot_from_emmc, 1499 aspeed_machine_ast2600_set_boot_from_emmc); 1500 object_class_property_set_description(oc, "boot-emmc", 1501 "Set or unset boot from EMMC"); 1502 } 1503 1504 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 1505 { 1506 MachineClass *mc = MACHINE_CLASS(oc); 1507 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1508 1509 mc->init = aspeed_machine_init; 1510 mc->no_floppy = 1; 1511 mc->no_cdrom = 1; 1512 mc->no_parallel = 1; 1513 mc->default_ram_id = "ram"; 1514 amc->macs_mask = ASPEED_MAC0_ON; 1515 amc->uart_default = ASPEED_DEV_UART5; 1516 1517 aspeed_machine_class_props_init(oc); 1518 } 1519 1520 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, 1521 const void *data) 1522 { 1523 MachineClass *mc = MACHINE_CLASS(oc); 1524 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1525 1526 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1527 amc->soc_name = "ast2400-a1"; 1528 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1529 amc->fmc_model = "n25q256a"; 1530 amc->spi_model = "mx25l25635f"; 1531 amc->num_cs = 1; 1532 amc->i2c_init = palmetto_bmc_i2c_init; 1533 mc->auto_create_sdcard = true; 1534 mc->default_ram_size = 256 * MiB; 1535 aspeed_machine_class_init_cpus_defaults(mc); 1536 }; 1537 1538 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, 1539 const void *data) 1540 { 1541 MachineClass *mc = MACHINE_CLASS(oc); 1542 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1543 1544 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1545 amc->soc_name = "ast2400-a1"; 1546 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1547 amc->fmc_model = "n25q256a"; 1548 amc->spi_model = "mx25l25635e"; 1549 amc->num_cs = 1; 1550 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1551 mc->auto_create_sdcard = true; 1552 mc->default_ram_size = 128 * MiB; 1553 aspeed_machine_class_init_cpus_defaults(mc); 1554 } 1555 1556 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1557 const void *data) 1558 { 1559 MachineClass *mc = MACHINE_CLASS(oc); 1560 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1561 1562 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1563 amc->soc_name = "ast2400-a1"; 1564 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1565 amc->fmc_model = "mx25l25635e"; 1566 amc->spi_model = "mx25l25635e"; 1567 amc->num_cs = 1; 1568 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1569 amc->i2c_init = palmetto_bmc_i2c_init; 1570 mc->auto_create_sdcard = true; 1571 mc->default_ram_size = 256 * MiB; 1572 aspeed_machine_class_init_cpus_defaults(mc); 1573 } 1574 1575 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1576 const void *data) 1577 { 1578 MachineClass *mc = MACHINE_CLASS(oc); 1579 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1580 1581 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1582 amc->soc_name = "ast2500-a1"; 1583 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1584 amc->fmc_model = "mx25l25635e"; 1585 amc->spi_model = "mx25l25635e"; 1586 amc->num_cs = 1; 1587 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1588 amc->i2c_init = palmetto_bmc_i2c_init; 1589 mc->auto_create_sdcard = true; 1590 mc->default_ram_size = 512 * MiB; 1591 aspeed_machine_class_init_cpus_defaults(mc); 1592 } 1593 1594 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, 1595 const void *data) 1596 { 1597 MachineClass *mc = MACHINE_CLASS(oc); 1598 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1599 1600 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1601 amc->soc_name = "ast2500-a1"; 1602 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1603 amc->fmc_model = "mx25l25635e"; 1604 amc->spi_model = "mx25l25635f"; 1605 amc->num_cs = 1; 1606 amc->i2c_init = ast2500_evb_i2c_init; 1607 mc->auto_create_sdcard = true; 1608 mc->default_ram_size = 512 * MiB; 1609 aspeed_machine_class_init_cpus_defaults(mc); 1610 }; 1611 1612 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, 1613 const void *data) 1614 { 1615 MachineClass *mc = MACHINE_CLASS(oc); 1616 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1617 1618 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1619 amc->soc_name = "ast2500-a1"; 1620 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1621 amc->hw_strap2 = 0; 1622 amc->fmc_model = "n25q256a"; 1623 amc->spi_model = "mx25l25635e"; 1624 amc->num_cs = 2; 1625 amc->i2c_init = yosemitev2_bmc_i2c_init; 1626 mc->auto_create_sdcard = true; 1627 mc->default_ram_size = 512 * MiB; 1628 aspeed_machine_class_init_cpus_defaults(mc); 1629 }; 1630 1631 static void aspeed_machine_romulus_class_init(ObjectClass *oc, 1632 const void *data) 1633 { 1634 MachineClass *mc = MACHINE_CLASS(oc); 1635 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1636 1637 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1638 amc->soc_name = "ast2500-a1"; 1639 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1640 amc->fmc_model = "n25q256a"; 1641 amc->spi_model = "mx66l1g45g"; 1642 amc->num_cs = 2; 1643 amc->i2c_init = romulus_bmc_i2c_init; 1644 mc->auto_create_sdcard = true; 1645 mc->default_ram_size = 512 * MiB; 1646 aspeed_machine_class_init_cpus_defaults(mc); 1647 }; 1648 1649 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, 1650 const void *data) 1651 { 1652 MachineClass *mc = MACHINE_CLASS(oc); 1653 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1654 1655 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1656 amc->soc_name = "ast2500-a1"; 1657 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1658 amc->hw_strap2 = 0; 1659 amc->fmc_model = "n25q256a"; 1660 amc->spi_model = "mx25l25635e"; 1661 amc->num_cs = 2; 1662 amc->i2c_init = tiogapass_bmc_i2c_init; 1663 mc->auto_create_sdcard = true; 1664 mc->default_ram_size = 1 * GiB; 1665 aspeed_machine_class_init_cpus_defaults(mc); 1666 }; 1667 1668 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, 1669 const void *data) 1670 { 1671 MachineClass *mc = MACHINE_CLASS(oc); 1672 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1673 1674 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1675 amc->soc_name = "ast2500-a1"; 1676 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1677 amc->fmc_model = "mx66l1g45g"; 1678 amc->spi_model = "mx66l1g45g"; 1679 amc->num_cs = 2; 1680 amc->i2c_init = sonorapass_bmc_i2c_init; 1681 mc->auto_create_sdcard = true; 1682 mc->default_ram_size = 512 * MiB; 1683 aspeed_machine_class_init_cpus_defaults(mc); 1684 }; 1685 1686 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, 1687 const void *data) 1688 { 1689 MachineClass *mc = MACHINE_CLASS(oc); 1690 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1691 1692 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1693 amc->soc_name = "ast2500-a1"; 1694 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1695 amc->fmc_model = "mx25l25635f"; 1696 amc->spi_model = "mx66l1g45g"; 1697 amc->num_cs = 2; 1698 amc->i2c_init = witherspoon_bmc_i2c_init; 1699 mc->auto_create_sdcard = true; 1700 mc->default_ram_size = 512 * MiB; 1701 aspeed_machine_class_init_cpus_defaults(mc); 1702 }; 1703 1704 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, 1705 const void *data) 1706 { 1707 MachineClass *mc = MACHINE_CLASS(oc); 1708 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1709 1710 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1711 amc->soc_name = "ast2600-a3"; 1712 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1713 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1714 amc->fmc_model = "mx66u51235f"; 1715 amc->spi_model = "mx66u51235f"; 1716 amc->num_cs = 1; 1717 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1718 ASPEED_MAC3_ON; 1719 amc->sdhci_wp_inverted = true; 1720 amc->i2c_init = ast2600_evb_i2c_init; 1721 mc->auto_create_sdcard = true; 1722 mc->default_ram_size = 1 * GiB; 1723 aspeed_machine_class_init_cpus_defaults(mc); 1724 aspeed_machine_ast2600_class_emmc_init(oc); 1725 }; 1726 1727 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data) 1728 { 1729 MachineClass *mc = MACHINE_CLASS(oc); 1730 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1731 1732 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1733 amc->soc_name = "ast2500-a1"; 1734 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1735 amc->fmc_model = "n25q512a"; 1736 amc->spi_model = "mx25l25635e"; 1737 amc->num_cs = 2; 1738 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1739 amc->i2c_init = g220a_bmc_i2c_init; 1740 mc->auto_create_sdcard = true; 1741 mc->default_ram_size = 1024 * MiB; 1742 aspeed_machine_class_init_cpus_defaults(mc); 1743 }; 1744 1745 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, 1746 const void *data) 1747 { 1748 MachineClass *mc = MACHINE_CLASS(oc); 1749 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1750 1751 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1752 amc->soc_name = "ast2500-a1"; 1753 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1754 amc->fmc_model = "n25q512a"; 1755 amc->spi_model = "mx25l25635e"; 1756 amc->num_cs = 2; 1757 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1758 amc->i2c_init = fp5280g2_bmc_i2c_init; 1759 mc->auto_create_sdcard = true; 1760 mc->default_ram_size = 512 * MiB; 1761 aspeed_machine_class_init_cpus_defaults(mc); 1762 }; 1763 1764 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) 1765 { 1766 MachineClass *mc = MACHINE_CLASS(oc); 1767 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1768 1769 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1770 amc->soc_name = "ast2600-a3"; 1771 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1772 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1773 amc->fmc_model = "mx66l1g45g"; 1774 amc->spi_model = "mx66l1g45g"; 1775 amc->num_cs = 2; 1776 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1777 amc->i2c_init = rainier_bmc_i2c_init; 1778 mc->auto_create_sdcard = true; 1779 mc->default_ram_size = 1 * GiB; 1780 aspeed_machine_class_init_cpus_defaults(mc); 1781 aspeed_machine_ast2600_class_emmc_init(oc); 1782 }; 1783 1784 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1785 1786 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data) 1787 { 1788 MachineClass *mc = MACHINE_CLASS(oc); 1789 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1790 1791 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1792 amc->soc_name = "ast2600-a3"; 1793 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1794 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1795 amc->fmc_model = "mx66l1g45g"; 1796 amc->spi_model = "mx66l1g45g"; 1797 amc->num_cs = 2; 1798 amc->macs_mask = ASPEED_MAC3_ON; 1799 amc->i2c_init = fuji_bmc_i2c_init; 1800 amc->uart_default = ASPEED_DEV_UART1; 1801 mc->auto_create_sdcard = true; 1802 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1803 aspeed_machine_class_init_cpus_defaults(mc); 1804 }; 1805 1806 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1807 1808 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, 1809 const void *data) 1810 { 1811 MachineClass *mc = MACHINE_CLASS(oc); 1812 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1813 1814 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1815 amc->soc_name = "ast2600-a3"; 1816 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1817 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1818 amc->fmc_model = "w25q01jvq"; 1819 amc->spi_model = NULL; 1820 amc->num_cs = 2; 1821 amc->macs_mask = ASPEED_MAC2_ON; 1822 amc->i2c_init = bletchley_bmc_i2c_init; 1823 mc->auto_create_sdcard = true; 1824 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1825 aspeed_machine_class_init_cpus_defaults(mc); 1826 } 1827 1828 static void aspeed_machine_catalina_class_init(ObjectClass *oc, 1829 const void *data) 1830 { 1831 MachineClass *mc = MACHINE_CLASS(oc); 1832 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1833 1834 mc->desc = "Facebook Catalina BMC (Cortex-A7)"; 1835 amc->soc_name = "ast2600-a3"; 1836 amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; 1837 amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; 1838 amc->fmc_model = "w25q01jvq"; 1839 amc->spi_model = NULL; 1840 amc->num_cs = 2; 1841 amc->macs_mask = ASPEED_MAC2_ON; 1842 amc->i2c_init = catalina_bmc_i2c_init; 1843 mc->auto_create_sdcard = true; 1844 mc->default_ram_size = CATALINA_BMC_RAM_SIZE; 1845 aspeed_machine_class_init_cpus_defaults(mc); 1846 aspeed_machine_ast2600_class_emmc_init(oc); 1847 } 1848 1849 #define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB) 1850 1851 static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc, 1852 const void *data) 1853 { 1854 MachineClass *mc = MACHINE_CLASS(oc); 1855 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1856 1857 mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)"; 1858 amc->soc_name = "ast2600-a3"; 1859 amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1; 1860 amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2; 1861 amc->fmc_model = "mx66u51235f"; 1862 amc->spi_model = "mx66u51235f"; 1863 amc->num_cs = 2; 1864 1865 amc->spi2_model = "mx66u51235f"; 1866 amc->num_cs2 = 1; 1867 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1868 amc->i2c_init = gb200nvl_bmc_i2c_init; 1869 mc->default_ram_size = GB200NVL_BMC_RAM_SIZE; 1870 aspeed_machine_class_init_cpus_defaults(mc); 1871 aspeed_machine_ast2600_class_emmc_init(oc); 1872 } 1873 1874 static void fby35_reset(MachineState *state, ResetType type) 1875 { 1876 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1877 AspeedGPIOState *gpio = &bmc->soc->gpio; 1878 1879 qemu_devices_reset(type); 1880 1881 /* Board ID: 7 (Class-1, 4 slots) */ 1882 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1883 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1884 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1885 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1886 1887 /* Slot presence pins, inverse polarity. (False means present) */ 1888 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1889 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1890 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1891 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1892 1893 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1894 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1895 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1896 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1897 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1898 } 1899 1900 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data) 1901 { 1902 MachineClass *mc = MACHINE_CLASS(oc); 1903 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1904 1905 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1906 mc->reset = fby35_reset; 1907 amc->fmc_model = "mx66l1g45g"; 1908 amc->num_cs = 2; 1909 amc->macs_mask = ASPEED_MAC3_ON; 1910 amc->i2c_init = fby35_i2c_init; 1911 mc->auto_create_sdcard = true; 1912 /* FIXME: Replace this macro with something more general */ 1913 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1914 aspeed_machine_class_init_cpus_defaults(mc); 1915 } 1916 1917 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1918 /* Main SYSCLK frequency in Hz (200MHz) */ 1919 #define SYSCLK_FRQ 200000000ULL 1920 1921 static void aspeed_minibmc_machine_init(MachineState *machine) 1922 { 1923 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1924 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1925 Clock *sysclk; 1926 1927 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1928 clock_set_hz(sysclk, SYSCLK_FRQ); 1929 1930 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1931 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1932 object_unref(OBJECT(bmc->soc)); 1933 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1934 1935 object_property_set_link(OBJECT(bmc->soc), "memory", 1936 OBJECT(get_system_memory()), &error_abort); 1937 connect_serial_hds_to_uarts(bmc); 1938 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1939 1940 if (defaults_enabled()) { 1941 aspeed_board_init_flashes(&bmc->soc->fmc, 1942 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1943 amc->num_cs, 1944 0); 1945 1946 aspeed_board_init_flashes(&bmc->soc->spi[0], 1947 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1948 amc->num_cs, amc->num_cs); 1949 1950 aspeed_board_init_flashes(&bmc->soc->spi[1], 1951 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1952 amc->num_cs, (amc->num_cs * 2)); 1953 } 1954 1955 if (amc->i2c_init) { 1956 amc->i2c_init(bmc); 1957 } 1958 1959 armv7m_load_kernel(ARM_CPU(first_cpu), 1960 machine->kernel_filename, 1961 0, 1962 AST1030_INTERNAL_FLASH_SIZE); 1963 } 1964 1965 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1966 { 1967 AspeedSoCState *soc = bmc->soc; 1968 1969 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1970 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1971 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1972 1973 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1974 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1975 } 1976 1977 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1978 const void *data) 1979 { 1980 MachineClass *mc = MACHINE_CLASS(oc); 1981 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1982 1983 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1984 amc->soc_name = "ast1030-a1"; 1985 amc->hw_strap1 = 0; 1986 amc->hw_strap2 = 0; 1987 mc->init = aspeed_minibmc_machine_init; 1988 amc->i2c_init = ast1030_evb_i2c_init; 1989 mc->default_ram_size = 0; 1990 amc->fmc_model = "w25q80bl"; 1991 amc->spi_model = "w25q256"; 1992 amc->num_cs = 2; 1993 amc->macs_mask = 0; 1994 aspeed_machine_class_init_cpus_defaults(mc); 1995 } 1996 1997 #ifdef TARGET_AARCH64 1998 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1999 { 2000 AspeedSoCState *soc = bmc->soc; 2001 2002 /* LM75 is compatible with TMP105 driver */ 2003 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 2004 TYPE_TMP105, 0x4d); 2005 } 2006 2007 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, 2008 const void *data) 2009 { 2010 MachineClass *mc = MACHINE_CLASS(oc); 2011 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 2012 2013 mc->alias = "ast2700-evb"; 2014 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; 2015 amc->soc_name = "ast2700-a0"; 2016 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 2017 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 2018 amc->fmc_model = "w25q01jvq"; 2019 amc->spi_model = "w25q512jv"; 2020 amc->num_cs = 2; 2021 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 2022 amc->uart_default = ASPEED_DEV_UART12; 2023 amc->i2c_init = ast2700_evb_i2c_init; 2024 amc->vbootrom = true; 2025 mc->auto_create_sdcard = true; 2026 mc->default_ram_size = 1 * GiB; 2027 aspeed_machine_class_init_cpus_defaults(mc); 2028 } 2029 2030 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, 2031 const void *data) 2032 { 2033 MachineClass *mc = MACHINE_CLASS(oc); 2034 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 2035 2036 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; 2037 amc->soc_name = "ast2700-a1"; 2038 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 2039 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 2040 amc->fmc_model = "w25q01jvq"; 2041 amc->spi_model = "w25q512jv"; 2042 amc->num_cs = 2; 2043 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 2044 amc->uart_default = ASPEED_DEV_UART12; 2045 amc->i2c_init = ast2700_evb_i2c_init; 2046 amc->vbootrom = true; 2047 mc->auto_create_sdcard = true; 2048 mc->default_ram_size = 1 * GiB; 2049 aspeed_machine_class_init_cpus_defaults(mc); 2050 } 2051 #endif 2052 2053 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 2054 const void *data) 2055 { 2056 MachineClass *mc = MACHINE_CLASS(oc); 2057 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 2058 2059 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 2060 amc->soc_name = "ast2600-a3"; 2061 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 2062 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 2063 amc->fmc_model = "n25q512a"; 2064 amc->spi_model = "n25q512a"; 2065 amc->num_cs = 2; 2066 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 2067 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 2068 mc->auto_create_sdcard = true; 2069 mc->default_ram_size = 1 * GiB; 2070 aspeed_machine_class_init_cpus_defaults(mc); 2071 }; 2072 2073 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 2074 const void *data) 2075 { 2076 MachineClass *mc = MACHINE_CLASS(oc); 2077 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 2078 2079 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 2080 amc->soc_name = "ast2600-a3"; 2081 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 2082 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 2083 amc->fmc_model = "n25q512a"; 2084 amc->spi_model = "n25q512a"; 2085 amc->num_cs = 2; 2086 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 2087 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 2088 mc->auto_create_sdcard = true; 2089 mc->default_ram_size = 1 * GiB; 2090 aspeed_machine_class_init_cpus_defaults(mc); 2091 }; 2092 2093 static const TypeInfo aspeed_machine_types[] = { 2094 { 2095 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 2096 .parent = TYPE_ASPEED_MACHINE, 2097 .class_init = aspeed_machine_palmetto_class_init, 2098 }, { 2099 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 2100 .parent = TYPE_ASPEED_MACHINE, 2101 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 2102 }, { 2103 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 2104 .parent = TYPE_ASPEED_MACHINE, 2105 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 2106 }, { 2107 .name = MACHINE_TYPE_NAME("ast2500-evb"), 2108 .parent = TYPE_ASPEED_MACHINE, 2109 .class_init = aspeed_machine_ast2500_evb_class_init, 2110 }, { 2111 .name = MACHINE_TYPE_NAME("romulus-bmc"), 2112 .parent = TYPE_ASPEED_MACHINE, 2113 .class_init = aspeed_machine_romulus_class_init, 2114 }, { 2115 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 2116 .parent = TYPE_ASPEED_MACHINE, 2117 .class_init = aspeed_machine_sonorapass_class_init, 2118 }, { 2119 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 2120 .parent = TYPE_ASPEED_MACHINE, 2121 .class_init = aspeed_machine_witherspoon_class_init, 2122 }, { 2123 .name = MACHINE_TYPE_NAME("ast2600-evb"), 2124 .parent = TYPE_ASPEED_MACHINE, 2125 .class_init = aspeed_machine_ast2600_evb_class_init, 2126 }, { 2127 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 2128 .parent = TYPE_ASPEED_MACHINE, 2129 .class_init = aspeed_machine_yosemitev2_class_init, 2130 }, { 2131 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 2132 .parent = TYPE_ASPEED_MACHINE, 2133 .class_init = aspeed_machine_tiogapass_class_init, 2134 }, { 2135 .name = MACHINE_TYPE_NAME("g220a-bmc"), 2136 .parent = TYPE_ASPEED_MACHINE, 2137 .class_init = aspeed_machine_g220a_class_init, 2138 }, { 2139 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 2140 .parent = TYPE_ASPEED_MACHINE, 2141 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 2142 }, { 2143 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 2144 .parent = TYPE_ASPEED_MACHINE, 2145 .class_init = aspeed_machine_qcom_firework_class_init, 2146 }, { 2147 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 2148 .parent = TYPE_ASPEED_MACHINE, 2149 .class_init = aspeed_machine_fp5280g2_class_init, 2150 }, { 2151 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 2152 .parent = TYPE_ASPEED_MACHINE, 2153 .class_init = aspeed_machine_quanta_q71l_class_init, 2154 }, { 2155 .name = MACHINE_TYPE_NAME("rainier-bmc"), 2156 .parent = TYPE_ASPEED_MACHINE, 2157 .class_init = aspeed_machine_rainier_class_init, 2158 }, { 2159 .name = MACHINE_TYPE_NAME("fuji-bmc"), 2160 .parent = TYPE_ASPEED_MACHINE, 2161 .class_init = aspeed_machine_fuji_class_init, 2162 }, { 2163 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 2164 .parent = TYPE_ASPEED_MACHINE, 2165 .class_init = aspeed_machine_bletchley_class_init, 2166 }, { 2167 .name = MACHINE_TYPE_NAME("gb200nvl-bmc"), 2168 .parent = TYPE_ASPEED_MACHINE, 2169 .class_init = aspeed_machine_gb200nvl_class_init, 2170 }, { 2171 .name = MACHINE_TYPE_NAME("catalina-bmc"), 2172 .parent = TYPE_ASPEED_MACHINE, 2173 .class_init = aspeed_machine_catalina_class_init, 2174 }, { 2175 .name = MACHINE_TYPE_NAME("fby35-bmc"), 2176 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 2177 .class_init = aspeed_machine_fby35_class_init, 2178 }, { 2179 .name = MACHINE_TYPE_NAME("ast1030-evb"), 2180 .parent = TYPE_ASPEED_MACHINE, 2181 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 2182 #ifdef TARGET_AARCH64 2183 }, { 2184 .name = MACHINE_TYPE_NAME("ast2700a0-evb"), 2185 .parent = TYPE_ASPEED_MACHINE, 2186 .class_init = aspeed_machine_ast2700a0_evb_class_init, 2187 }, { 2188 .name = MACHINE_TYPE_NAME("ast2700a1-evb"), 2189 .parent = TYPE_ASPEED_MACHINE, 2190 .class_init = aspeed_machine_ast2700a1_evb_class_init, 2191 #endif 2192 }, { 2193 .name = TYPE_ASPEED_MACHINE, 2194 .parent = TYPE_MACHINE, 2195 .instance_size = sizeof(AspeedMachineState), 2196 .instance_init = aspeed_machine_instance_init, 2197 .class_size = sizeof(AspeedMachineClass), 2198 .class_init = aspeed_machine_class_init, 2199 .abstract = true, 2200 } 2201 }; 2202 2203 DEFINE_TYPES(aspeed_machine_types) 2204