xref: /openbmc/qemu/hw/arm/aspeed.c (revision 88dd060d)
1 /*
2  * OpenPOWER Palmetto BMC
3  *
4  * Andrew Jeffery <andrew@aj.id.au>
5  *
6  * Copyright 2016 IBM Corp.
7  *
8  * This code is licensed under the GPL version 2 or later.  See
9  * the COPYING file in the top-level directory.
10  */
11 
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/nvram/eeprom_at24c.h"
23 #include "hw/sensor/tmp105.h"
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/reset.h"
28 #include "hw/loader.h"
29 #include "qemu/error-report.h"
30 #include "qemu/units.h"
31 #include "hw/qdev-clock.h"
32 #include "sysemu/sysemu.h"
33 
34 static struct arm_boot_info aspeed_board_binfo = {
35     .board_id = -1, /* device-tree-only board */
36 };
37 
38 struct AspeedMachineState {
39     /* Private */
40     MachineState parent_obj;
41     /* Public */
42 
43     AspeedSoCState *soc;
44     MemoryRegion boot_rom;
45     bool mmio_exec;
46     uint32_t uart_chosen;
47     char *fmc_model;
48     char *spi_model;
49     uint32_t hw_strap1;
50 };
51 
52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
53 #if HOST_LONG_BITS == 32
54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
55 #else
56 #define ASPEED_RAM_SIZE(sz) (sz)
57 #endif
58 
59 /* Palmetto hardware value: 0x120CE416 */
60 #define PALMETTO_BMC_HW_STRAP1 (                                        \
61         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
62         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
63         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
64         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
65         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
66         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
67         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
68         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69         SCU_HW_STRAP_SPI_WIDTH |                                        \
70         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
71         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72 
73 /* TODO: Find the actual hardware value */
74 #define SUPERMICROX11_BMC_HW_STRAP1 (                                   \
75         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
76         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) |                           \
77         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
78         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
79         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
80         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
81         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
82         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
83         SCU_HW_STRAP_SPI_WIDTH |                                        \
84         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
85         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
86 
87 /* TODO: Find the actual hardware value */
88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
89         AST2500_HW_STRAP1_DEFAULTS |                                    \
90         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
91         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
92         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
93         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
94         SCU_HW_STRAP_SPI_WIDTH |                                        \
95         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
96 
97 /* AST2500 evb hardware value: 0xF100C2E6 */
98 #define AST2500_EVB_HW_STRAP1 ((                                        \
99         AST2500_HW_STRAP1_DEFAULTS |                                    \
100         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
101         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
102         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
103         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
104         SCU_HW_STRAP_MAC1_RGMII |                                       \
105         SCU_HW_STRAP_MAC0_RGMII) &                                      \
106         ~SCU_HW_STRAP_2ND_BOOT_WDT)
107 
108 /* Romulus hardware value: 0xF10AD206 */
109 #define ROMULUS_BMC_HW_STRAP1 (                                         \
110         AST2500_HW_STRAP1_DEFAULTS |                                    \
111         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
112         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
113         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
114         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
115         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
116         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
117 
118 /* Sonorapass hardware value: 0xF100D216 */
119 #define SONORAPASS_BMC_HW_STRAP1 (                                      \
120         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
121         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
122         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
123         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
124         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
125         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
126         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
127         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
128         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
129         SCU_HW_STRAP_VGA_BIOS_ROM |                                     \
130         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
131         SCU_AST2500_HW_STRAP_RESERVED1)
132 
133 #define G220A_BMC_HW_STRAP1 (                                      \
134         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
135         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
136         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
137         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
138         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
139         SCU_HW_STRAP_2ND_BOOT_WDT |                                     \
140         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
141         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
142         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
143         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
144         SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) |                       \
145         SCU_AST2500_HW_STRAP_RESERVED1)
146 
147 /* FP5280G2 hardware value: 0XF100D286 */
148 #define FP5280G2_BMC_HW_STRAP1 (                                      \
149         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
150         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
151         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
152         SCU_AST2500_HW_STRAP_RESERVED28 |                               \
153         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
154         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
155         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
156         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) |                \
157         SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) |     \
158         SCU_HW_STRAP_MAC1_RGMII |                                       \
159         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
160         SCU_AST2500_HW_STRAP_RESERVED1)
161 
162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
164 
165 /* Quanta-Q71l hardware value */
166 #define QUANTA_Q71L_BMC_HW_STRAP1 (                                     \
167         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) |               \
168         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
169         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
170         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) |       \
171         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
172         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) |          \
173         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
174         SCU_HW_STRAP_SPI_WIDTH |                                        \
175         SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) |                        \
176         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
177 
178 /* AST2600 evb hardware value */
179 #define AST2600_EVB_HW_STRAP1 0x000000C0
180 #define AST2600_EVB_HW_STRAP2 0x00000003
181 
182 #ifdef TARGET_AARCH64
183 /* AST2700 evb hardware value */
184 #define AST2700_EVB_HW_STRAP1 0x000000C0
185 #define AST2700_EVB_HW_STRAP2 0x00000003
186 #endif
187 
188 /* Tacoma hardware value */
189 #define TACOMA_BMC_HW_STRAP1  0x00000000
190 #define TACOMA_BMC_HW_STRAP2  0x00000040
191 
192 /* Rainier hardware value: (QEMU prototype) */
193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
194 #define RAINIER_BMC_HW_STRAP2 0x80000848
195 
196 /* Fuji hardware value */
197 #define FUJI_BMC_HW_STRAP1    0x00000000
198 #define FUJI_BMC_HW_STRAP2    0x00000000
199 
200 /* Bletchley hardware value */
201 /* TODO: Leave same as EVB for now. */
202 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
203 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
204 
205 /* Qualcomm DC-SCM hardware value */
206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
207 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
208 
209 #define AST_SMP_MAILBOX_BASE            0x1e6e2180
210 #define AST_SMP_MBOX_FIELD_ENTRY        (AST_SMP_MAILBOX_BASE + 0x0)
211 #define AST_SMP_MBOX_FIELD_GOSIGN       (AST_SMP_MAILBOX_BASE + 0x4)
212 #define AST_SMP_MBOX_FIELD_READY        (AST_SMP_MAILBOX_BASE + 0x8)
213 #define AST_SMP_MBOX_FIELD_POLLINSN     (AST_SMP_MAILBOX_BASE + 0xc)
214 #define AST_SMP_MBOX_CODE               (AST_SMP_MAILBOX_BASE + 0x10)
215 #define AST_SMP_MBOX_GOSIGN             0xabbaab00
216 
217 static void aspeed_write_smpboot(ARMCPU *cpu,
218                                  const struct arm_boot_info *info)
219 {
220     AddressSpace *as = arm_boot_address_space(cpu, info);
221     static const ARMInsnFixup poll_mailbox_ready[] = {
222         /*
223          * r2 = per-cpu go sign value
224          * r1 = AST_SMP_MBOX_FIELD_ENTRY
225          * r0 = AST_SMP_MBOX_FIELD_GOSIGN
226          */
227         { 0xee100fb0 },  /* mrc     p15, 0, r0, c0, c0, 5 */
228         { 0xe21000ff },  /* ands    r0, r0, #255          */
229         { 0xe59f201c },  /* ldr     r2, [pc, #28]         */
230         { 0xe1822000 },  /* orr     r2, r2, r0            */
231 
232         { 0xe59f1018 },  /* ldr     r1, [pc, #24]         */
233         { 0xe59f0018 },  /* ldr     r0, [pc, #24]         */
234 
235         { 0xe320f002 },  /* wfe                           */
236         { 0xe5904000 },  /* ldr     r4, [r0]              */
237         { 0xe1520004 },  /* cmp     r2, r4                */
238         { 0x1afffffb },  /* bne     <wfe>                 */
239         { 0xe591f000 },  /* ldr     pc, [r1]              */
240         { AST_SMP_MBOX_GOSIGN },
241         { AST_SMP_MBOX_FIELD_ENTRY },
242         { AST_SMP_MBOX_FIELD_GOSIGN },
243         { 0, FIXUP_TERMINATOR }
244     };
245     static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
246 
247     arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
248                          poll_mailbox_ready, fixupcontext);
249 }
250 
251 static void aspeed_reset_secondary(ARMCPU *cpu,
252                                    const struct arm_boot_info *info)
253 {
254     AddressSpace *as = arm_boot_address_space(cpu, info);
255     CPUState *cs = CPU(cpu);
256 
257     /* info->smp_bootreg_addr */
258     address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
259                                MEMTXATTRS_UNSPECIFIED, NULL);
260     cpu_set_pc(cs, info->smp_loader_start);
261 }
262 
263 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
264                            Error **errp)
265 {
266     g_autofree void *storage = NULL;
267     int64_t size;
268 
269     /*
270      * The block backend size should have already been 'validated' by
271      * the creation of the m25p80 object.
272      */
273     size = blk_getlength(blk);
274     if (size <= 0) {
275         error_setg(errp, "failed to get flash size");
276         return;
277     }
278 
279     if (rom_size > size) {
280         rom_size = size;
281     }
282 
283     storage = g_malloc0(rom_size);
284     if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
285         error_setg(errp, "failed to read the initial flash content");
286         return;
287     }
288 
289     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
290 }
291 
292 /*
293  * Create a ROM and copy the flash contents at the expected address
294  * (0x0). Boots faster than execute-in-place.
295  */
296 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
297                                     uint64_t rom_size)
298 {
299     AspeedSoCState *soc = bmc->soc;
300     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
301 
302     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
303                            &error_abort);
304     memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
305                                         &bmc->boot_rom, 1);
306     write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
307                    rom_size, &error_abort);
308 }
309 
310 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
311                                       unsigned int count, int unit0)
312 {
313     int i;
314 
315     if (!flashtype) {
316         return;
317     }
318 
319     for (i = 0; i < count; ++i) {
320         DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
321         DeviceState *dev;
322 
323         dev = qdev_new(flashtype);
324         if (dinfo) {
325             qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
326         }
327         qdev_prop_set_uint8(dev, "cs", i);
328         qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
329     }
330 }
331 
332 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
333                                bool boot_emmc)
334 {
335         DeviceState *card;
336 
337         if (!dinfo) {
338             return;
339         }
340         card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
341 
342         /*
343          * Force the boot properties of the eMMC device only when the
344          * machine is strapped to boot from eMMC. Without these
345          * settings, the machine would not boot.
346          *
347          * This also allows the machine to use an eMMC device without
348          * boot areas when booting from the flash device (or -kernel)
349          * Ideally, the device and its properties should be defined on
350          * the command line.
351          */
352         if (emmc && boot_emmc) {
353             qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
354             qdev_prop_set_uint8(card, "boot-config", 0x1 << 3);
355         }
356         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
357                                 &error_fatal);
358         qdev_realize_and_unref(card,
359                                qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
360                                &error_fatal);
361 }
362 
363 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
364 {
365     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
366     AspeedSoCState *s = bmc->soc;
367     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
368     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
369 
370     aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
371     for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
372         if (uart == uart_chosen) {
373             continue;
374         }
375         aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
376     }
377 }
378 
379 static void aspeed_machine_init(MachineState *machine)
380 {
381     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
382     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
383     AspeedSoCClass *sc;
384     int i;
385     DriveInfo *emmc0 = NULL;
386     bool boot_emmc;
387 
388     bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
389     object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
390     object_unref(OBJECT(bmc->soc));
391     sc = ASPEED_SOC_GET_CLASS(bmc->soc);
392 
393     /*
394      * This will error out if the RAM size is not supported by the
395      * memory controller of the SoC.
396      */
397     object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
398                              &error_fatal);
399 
400     for (i = 0; i < sc->macs_num; i++) {
401         if ((amc->macs_mask & (1 << i)) &&
402             !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
403                                        true, NULL)) {
404             break; /* No configs left; stop asking */
405         }
406     }
407 
408     object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
409                             &error_abort);
410     object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
411                             &error_abort);
412     object_property_set_link(OBJECT(bmc->soc), "memory",
413                              OBJECT(get_system_memory()), &error_abort);
414     object_property_set_link(OBJECT(bmc->soc), "dram",
415                              OBJECT(machine->ram), &error_abort);
416     if (machine->kernel_filename) {
417         /*
418          * When booting with a -kernel command line there is no u-boot
419          * that runs to unlock the SCU. In this case set the default to
420          * be unlocked as the kernel expects
421          */
422         object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
423                                 ASPEED_SCU_PROT_KEY, &error_abort);
424     }
425     connect_serial_hds_to_uarts(bmc);
426     qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
427 
428     if (defaults_enabled()) {
429         aspeed_board_init_flashes(&bmc->soc->fmc,
430                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
431                               amc->num_cs, 0);
432         aspeed_board_init_flashes(&bmc->soc->spi[0],
433                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
434                               1, amc->num_cs);
435     }
436 
437     if (machine->kernel_filename && sc->num_cpus > 1) {
438         /* With no u-boot we must set up a boot stub for the secondary CPU */
439         MemoryRegion *smpboot = g_new(MemoryRegion, 1);
440         memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
441                                0x80, &error_abort);
442         memory_region_add_subregion(get_system_memory(),
443                                     AST_SMP_MAILBOX_BASE, smpboot);
444 
445         aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
446         aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
447         aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
448     }
449 
450     aspeed_board_binfo.ram_size = machine->ram_size;
451     aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
452 
453     if (amc->i2c_init) {
454         amc->i2c_init(bmc);
455     }
456 
457     for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
458         sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
459                            drive_get(IF_SD, 0, i), false, false);
460     }
461 
462     boot_emmc = sc->boot_from_emmc(bmc->soc);
463 
464     if (bmc->soc->emmc.num_slots) {
465         emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
466         sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
467     }
468 
469     if (!bmc->mmio_exec) {
470         DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
471         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
472 
473         if (fmc0 && !boot_emmc) {
474             uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
475             aspeed_install_boot_rom(bmc, fmc0, rom_size);
476         } else if (emmc0) {
477             aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
478         }
479     }
480 
481     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
482 }
483 
484 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
485 {
486     AspeedSoCState *soc = bmc->soc;
487     DeviceState *dev;
488     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
489 
490     /*
491      * The palmetto platform expects a ds3231 RTC but a ds1338 is
492      * enough to provide basic RTC features. Alarms will be missing
493      */
494     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
495 
496     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
497                           eeprom_buf);
498 
499     /* add a TMP423 temperature sensor */
500     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
501                                          "tmp423", 0x4c));
502     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
503     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
504     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
505     object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
506 }
507 
508 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
509 {
510     AspeedSoCState *soc = bmc->soc;
511 
512     /*
513      * The quanta-q71l platform expects tmp75s which are compatible with
514      * tmp105s.
515      */
516     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
517     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
518     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
519 
520     /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
521     /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
522     /* TODO: Add Memory Riser i2c mux and eeproms. */
523 
524     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
525     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
526 
527     /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
528 
529     /* i2c-7 */
530     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
531     /*        - i2c@0: pmbus@59 */
532     /*        - i2c@1: pmbus@58 */
533     /*        - i2c@2: pmbus@58 */
534     /*        - i2c@3: pmbus@59 */
535 
536     /* TODO: i2c-7: Add PDB FRU eeprom@52 */
537     /* TODO: i2c-8: Add BMC FRU eeprom@50 */
538 }
539 
540 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
541 {
542     AspeedSoCState *soc = bmc->soc;
543     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
544 
545     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
546                           eeprom_buf);
547 
548     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
549     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
550                      TYPE_TMP105, 0x4d);
551 }
552 
553 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
554 {
555     AspeedSoCState *soc = bmc->soc;
556     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
557 
558     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
559                           eeprom_buf);
560 
561     /* LM75 is compatible with TMP105 driver */
562     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
563                      TYPE_TMP105, 0x4d);
564 }
565 
566 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
567 {
568     AspeedSoCState *soc = bmc->soc;
569 
570     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
571     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
572                           yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
573     /* TMP421 */
574     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
575     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
576     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
577 
578 }
579 
580 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
581 {
582     AspeedSoCState *soc = bmc->soc;
583 
584     /*
585      * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
586      * good enough
587      */
588     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
589 }
590 
591 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
592 {
593     AspeedSoCState *soc = bmc->soc;
594 
595     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
596     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
597                           tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
598     /* TMP421 */
599     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
600     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
601     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
602 }
603 
604 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
605 {
606     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
607                             TYPE_PCA9552, addr);
608 }
609 
610 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
611 {
612     AspeedSoCState *soc = bmc->soc;
613 
614     /* bus 2 : */
615     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
616     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
617     /* bus 2 : pca9546 @ 0x73 */
618 
619     /* bus 3 : pca9548 @ 0x70 */
620 
621     /* bus 4 : */
622     uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
623     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
624                           eeprom4_54);
625     /* PCA9539 @ 0x76, but PCA9552 is compatible */
626     create_pca9552(soc, 4, 0x76);
627     /* PCA9539 @ 0x77, but PCA9552 is compatible */
628     create_pca9552(soc, 4, 0x77);
629 
630     /* bus 6 : */
631     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
632     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
633     /* bus 6 : pca9546 @ 0x73 */
634 
635     /* bus 8 : */
636     uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
637     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
638                           eeprom8_56);
639     create_pca9552(soc, 8, 0x60);
640     create_pca9552(soc, 8, 0x61);
641     /* bus 8 : adc128d818 @ 0x1d */
642     /* bus 8 : adc128d818 @ 0x1f */
643 
644     /*
645      * bus 13 : pca9548 @ 0x71
646      *      - channel 3:
647      *          - tmm421 @ 0x4c
648      *          - tmp421 @ 0x4e
649      *          - tmp421 @ 0x4f
650      */
651 
652 }
653 
654 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
655 {
656     static const struct {
657         unsigned gpio_id;
658         LEDColor color;
659         const char *description;
660         bool gpio_polarity;
661     } pca1_leds[] = {
662         {13, LED_COLOR_GREEN, "front-fault-4",  GPIO_POLARITY_ACTIVE_LOW},
663         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
664         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
665     };
666     AspeedSoCState *soc = bmc->soc;
667     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
668     DeviceState *dev;
669     LEDState *led;
670 
671     /* Bus 3: TODO bmp280@77 */
672     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
673     qdev_prop_set_string(dev, "description", "pca1");
674     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
675                                 aspeed_i2c_get_bus(&soc->i2c, 3),
676                                 &error_fatal);
677 
678     for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
679         led = led_create_simple(OBJECT(bmc),
680                                 pca1_leds[i].gpio_polarity,
681                                 pca1_leds[i].color,
682                                 pca1_leds[i].description);
683         qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
684                               qdev_get_gpio_in(DEVICE(led), 0));
685     }
686     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
687     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
688     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
689     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
690 
691     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
692     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
693                      0x4a);
694 
695     /*
696      * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
697      * good enough
698      */
699     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
700 
701     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
702                           eeprom_buf);
703     dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
704     qdev_prop_set_string(dev, "description", "pca0");
705     i2c_slave_realize_and_unref(I2C_SLAVE(dev),
706                                 aspeed_i2c_get_bus(&soc->i2c, 11),
707                                 &error_fatal);
708     /* Bus 11: TODO ucd90160@64 */
709 }
710 
711 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
712 {
713     AspeedSoCState *soc = bmc->soc;
714     DeviceState *dev;
715 
716     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
717                                          "emc1413", 0x4c));
718     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
719     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
720     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
721 
722     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
723                                          "emc1413", 0x4c));
724     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
725     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
726     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
727 
728     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
729                                          "emc1413", 0x4c));
730     object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
731     object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
732     object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
733 
734     static uint8_t eeprom_buf[2 * 1024] = {
735             0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
736             0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
737             0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
738             0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
739             0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
740             0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
741             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
742     };
743     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
744                           eeprom_buf);
745 }
746 
747 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
748 {
749     AspeedSoCState *soc = bmc->soc;
750     I2CSlave *i2c_mux;
751 
752     /* The at24c256 */
753     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
754 
755     /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
756     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
757                      0x48);
758     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
759                      0x49);
760 
761     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
762                      "pca9546", 0x70);
763     /* It expects a TMP112 but a TMP105 is compatible */
764     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
765                      0x4a);
766 
767     /* It expects a ds3232 but a ds1338 is good enough */
768     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
769 
770     /* It expects a pca9555 but a pca9552 is compatible */
771     create_pca9552(soc, 8, 0x30);
772 }
773 
774 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
775 {
776     AspeedSoCState *soc = bmc->soc;
777     I2CSlave *i2c_mux;
778 
779     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
780 
781     create_pca9552(soc, 3, 0x61);
782 
783     /* The rainier expects a TMP275 but a TMP105 is compatible */
784     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
785                      0x48);
786     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
787                      0x49);
788     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
789                      0x4a);
790     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
791                                       "pca9546", 0x70);
792     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
793     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
794     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
795     create_pca9552(soc, 4, 0x60);
796 
797     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
798                      0x48);
799     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
800                      0x49);
801     create_pca9552(soc, 5, 0x60);
802     create_pca9552(soc, 5, 0x61);
803     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
804                                       "pca9546", 0x70);
805     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
806     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
807 
808     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
809                      0x48);
810     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
811                      0x4a);
812     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
813                      0x4b);
814     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
815                                       "pca9546", 0x70);
816     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
817     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
818     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
819     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
820 
821     create_pca9552(soc, 7, 0x30);
822     create_pca9552(soc, 7, 0x31);
823     create_pca9552(soc, 7, 0x32);
824     create_pca9552(soc, 7, 0x33);
825     create_pca9552(soc, 7, 0x60);
826     create_pca9552(soc, 7, 0x61);
827     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
828     /* Bus 7: TODO si7021-a20@20 */
829     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
830                      0x48);
831     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
832     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
833     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
834 
835     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
836                      0x48);
837     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
838                      0x4a);
839     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
840                           64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
841     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
842                           64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
843     create_pca9552(soc, 8, 0x60);
844     create_pca9552(soc, 8, 0x61);
845     /* Bus 8: ucd90320@11 */
846     /* Bus 8: ucd90320@b */
847     /* Bus 8: ucd90320@c */
848 
849     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
850     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
851     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
852 
853     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
854     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
855     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
856 
857     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
858                      0x48);
859     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
860                      0x49);
861     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
862                                       "pca9546", 0x70);
863     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
864     at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
865     create_pca9552(soc, 11, 0x60);
866 
867 
868     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
869     create_pca9552(soc, 13, 0x60);
870 
871     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
872     create_pca9552(soc, 14, 0x60);
873 
874     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
875     create_pca9552(soc, 15, 0x60);
876 }
877 
878 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
879                                  I2CBus **channels)
880 {
881     I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
882     for (int i = 0; i < 8; i++) {
883         channels[i] = pca954x_i2c_get_bus(mux, i);
884     }
885 }
886 
887 #define TYPE_LM75 TYPE_TMP105
888 #define TYPE_TMP75 TYPE_TMP105
889 #define TYPE_TMP422 "tmp422"
890 
891 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
892 {
893     AspeedSoCState *soc = bmc->soc;
894     I2CBus *i2c[144] = {};
895 
896     for (int i = 0; i < 16; i++) {
897         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
898     }
899     I2CBus *i2c180 = i2c[2];
900     I2CBus *i2c480 = i2c[8];
901     I2CBus *i2c600 = i2c[11];
902 
903     get_pca9548_channels(i2c180, 0x70, &i2c[16]);
904     get_pca9548_channels(i2c480, 0x70, &i2c[24]);
905     /* NOTE: The device tree skips [32, 40) in the alias numbering */
906     get_pca9548_channels(i2c600, 0x77, &i2c[40]);
907     get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
908     get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
909     get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
910     get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
911     for (int i = 0; i < 8; i++) {
912         get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
913     }
914 
915     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
916     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
917 
918     /*
919      * EEPROM 24c64 size is 64Kbits or 8 Kbytes
920      *        24c02 size is 2Kbits or 256 bytes
921      */
922     at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
923     at24c_eeprom_init(i2c[20], 0x50, 256);
924     at24c_eeprom_init(i2c[22], 0x52, 256);
925 
926     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
927     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
928     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
929     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
930 
931     at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
932     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
933 
934     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
935     at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
936     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
937     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
938 
939     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
940     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
941 
942     at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
943     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
944     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
945     at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
946     at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
947     at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
948     at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
949 
950     at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
951     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
952     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
953     at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
954     at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
955     at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
956     at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
957     at24c_eeprom_init(i2c[28], 0x50, 256);
958 
959     for (int i = 0; i < 8; i++) {
960         at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
961         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
962         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
963         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
964     }
965 }
966 
967 #define TYPE_TMP421 "tmp421"
968 
969 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
970 {
971     AspeedSoCState *soc = bmc->soc;
972     I2CBus *i2c[13] = {};
973     for (int i = 0; i < 13; i++) {
974         if ((i == 8) || (i == 11)) {
975             continue;
976         }
977         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
978     }
979 
980     /* Bus 0 - 5 all have the same config. */
981     for (int i = 0; i < 6; i++) {
982         /* Missing model: ti,ina230 @ 0x45 */
983         /* Missing model: mps,mp5023 @ 0x40 */
984         i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
985         /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
986         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
987         i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
988         /* Missing model: fsc,fusb302 @ 0x22 */
989     }
990 
991     /* Bus 6 */
992     at24c_eeprom_init(i2c[6], 0x56, 65536);
993     /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
994     i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
995 
996 
997     /* Bus 7 */
998     at24c_eeprom_init(i2c[7], 0x54, 65536);
999 
1000     /* Bus 9 */
1001     i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
1002 
1003     /* Bus 10 */
1004     i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
1005     /* Missing model: ti,hdc1080 @ 0x40 */
1006     i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
1007 
1008     /* Bus 12 */
1009     /* Missing model: adi,adm1278 @ 0x11 */
1010     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1011     i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1012     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1013 }
1014 
1015 static void fby35_i2c_init(AspeedMachineState *bmc)
1016 {
1017     AspeedSoCState *soc = bmc->soc;
1018     I2CBus *i2c[16];
1019 
1020     for (int i = 0; i < 16; i++) {
1021         i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1022     }
1023 
1024     i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1025     i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1026     /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1027     i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1028     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1029     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1030 
1031     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1032     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1033     at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1034                           fby35_nic_fruid_len);
1035     at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1036                           fby35_bb_fruid_len);
1037     at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1038                           fby35_bmc_fruid_len);
1039 
1040     /*
1041      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1042      * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1043      * each.
1044      */
1045 }
1046 
1047 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1048 {
1049     AspeedSoCState *soc = bmc->soc;
1050 
1051     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1052 }
1053 
1054 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1055 {
1056     AspeedSoCState *soc = bmc->soc;
1057     I2CSlave *therm_mux, *cpuvr_mux;
1058 
1059     /* Create the generic DC-SCM hardware */
1060     qcom_dc_scm_bmc_i2c_init(bmc);
1061 
1062     /* Now create the Firework specific hardware */
1063 
1064     /* I2C7 CPUVR MUX */
1065     cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1066                                         "pca9546", 0x70);
1067     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1068     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1069     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1070     i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1071 
1072     /* I2C8 Thermal Diodes*/
1073     therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1074                                         "pca9548", 0x70);
1075     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1076     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1077     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1078     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1079     i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1080 
1081     /* I2C9 Fan Controller (MAX31785) */
1082     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1083     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1084 }
1085 
1086 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1087 {
1088     return ASPEED_MACHINE(obj)->mmio_exec;
1089 }
1090 
1091 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1092 {
1093     ASPEED_MACHINE(obj)->mmio_exec = value;
1094 }
1095 
1096 static void aspeed_machine_instance_init(Object *obj)
1097 {
1098     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1099 
1100     ASPEED_MACHINE(obj)->mmio_exec = false;
1101     ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1102 }
1103 
1104 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1105 {
1106     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1107     return g_strdup(bmc->fmc_model);
1108 }
1109 
1110 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1111 {
1112     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1113 
1114     g_free(bmc->fmc_model);
1115     bmc->fmc_model = g_strdup(value);
1116 }
1117 
1118 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1119 {
1120     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1121     return g_strdup(bmc->spi_model);
1122 }
1123 
1124 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1125 {
1126     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1127 
1128     g_free(bmc->spi_model);
1129     bmc->spi_model = g_strdup(value);
1130 }
1131 
1132 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1133 {
1134     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1135     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1136     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1137 
1138     return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1139 }
1140 
1141 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1142 {
1143     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1144     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1145     AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1146     int val;
1147     int uart_first = aspeed_uart_first(sc);
1148     int uart_last = aspeed_uart_last(sc);
1149 
1150     if (sscanf(value, "uart%u", &val) != 1) {
1151         error_setg(errp, "Bad value for \"uart\" property");
1152         return;
1153     }
1154 
1155     /* The number of UART depends on the SoC */
1156     if (val < uart_first || val > uart_last) {
1157         error_setg(errp, "\"uart\" should be in range [%d - %d]",
1158                    uart_first, uart_last);
1159         return;
1160     }
1161     bmc->uart_chosen = val + ASPEED_DEV_UART0;
1162 }
1163 
1164 static void aspeed_machine_class_props_init(ObjectClass *oc)
1165 {
1166     object_class_property_add_bool(oc, "execute-in-place",
1167                                    aspeed_get_mmio_exec,
1168                                    aspeed_set_mmio_exec);
1169     object_class_property_set_description(oc, "execute-in-place",
1170                            "boot directly from CE0 flash device");
1171 
1172     object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1173                                   aspeed_set_bmc_console);
1174     object_class_property_set_description(oc, "bmc-console",
1175                            "Change the default UART to \"uartX\"");
1176 
1177     object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1178                                    aspeed_set_fmc_model);
1179     object_class_property_set_description(oc, "fmc-model",
1180                                           "Change the FMC Flash model");
1181     object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1182                                    aspeed_set_spi_model);
1183     object_class_property_set_description(oc, "spi-model",
1184                                           "Change the SPI Flash model");
1185 }
1186 
1187 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1188 {
1189     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1190     AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1191 
1192     mc->default_cpus = sc->num_cpus;
1193     mc->min_cpus = sc->num_cpus;
1194     mc->max_cpus = sc->num_cpus;
1195     mc->valid_cpu_types = sc->valid_cpu_types;
1196 }
1197 
1198 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1199 {
1200     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1201 
1202     return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1203 }
1204 
1205 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1206                                                       Error **errp)
1207 {
1208     AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1209 
1210     if (value) {
1211         bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1212     } else {
1213         bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1214     }
1215 }
1216 
1217 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1218 {
1219     object_class_property_add_bool(oc, "boot-emmc",
1220                                    aspeed_machine_ast2600_get_boot_from_emmc,
1221                                    aspeed_machine_ast2600_set_boot_from_emmc);
1222     object_class_property_set_description(oc, "boot-emmc",
1223                                           "Set or unset boot from EMMC");
1224 }
1225 
1226 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1227 {
1228     MachineClass *mc = MACHINE_CLASS(oc);
1229     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1230 
1231     mc->init = aspeed_machine_init;
1232     mc->no_floppy = 1;
1233     mc->no_cdrom = 1;
1234     mc->no_parallel = 1;
1235     mc->default_ram_id = "ram";
1236     amc->macs_mask = ASPEED_MAC0_ON;
1237     amc->uart_default = ASPEED_DEV_UART5;
1238 
1239     aspeed_machine_class_props_init(oc);
1240 }
1241 
1242 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1243 {
1244     MachineClass *mc = MACHINE_CLASS(oc);
1245     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1246 
1247     mc->desc       = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1248     amc->soc_name  = "ast2400-a1";
1249     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1250     amc->fmc_model = "n25q256a";
1251     amc->spi_model = "mx25l25635f";
1252     amc->num_cs    = 1;
1253     amc->i2c_init  = palmetto_bmc_i2c_init;
1254     mc->default_ram_size       = 256 * MiB;
1255     aspeed_machine_class_init_cpus_defaults(mc);
1256 };
1257 
1258 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1259 {
1260     MachineClass *mc = MACHINE_CLASS(oc);
1261     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1262 
1263     mc->desc       = "Quanta-Q71l BMC (ARM926EJ-S)";
1264     amc->soc_name  = "ast2400-a1";
1265     amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1266     amc->fmc_model = "n25q256a";
1267     amc->spi_model = "mx25l25635e";
1268     amc->num_cs    = 1;
1269     amc->i2c_init  = quanta_q71l_bmc_i2c_init;
1270     mc->default_ram_size       = 128 * MiB;
1271     aspeed_machine_class_init_cpus_defaults(mc);
1272 }
1273 
1274 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1275                                                         void *data)
1276 {
1277     MachineClass *mc = MACHINE_CLASS(oc);
1278     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1279 
1280     mc->desc       = "Supermicro X11 BMC (ARM926EJ-S)";
1281     amc->soc_name  = "ast2400-a1";
1282     amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1283     amc->fmc_model = "mx25l25635e";
1284     amc->spi_model = "mx25l25635e";
1285     amc->num_cs    = 1;
1286     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1287     amc->i2c_init  = palmetto_bmc_i2c_init;
1288     mc->default_ram_size = 256 * MiB;
1289     aspeed_machine_class_init_cpus_defaults(mc);
1290 }
1291 
1292 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1293                                                             void *data)
1294 {
1295     MachineClass *mc = MACHINE_CLASS(oc);
1296     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1297 
1298     mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
1299     amc->soc_name  = "ast2500-a1";
1300     amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1301     amc->fmc_model = "mx25l25635e";
1302     amc->spi_model = "mx25l25635e";
1303     amc->num_cs    = 1;
1304     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1305     amc->i2c_init  = palmetto_bmc_i2c_init;
1306     mc->default_ram_size = 512 * MiB;
1307     aspeed_machine_class_init_cpus_defaults(mc);
1308 }
1309 
1310 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1311 {
1312     MachineClass *mc = MACHINE_CLASS(oc);
1313     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1314 
1315     mc->desc       = "Aspeed AST2500 EVB (ARM1176)";
1316     amc->soc_name  = "ast2500-a1";
1317     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1318     amc->fmc_model = "mx25l25635e";
1319     amc->spi_model = "mx25l25635f";
1320     amc->num_cs    = 1;
1321     amc->i2c_init  = ast2500_evb_i2c_init;
1322     mc->default_ram_size       = 512 * MiB;
1323     aspeed_machine_class_init_cpus_defaults(mc);
1324 };
1325 
1326 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1327 {
1328     MachineClass *mc = MACHINE_CLASS(oc);
1329     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1330 
1331     mc->desc       = "Facebook YosemiteV2 BMC (ARM1176)";
1332     amc->soc_name  = "ast2500-a1";
1333     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1334     amc->hw_strap2 = 0;
1335     amc->fmc_model = "n25q256a";
1336     amc->spi_model = "mx25l25635e";
1337     amc->num_cs    = 2;
1338     amc->i2c_init  = yosemitev2_bmc_i2c_init;
1339     mc->default_ram_size       = 512 * MiB;
1340     aspeed_machine_class_init_cpus_defaults(mc);
1341 };
1342 
1343 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1344 {
1345     MachineClass *mc = MACHINE_CLASS(oc);
1346     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1347 
1348     mc->desc       = "OpenPOWER Romulus BMC (ARM1176)";
1349     amc->soc_name  = "ast2500-a1";
1350     amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1351     amc->fmc_model = "n25q256a";
1352     amc->spi_model = "mx66l1g45g";
1353     amc->num_cs    = 2;
1354     amc->i2c_init  = romulus_bmc_i2c_init;
1355     mc->default_ram_size       = 512 * MiB;
1356     aspeed_machine_class_init_cpus_defaults(mc);
1357 };
1358 
1359 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1360 {
1361     MachineClass *mc = MACHINE_CLASS(oc);
1362     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1363 
1364     mc->desc       = "Facebook Tiogapass BMC (ARM1176)";
1365     amc->soc_name  = "ast2500-a1";
1366     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1367     amc->hw_strap2 = 0;
1368     amc->fmc_model = "n25q256a";
1369     amc->spi_model = "mx25l25635e";
1370     amc->num_cs    = 2;
1371     amc->i2c_init  = tiogapass_bmc_i2c_init;
1372     mc->default_ram_size       = 1 * GiB;
1373     aspeed_machine_class_init_cpus_defaults(mc);
1374 };
1375 
1376 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1377 {
1378     MachineClass *mc = MACHINE_CLASS(oc);
1379     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1380 
1381     mc->desc       = "OCP SonoraPass BMC (ARM1176)";
1382     amc->soc_name  = "ast2500-a1";
1383     amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1384     amc->fmc_model = "mx66l1g45g";
1385     amc->spi_model = "mx66l1g45g";
1386     amc->num_cs    = 2;
1387     amc->i2c_init  = sonorapass_bmc_i2c_init;
1388     mc->default_ram_size       = 512 * MiB;
1389     aspeed_machine_class_init_cpus_defaults(mc);
1390 };
1391 
1392 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1393 {
1394     MachineClass *mc = MACHINE_CLASS(oc);
1395     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1396 
1397     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
1398     amc->soc_name  = "ast2500-a1";
1399     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1400     amc->fmc_model = "mx25l25635f";
1401     amc->spi_model = "mx66l1g45g";
1402     amc->num_cs    = 2;
1403     amc->i2c_init  = witherspoon_bmc_i2c_init;
1404     mc->default_ram_size = 512 * MiB;
1405     aspeed_machine_class_init_cpus_defaults(mc);
1406 };
1407 
1408 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1409 {
1410     MachineClass *mc = MACHINE_CLASS(oc);
1411     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1412 
1413     mc->desc       = "Aspeed AST2600 EVB (Cortex-A7)";
1414     amc->soc_name  = "ast2600-a3";
1415     amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1416     amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1417     amc->fmc_model = "mx66u51235f";
1418     amc->spi_model = "mx66u51235f";
1419     amc->num_cs    = 1;
1420     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1421                      ASPEED_MAC3_ON;
1422     amc->i2c_init  = ast2600_evb_i2c_init;
1423     mc->default_ram_size = 1 * GiB;
1424     aspeed_machine_class_init_cpus_defaults(mc);
1425     aspeed_machine_ast2600_class_emmc_init(oc);
1426 };
1427 
1428 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1429 {
1430     MachineClass *mc = MACHINE_CLASS(oc);
1431     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1432 
1433     mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
1434     amc->soc_name  = "ast2600-a3";
1435     amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1436     amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1437     amc->fmc_model = "mx66l1g45g";
1438     amc->spi_model = "mx66l1g45g";
1439     amc->num_cs    = 2;
1440     amc->macs_mask  = ASPEED_MAC2_ON;
1441     amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
1442     mc->default_ram_size = 1 * GiB;
1443     aspeed_machine_class_init_cpus_defaults(mc);
1444 
1445     mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine";
1446 };
1447 
1448 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1449 {
1450     MachineClass *mc = MACHINE_CLASS(oc);
1451     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1452 
1453     mc->desc       = "Bytedance G220A BMC (ARM1176)";
1454     amc->soc_name  = "ast2500-a1";
1455     amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1456     amc->fmc_model = "n25q512a";
1457     amc->spi_model = "mx25l25635e";
1458     amc->num_cs    = 2;
1459     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1460     amc->i2c_init  = g220a_bmc_i2c_init;
1461     mc->default_ram_size = 1024 * MiB;
1462     aspeed_machine_class_init_cpus_defaults(mc);
1463 };
1464 
1465 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1466 {
1467     MachineClass *mc = MACHINE_CLASS(oc);
1468     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1469 
1470     mc->desc       = "Inspur FP5280G2 BMC (ARM1176)";
1471     amc->soc_name  = "ast2500-a1";
1472     amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1473     amc->fmc_model = "n25q512a";
1474     amc->spi_model = "mx25l25635e";
1475     amc->num_cs    = 2;
1476     amc->macs_mask  = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1477     amc->i2c_init  = fp5280g2_bmc_i2c_init;
1478     mc->default_ram_size = 512 * MiB;
1479     aspeed_machine_class_init_cpus_defaults(mc);
1480 };
1481 
1482 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1483 {
1484     MachineClass *mc = MACHINE_CLASS(oc);
1485     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1486 
1487     mc->desc       = "IBM Rainier BMC (Cortex-A7)";
1488     amc->soc_name  = "ast2600-a3";
1489     amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1490     amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1491     amc->fmc_model = "mx66l1g45g";
1492     amc->spi_model = "mx66l1g45g";
1493     amc->num_cs    = 2;
1494     amc->macs_mask  = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1495     amc->i2c_init  = rainier_bmc_i2c_init;
1496     mc->default_ram_size = 1 * GiB;
1497     aspeed_machine_class_init_cpus_defaults(mc);
1498     aspeed_machine_ast2600_class_emmc_init(oc);
1499 };
1500 
1501 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1502 
1503 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1504 {
1505     MachineClass *mc = MACHINE_CLASS(oc);
1506     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1507 
1508     mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1509     amc->soc_name = "ast2600-a3";
1510     amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1511     amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1512     amc->fmc_model = "mx66l1g45g";
1513     amc->spi_model = "mx66l1g45g";
1514     amc->num_cs = 2;
1515     amc->macs_mask = ASPEED_MAC3_ON;
1516     amc->i2c_init = fuji_bmc_i2c_init;
1517     amc->uart_default = ASPEED_DEV_UART1;
1518     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1519     aspeed_machine_class_init_cpus_defaults(mc);
1520 };
1521 
1522 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1523 
1524 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1525 {
1526     MachineClass *mc = MACHINE_CLASS(oc);
1527     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1528 
1529     mc->desc       = "Facebook Bletchley BMC (Cortex-A7)";
1530     amc->soc_name  = "ast2600-a3";
1531     amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1532     amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1533     amc->fmc_model = "w25q01jvq";
1534     amc->spi_model = NULL;
1535     amc->num_cs    = 2;
1536     amc->macs_mask = ASPEED_MAC2_ON;
1537     amc->i2c_init  = bletchley_bmc_i2c_init;
1538     mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1539     aspeed_machine_class_init_cpus_defaults(mc);
1540 }
1541 
1542 static void fby35_reset(MachineState *state, ResetType type)
1543 {
1544     AspeedMachineState *bmc = ASPEED_MACHINE(state);
1545     AspeedGPIOState *gpio = &bmc->soc->gpio;
1546 
1547     qemu_devices_reset(type);
1548 
1549     /* Board ID: 7 (Class-1, 4 slots) */
1550     object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1551     object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1552     object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1553     object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1554 
1555     /* Slot presence pins, inverse polarity. (False means present) */
1556     object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1557     object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1558     object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1559     object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1560 
1561     /* Slot 12v power pins, normal polarity. (True means powered-on) */
1562     object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1563     object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1564     object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1565     object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1566 }
1567 
1568 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1569 {
1570     MachineClass *mc = MACHINE_CLASS(oc);
1571     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1572 
1573     mc->desc       = "Facebook fby35 BMC (Cortex-A7)";
1574     mc->reset      = fby35_reset;
1575     amc->fmc_model = "mx66l1g45g";
1576     amc->num_cs    = 2;
1577     amc->macs_mask = ASPEED_MAC3_ON;
1578     amc->i2c_init  = fby35_i2c_init;
1579     /* FIXME: Replace this macro with something more general */
1580     mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1581     aspeed_machine_class_init_cpus_defaults(mc);
1582 }
1583 
1584 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1585 /* Main SYSCLK frequency in Hz (200MHz) */
1586 #define SYSCLK_FRQ 200000000ULL
1587 
1588 static void aspeed_minibmc_machine_init(MachineState *machine)
1589 {
1590     AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1591     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1592     Clock *sysclk;
1593 
1594     sysclk = clock_new(OBJECT(machine), "SYSCLK");
1595     clock_set_hz(sysclk, SYSCLK_FRQ);
1596 
1597     bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1598     object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1599     object_unref(OBJECT(bmc->soc));
1600     qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1601 
1602     object_property_set_link(OBJECT(bmc->soc), "memory",
1603                              OBJECT(get_system_memory()), &error_abort);
1604     connect_serial_hds_to_uarts(bmc);
1605     qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1606 
1607     if (defaults_enabled()) {
1608         aspeed_board_init_flashes(&bmc->soc->fmc,
1609                             bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1610                             amc->num_cs,
1611                             0);
1612 
1613         aspeed_board_init_flashes(&bmc->soc->spi[0],
1614                             bmc->spi_model ? bmc->spi_model : amc->spi_model,
1615                             amc->num_cs, amc->num_cs);
1616 
1617         aspeed_board_init_flashes(&bmc->soc->spi[1],
1618                             bmc->spi_model ? bmc->spi_model : amc->spi_model,
1619                             amc->num_cs, (amc->num_cs * 2));
1620     }
1621 
1622     if (amc->i2c_init) {
1623         amc->i2c_init(bmc);
1624     }
1625 
1626     armv7m_load_kernel(ARM_CPU(first_cpu),
1627                        machine->kernel_filename,
1628                        0,
1629                        AST1030_INTERNAL_FLASH_SIZE);
1630 }
1631 
1632 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1633 {
1634     AspeedSoCState *soc = bmc->soc;
1635 
1636     /* U10 24C08 connects to SDA/SCL Group 1 by default */
1637     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1638     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1639 
1640     /* U11 LM75 connects to SDA/SCL Group 2 by default */
1641     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1642 }
1643 
1644 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1645                                                           void *data)
1646 {
1647     MachineClass *mc = MACHINE_CLASS(oc);
1648     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1649 
1650     mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1651     amc->soc_name = "ast1030-a1";
1652     amc->hw_strap1 = 0;
1653     amc->hw_strap2 = 0;
1654     mc->init = aspeed_minibmc_machine_init;
1655     amc->i2c_init = ast1030_evb_i2c_init;
1656     mc->default_ram_size = 0;
1657     amc->fmc_model = "w25q80bl";
1658     amc->spi_model = "w25q256";
1659     amc->num_cs = 2;
1660     amc->macs_mask = 0;
1661     aspeed_machine_class_init_cpus_defaults(mc);
1662 }
1663 
1664 #ifdef TARGET_AARCH64
1665 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
1666 {
1667     AspeedSoCState *soc = bmc->soc;
1668 
1669     /* LM75 is compatible with TMP105 driver */
1670     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
1671                             TYPE_TMP105, 0x4d);
1672 }
1673 
1674 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
1675 {
1676     MachineClass *mc = MACHINE_CLASS(oc);
1677     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1678 
1679     mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
1680     amc->soc_name  = "ast2700-a0";
1681     amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1682     amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1683     amc->fmc_model = "w25q01jvq";
1684     amc->spi_model = "w25q512jv";
1685     amc->num_cs    = 2;
1686     amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1687     amc->uart_default = ASPEED_DEV_UART12;
1688     amc->i2c_init  = ast2700_evb_i2c_init;
1689     mc->default_ram_size = 1 * GiB;
1690     aspeed_machine_class_init_cpus_defaults(mc);
1691 }
1692 #endif
1693 
1694 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1695                                                      void *data)
1696 {
1697     MachineClass *mc = MACHINE_CLASS(oc);
1698     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1699 
1700     mc->desc       = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1701     amc->soc_name  = "ast2600-a3";
1702     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1703     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1704     amc->fmc_model = "n25q512a";
1705     amc->spi_model = "n25q512a";
1706     amc->num_cs    = 2;
1707     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1708     amc->i2c_init  = qcom_dc_scm_bmc_i2c_init;
1709     mc->default_ram_size = 1 * GiB;
1710     aspeed_machine_class_init_cpus_defaults(mc);
1711 };
1712 
1713 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1714                                                     void *data)
1715 {
1716     MachineClass *mc = MACHINE_CLASS(oc);
1717     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1718 
1719     mc->desc       = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1720     amc->soc_name  = "ast2600-a3";
1721     amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1722     amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1723     amc->fmc_model = "n25q512a";
1724     amc->spi_model = "n25q512a";
1725     amc->num_cs    = 2;
1726     amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1727     amc->i2c_init  = qcom_dc_scm_firework_i2c_init;
1728     mc->default_ram_size = 1 * GiB;
1729     aspeed_machine_class_init_cpus_defaults(mc);
1730 };
1731 
1732 static const TypeInfo aspeed_machine_types[] = {
1733     {
1734         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
1735         .parent        = TYPE_ASPEED_MACHINE,
1736         .class_init    = aspeed_machine_palmetto_class_init,
1737     }, {
1738         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1739         .parent        = TYPE_ASPEED_MACHINE,
1740         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
1741     }, {
1742         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1743         .parent        = TYPE_ASPEED_MACHINE,
1744         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
1745     }, {
1746         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
1747         .parent        = TYPE_ASPEED_MACHINE,
1748         .class_init    = aspeed_machine_ast2500_evb_class_init,
1749     }, {
1750         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
1751         .parent        = TYPE_ASPEED_MACHINE,
1752         .class_init    = aspeed_machine_romulus_class_init,
1753     }, {
1754         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
1755         .parent        = TYPE_ASPEED_MACHINE,
1756         .class_init    = aspeed_machine_sonorapass_class_init,
1757     }, {
1758         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
1759         .parent        = TYPE_ASPEED_MACHINE,
1760         .class_init    = aspeed_machine_witherspoon_class_init,
1761     }, {
1762         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
1763         .parent        = TYPE_ASPEED_MACHINE,
1764         .class_init    = aspeed_machine_ast2600_evb_class_init,
1765     }, {
1766         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1767         .parent        = TYPE_ASPEED_MACHINE,
1768         .class_init    = aspeed_machine_yosemitev2_class_init,
1769     }, {
1770         .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
1771         .parent        = TYPE_ASPEED_MACHINE,
1772         .class_init    = aspeed_machine_tacoma_class_init,
1773     }, {
1774         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
1775         .parent        = TYPE_ASPEED_MACHINE,
1776         .class_init    = aspeed_machine_tiogapass_class_init,
1777     }, {
1778         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
1779         .parent        = TYPE_ASPEED_MACHINE,
1780         .class_init    = aspeed_machine_g220a_class_init,
1781     }, {
1782         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1783         .parent        = TYPE_ASPEED_MACHINE,
1784         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
1785     }, {
1786         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1787         .parent        = TYPE_ASPEED_MACHINE,
1788         .class_init    = aspeed_machine_qcom_firework_class_init,
1789     }, {
1790         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1791         .parent        = TYPE_ASPEED_MACHINE,
1792         .class_init    = aspeed_machine_fp5280g2_class_init,
1793     }, {
1794         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1795         .parent        = TYPE_ASPEED_MACHINE,
1796         .class_init    = aspeed_machine_quanta_q71l_class_init,
1797     }, {
1798         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
1799         .parent        = TYPE_ASPEED_MACHINE,
1800         .class_init    = aspeed_machine_rainier_class_init,
1801     }, {
1802         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
1803         .parent        = TYPE_ASPEED_MACHINE,
1804         .class_init    = aspeed_machine_fuji_class_init,
1805     }, {
1806         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
1807         .parent        = TYPE_ASPEED_MACHINE,
1808         .class_init    = aspeed_machine_bletchley_class_init,
1809     }, {
1810         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
1811         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
1812         .class_init    = aspeed_machine_fby35_class_init,
1813     }, {
1814         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
1815         .parent         = TYPE_ASPEED_MACHINE,
1816         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
1817 #ifdef TARGET_AARCH64
1818     }, {
1819         .name          = MACHINE_TYPE_NAME("ast2700-evb"),
1820         .parent        = TYPE_ASPEED_MACHINE,
1821         .class_init    = aspeed_machine_ast2700_evb_class_init,
1822 #endif
1823     }, {
1824         .name          = TYPE_ASPEED_MACHINE,
1825         .parent        = TYPE_MACHINE,
1826         .instance_size = sizeof(AspeedMachineState),
1827         .instance_init = aspeed_machine_instance_init,
1828         .class_size    = sizeof(AspeedMachineClass),
1829         .class_init    = aspeed_machine_class_init,
1830         .abstract      = true,
1831     }
1832 };
1833 
1834 DEFINE_TYPES(aspeed_machine_types)
1835