1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 #define AST2700_EVB_HW_STRAP1 0x000000C0 185 #define AST2700_EVB_HW_STRAP2 0x00000003 186 #endif 187 188 /* Rainier hardware value: (QEMU prototype) */ 189 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 190 #define RAINIER_BMC_HW_STRAP2 0x80000848 191 192 /* Fuji hardware value */ 193 #define FUJI_BMC_HW_STRAP1 0x00000000 194 #define FUJI_BMC_HW_STRAP2 0x00000000 195 196 /* Bletchley hardware value */ 197 /* TODO: Leave same as EVB for now. */ 198 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 199 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 200 201 /* Qualcomm DC-SCM hardware value */ 202 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 203 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 204 205 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 206 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 207 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 208 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 209 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 210 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 211 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 212 213 static void aspeed_write_smpboot(ARMCPU *cpu, 214 const struct arm_boot_info *info) 215 { 216 AddressSpace *as = arm_boot_address_space(cpu, info); 217 static const ARMInsnFixup poll_mailbox_ready[] = { 218 /* 219 * r2 = per-cpu go sign value 220 * r1 = AST_SMP_MBOX_FIELD_ENTRY 221 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 222 */ 223 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 224 { 0xe21000ff }, /* ands r0, r0, #255 */ 225 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 226 { 0xe1822000 }, /* orr r2, r2, r0 */ 227 228 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 229 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 230 231 { 0xe320f002 }, /* wfe */ 232 { 0xe5904000 }, /* ldr r4, [r0] */ 233 { 0xe1520004 }, /* cmp r2, r4 */ 234 { 0x1afffffb }, /* bne <wfe> */ 235 { 0xe591f000 }, /* ldr pc, [r1] */ 236 { AST_SMP_MBOX_GOSIGN }, 237 { AST_SMP_MBOX_FIELD_ENTRY }, 238 { AST_SMP_MBOX_FIELD_GOSIGN }, 239 { 0, FIXUP_TERMINATOR } 240 }; 241 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 242 243 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 244 poll_mailbox_ready, fixupcontext); 245 } 246 247 static void aspeed_reset_secondary(ARMCPU *cpu, 248 const struct arm_boot_info *info) 249 { 250 AddressSpace *as = arm_boot_address_space(cpu, info); 251 CPUState *cs = CPU(cpu); 252 253 /* info->smp_bootreg_addr */ 254 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 255 MEMTXATTRS_UNSPECIFIED, NULL); 256 cpu_set_pc(cs, info->smp_loader_start); 257 } 258 259 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 260 Error **errp) 261 { 262 g_autofree void *storage = NULL; 263 int64_t size; 264 265 /* 266 * The block backend size should have already been 'validated' by 267 * the creation of the m25p80 object. 268 */ 269 size = blk_getlength(blk); 270 if (size <= 0) { 271 error_setg(errp, "failed to get flash size"); 272 return; 273 } 274 275 if (rom_size > size) { 276 rom_size = size; 277 } 278 279 storage = g_malloc0(rom_size); 280 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 281 error_setg(errp, "failed to read the initial flash content"); 282 return; 283 } 284 285 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 286 } 287 288 /* 289 * Create a ROM and copy the flash contents at the expected address 290 * (0x0). Boots faster than execute-in-place. 291 */ 292 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 293 uint64_t rom_size) 294 { 295 AspeedSoCState *soc = bmc->soc; 296 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 297 298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 299 &error_abort); 300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 301 &bmc->boot_rom, 1); 302 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 303 rom_size, &error_abort); 304 } 305 306 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 307 unsigned int count, int unit0) 308 { 309 int i; 310 311 if (!flashtype) { 312 return; 313 } 314 315 for (i = 0; i < count; ++i) { 316 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 317 DeviceState *dev; 318 319 dev = qdev_new(flashtype); 320 if (dinfo) { 321 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 322 } 323 qdev_prop_set_uint8(dev, "cs", i); 324 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 325 } 326 } 327 328 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 329 bool boot_emmc) 330 { 331 DeviceState *card; 332 333 if (!dinfo) { 334 return; 335 } 336 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 337 338 /* 339 * Force the boot properties of the eMMC device only when the 340 * machine is strapped to boot from eMMC. Without these 341 * settings, the machine would not boot. 342 * 343 * This also allows the machine to use an eMMC device without 344 * boot areas when booting from the flash device (or -kernel) 345 * Ideally, the device and its properties should be defined on 346 * the command line. 347 */ 348 if (emmc && boot_emmc) { 349 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 350 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 351 } 352 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 353 &error_fatal); 354 qdev_realize_and_unref(card, 355 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 356 &error_fatal); 357 } 358 359 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 360 { 361 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 362 AspeedSoCState *s = bmc->soc; 363 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 364 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 365 366 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 367 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 368 if (uart == uart_chosen) { 369 continue; 370 } 371 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 372 } 373 } 374 375 static void aspeed_machine_init(MachineState *machine) 376 { 377 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 378 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 379 AspeedSoCClass *sc; 380 int i; 381 DriveInfo *emmc0 = NULL; 382 bool boot_emmc; 383 384 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 385 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 386 object_unref(OBJECT(bmc->soc)); 387 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 388 389 /* 390 * This will error out if the RAM size is not supported by the 391 * memory controller of the SoC. 392 */ 393 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 394 &error_fatal); 395 396 for (i = 0; i < sc->macs_num; i++) { 397 if ((amc->macs_mask & (1 << i)) && 398 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 399 true, NULL)) { 400 break; /* No configs left; stop asking */ 401 } 402 } 403 404 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 405 &error_abort); 406 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 407 &error_abort); 408 object_property_set_link(OBJECT(bmc->soc), "memory", 409 OBJECT(get_system_memory()), &error_abort); 410 object_property_set_link(OBJECT(bmc->soc), "dram", 411 OBJECT(machine->ram), &error_abort); 412 if (amc->sdhci_wp_inverted) { 413 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 414 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 415 "wp-inverted", true, &error_abort); 416 } 417 } 418 if (machine->kernel_filename) { 419 /* 420 * When booting with a -kernel command line there is no u-boot 421 * that runs to unlock the SCU. In this case set the default to 422 * be unlocked as the kernel expects 423 */ 424 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 425 ASPEED_SCU_PROT_KEY, &error_abort); 426 } 427 connect_serial_hds_to_uarts(bmc); 428 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 429 430 if (defaults_enabled()) { 431 aspeed_board_init_flashes(&bmc->soc->fmc, 432 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 433 amc->num_cs, 0); 434 aspeed_board_init_flashes(&bmc->soc->spi[0], 435 bmc->spi_model ? bmc->spi_model : amc->spi_model, 436 1, amc->num_cs); 437 } 438 439 if (machine->kernel_filename && sc->num_cpus > 1) { 440 /* With no u-boot we must set up a boot stub for the secondary CPU */ 441 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 442 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 443 0x80, &error_abort); 444 memory_region_add_subregion(get_system_memory(), 445 AST_SMP_MAILBOX_BASE, smpboot); 446 447 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 448 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 449 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 450 } 451 452 aspeed_board_binfo.ram_size = machine->ram_size; 453 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 454 455 if (amc->i2c_init) { 456 amc->i2c_init(bmc); 457 } 458 459 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 460 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 461 drive_get(IF_SD, 0, i), false, false); 462 } 463 464 boot_emmc = sc->boot_from_emmc(bmc->soc); 465 466 if (bmc->soc->emmc.num_slots) { 467 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 468 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 469 } 470 471 if (!bmc->mmio_exec) { 472 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 473 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 474 475 if (fmc0 && !boot_emmc) { 476 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 477 aspeed_install_boot_rom(bmc, fmc0, rom_size); 478 } else if (emmc0) { 479 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 480 } 481 } 482 483 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 484 } 485 486 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 487 { 488 AspeedSoCState *soc = bmc->soc; 489 DeviceState *dev; 490 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 491 492 /* 493 * The palmetto platform expects a ds3231 RTC but a ds1338 is 494 * enough to provide basic RTC features. Alarms will be missing 495 */ 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 497 498 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 499 eeprom_buf); 500 501 /* add a TMP423 temperature sensor */ 502 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 503 "tmp423", 0x4c)); 504 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 505 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 506 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 507 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 508 } 509 510 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 511 { 512 AspeedSoCState *soc = bmc->soc; 513 514 /* 515 * The quanta-q71l platform expects tmp75s which are compatible with 516 * tmp105s. 517 */ 518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 521 522 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 523 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 524 /* TODO: Add Memory Riser i2c mux and eeproms. */ 525 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 528 529 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 530 531 /* i2c-7 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 533 /* - i2c@0: pmbus@59 */ 534 /* - i2c@1: pmbus@58 */ 535 /* - i2c@2: pmbus@58 */ 536 /* - i2c@3: pmbus@59 */ 537 538 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 539 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 540 } 541 542 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 543 { 544 AspeedSoCState *soc = bmc->soc; 545 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 546 547 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 548 eeprom_buf); 549 550 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 552 TYPE_TMP105, 0x4d); 553 } 554 555 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 556 { 557 AspeedSoCState *soc = bmc->soc; 558 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 559 560 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 561 eeprom_buf); 562 563 /* LM75 is compatible with TMP105 driver */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 565 TYPE_TMP105, 0x4d); 566 } 567 568 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 569 { 570 AspeedSoCState *soc = bmc->soc; 571 572 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 573 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 574 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 575 /* TMP421 */ 576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 579 580 } 581 582 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 583 { 584 AspeedSoCState *soc = bmc->soc; 585 586 /* 587 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 588 * good enough 589 */ 590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 591 } 592 593 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 594 { 595 AspeedSoCState *soc = bmc->soc; 596 597 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 598 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 599 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 600 /* TMP421 */ 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 603 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 604 } 605 606 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 607 { 608 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 609 TYPE_PCA9552, addr); 610 } 611 612 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 613 { 614 AspeedSoCState *soc = bmc->soc; 615 616 /* bus 2 : */ 617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 619 /* bus 2 : pca9546 @ 0x73 */ 620 621 /* bus 3 : pca9548 @ 0x70 */ 622 623 /* bus 4 : */ 624 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 626 eeprom4_54); 627 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 628 create_pca9552(soc, 4, 0x76); 629 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 630 create_pca9552(soc, 4, 0x77); 631 632 /* bus 6 : */ 633 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 635 /* bus 6 : pca9546 @ 0x73 */ 636 637 /* bus 8 : */ 638 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 639 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 640 eeprom8_56); 641 create_pca9552(soc, 8, 0x60); 642 create_pca9552(soc, 8, 0x61); 643 /* bus 8 : adc128d818 @ 0x1d */ 644 /* bus 8 : adc128d818 @ 0x1f */ 645 646 /* 647 * bus 13 : pca9548 @ 0x71 648 * - channel 3: 649 * - tmm421 @ 0x4c 650 * - tmp421 @ 0x4e 651 * - tmp421 @ 0x4f 652 */ 653 654 } 655 656 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 657 { 658 static const struct { 659 unsigned gpio_id; 660 LEDColor color; 661 const char *description; 662 bool gpio_polarity; 663 } pca1_leds[] = { 664 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 665 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 666 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 667 }; 668 AspeedSoCState *soc = bmc->soc; 669 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 670 DeviceState *dev; 671 LEDState *led; 672 673 /* Bus 3: TODO bmp280@77 */ 674 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 675 qdev_prop_set_string(dev, "description", "pca1"); 676 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 677 aspeed_i2c_get_bus(&soc->i2c, 3), 678 &error_fatal); 679 680 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 681 led = led_create_simple(OBJECT(bmc), 682 pca1_leds[i].gpio_polarity, 683 pca1_leds[i].color, 684 pca1_leds[i].description); 685 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 686 qdev_get_gpio_in(DEVICE(led), 0)); 687 } 688 689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 690 0x68); 691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 692 0x69); 693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 694 695 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 697 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x70); 698 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ir35221", 0x71); 699 700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 701 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x70); 702 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "ir35221", 0x71); 703 704 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 705 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 706 0x4a); 707 708 /* 709 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 710 * good enough 711 */ 712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 713 714 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 715 eeprom_buf); 716 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 717 qdev_prop_set_string(dev, "description", "pca0"); 718 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 719 aspeed_i2c_get_bus(&soc->i2c, 11), 720 &error_fatal); 721 /* Bus 11: TODO ucd90160@64 */ 722 } 723 724 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 725 { 726 AspeedSoCState *soc = bmc->soc; 727 DeviceState *dev; 728 729 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 730 "emc1413", 0x4c)); 731 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 732 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 733 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 734 735 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 736 "emc1413", 0x4c)); 737 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 738 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 739 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 740 741 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 742 "emc1413", 0x4c)); 743 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 744 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 745 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 746 747 static uint8_t eeprom_buf[2 * 1024] = { 748 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 749 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 750 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 751 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 752 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 753 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 754 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 755 }; 756 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 757 eeprom_buf); 758 } 759 760 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 761 { 762 AspeedSoCState *soc = bmc->soc; 763 I2CSlave *i2c_mux; 764 765 /* The at24c256 */ 766 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 767 768 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 769 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 770 0x48); 771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 772 0x49); 773 774 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 775 "pca9546", 0x70); 776 /* It expects a TMP112 but a TMP105 is compatible */ 777 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 778 0x4a); 779 780 /* It expects a ds3232 but a ds1338 is good enough */ 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 782 783 /* It expects a pca9555 but a pca9552 is compatible */ 784 create_pca9552(soc, 8, 0x30); 785 } 786 787 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 788 { 789 AspeedSoCState *soc = bmc->soc; 790 I2CSlave *i2c_mux; 791 792 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 793 794 create_pca9552(soc, 3, 0x61); 795 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 797 0x68); 798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 799 0x69); 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 801 0x6a); 802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 803 0x6b); 804 805 /* The rainier expects a TMP275 but a TMP105 is compatible */ 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 807 0x48); 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 809 0x49); 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 811 0x4a); 812 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 813 "pca9546", 0x70); 814 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 815 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 816 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 817 create_pca9552(soc, 4, 0x60); 818 819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 820 0x48); 821 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 822 0x49); 823 create_pca9552(soc, 5, 0x60); 824 create_pca9552(soc, 5, 0x61); 825 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 826 "pca9546", 0x70); 827 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 828 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 829 830 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 831 0x48); 832 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 833 0x4a); 834 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 835 0x4b); 836 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 837 "pca9546", 0x70); 838 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 839 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 840 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 841 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 842 843 create_pca9552(soc, 7, 0x30); 844 create_pca9552(soc, 7, 0x31); 845 create_pca9552(soc, 7, 0x32); 846 create_pca9552(soc, 7, 0x33); 847 create_pca9552(soc, 7, 0x60); 848 create_pca9552(soc, 7, 0x61); 849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 850 /* Bus 7: TODO si7021-a20@20 */ 851 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 852 0x48); 853 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 854 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 855 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 856 857 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 858 0x48); 859 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 860 0x4a); 861 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 862 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 863 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 864 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 865 create_pca9552(soc, 8, 0x60); 866 create_pca9552(soc, 8, 0x61); 867 /* Bus 8: ucd90320@11 */ 868 /* Bus 8: ucd90320@b */ 869 /* Bus 8: ucd90320@c */ 870 871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x42); 872 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x43); 873 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x44); 874 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x72); 875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x73); 876 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "ir35221", 0x74); 877 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 878 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 879 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 880 881 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x42); 882 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x43); 883 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x44); 884 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x72); 885 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x73); 886 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "ir35221", 0x74); 887 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 888 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 889 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 890 891 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 892 0x48); 893 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 894 0x49); 895 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 896 "pca9546", 0x70); 897 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 898 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 899 create_pca9552(soc, 11, 0x60); 900 901 902 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 903 create_pca9552(soc, 13, 0x60); 904 905 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 906 create_pca9552(soc, 14, 0x60); 907 908 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 909 create_pca9552(soc, 15, 0x60); 910 } 911 912 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 913 I2CBus **channels) 914 { 915 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 916 for (int i = 0; i < 8; i++) { 917 channels[i] = pca954x_i2c_get_bus(mux, i); 918 } 919 } 920 921 #define TYPE_LM75 TYPE_TMP105 922 #define TYPE_TMP75 TYPE_TMP105 923 #define TYPE_TMP422 "tmp422" 924 925 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 926 { 927 AspeedSoCState *soc = bmc->soc; 928 I2CBus *i2c[144] = {}; 929 930 for (int i = 0; i < 16; i++) { 931 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 932 } 933 I2CBus *i2c180 = i2c[2]; 934 I2CBus *i2c480 = i2c[8]; 935 I2CBus *i2c600 = i2c[11]; 936 937 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 938 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 939 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 940 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 941 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 942 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 943 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 944 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 945 for (int i = 0; i < 8; i++) { 946 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 947 } 948 949 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 950 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 951 952 /* 953 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 954 * 24c02 size is 2Kbits or 256 bytes 955 */ 956 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 957 at24c_eeprom_init(i2c[20], 0x50, 256); 958 at24c_eeprom_init(i2c[22], 0x52, 256); 959 960 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 961 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 962 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 963 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 964 965 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 966 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 967 968 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 969 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 970 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 971 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 972 973 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 974 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 975 976 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 977 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 978 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 979 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 980 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 981 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 982 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 983 984 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 985 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 986 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 987 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 988 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 989 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 990 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 991 at24c_eeprom_init(i2c[28], 0x50, 256); 992 993 for (int i = 0; i < 8; i++) { 994 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 995 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 996 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 997 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 998 } 999 } 1000 1001 #define TYPE_TMP421 "tmp421" 1002 1003 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1004 { 1005 AspeedSoCState *soc = bmc->soc; 1006 I2CBus *i2c[13] = {}; 1007 for (int i = 0; i < 13; i++) { 1008 if ((i == 8) || (i == 11)) { 1009 continue; 1010 } 1011 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1012 } 1013 1014 /* Bus 0 - 5 all have the same config. */ 1015 for (int i = 0; i < 6; i++) { 1016 /* Missing model: ti,ina230 @ 0x45 */ 1017 /* Missing model: mps,mp5023 @ 0x40 */ 1018 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1019 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1020 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1021 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1022 /* Missing model: fsc,fusb302 @ 0x22 */ 1023 } 1024 1025 /* Bus 6 */ 1026 at24c_eeprom_init(i2c[6], 0x56, 65536); 1027 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1028 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1029 1030 1031 /* Bus 7 */ 1032 at24c_eeprom_init(i2c[7], 0x54, 65536); 1033 1034 /* Bus 9 */ 1035 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1036 1037 /* Bus 10 */ 1038 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1039 /* Missing model: ti,hdc1080 @ 0x40 */ 1040 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1041 1042 /* Bus 12 */ 1043 /* Missing model: adi,adm1278 @ 0x11 */ 1044 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1045 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1046 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1047 } 1048 1049 static void fby35_i2c_init(AspeedMachineState *bmc) 1050 { 1051 AspeedSoCState *soc = bmc->soc; 1052 I2CBus *i2c[16]; 1053 1054 for (int i = 0; i < 16; i++) { 1055 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1056 } 1057 1058 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1059 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1060 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1061 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1062 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1063 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1064 1065 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1066 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1067 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1068 fby35_nic_fruid_len); 1069 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1070 fby35_bb_fruid_len); 1071 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1072 fby35_bmc_fruid_len); 1073 1074 /* 1075 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1076 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1077 * each. 1078 */ 1079 } 1080 1081 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1082 { 1083 AspeedSoCState *soc = bmc->soc; 1084 1085 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1086 } 1087 1088 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1089 { 1090 AspeedSoCState *soc = bmc->soc; 1091 I2CSlave *therm_mux, *cpuvr_mux; 1092 1093 /* Create the generic DC-SCM hardware */ 1094 qcom_dc_scm_bmc_i2c_init(bmc); 1095 1096 /* Now create the Firework specific hardware */ 1097 1098 /* I2C7 CPUVR MUX */ 1099 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1100 "pca9546", 0x70); 1101 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1102 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1103 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1104 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1105 1106 /* I2C8 Thermal Diodes*/ 1107 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1108 "pca9548", 0x70); 1109 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1110 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1111 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1112 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1113 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1114 1115 /* I2C9 Fan Controller (MAX31785) */ 1116 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1117 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1118 } 1119 1120 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1121 { 1122 return ASPEED_MACHINE(obj)->mmio_exec; 1123 } 1124 1125 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1126 { 1127 ASPEED_MACHINE(obj)->mmio_exec = value; 1128 } 1129 1130 static void aspeed_machine_instance_init(Object *obj) 1131 { 1132 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1133 1134 ASPEED_MACHINE(obj)->mmio_exec = false; 1135 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1136 } 1137 1138 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1139 { 1140 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1141 return g_strdup(bmc->fmc_model); 1142 } 1143 1144 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1145 { 1146 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1147 1148 g_free(bmc->fmc_model); 1149 bmc->fmc_model = g_strdup(value); 1150 } 1151 1152 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1153 { 1154 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1155 return g_strdup(bmc->spi_model); 1156 } 1157 1158 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1159 { 1160 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1161 1162 g_free(bmc->spi_model); 1163 bmc->spi_model = g_strdup(value); 1164 } 1165 1166 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1167 { 1168 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1169 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1170 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1171 1172 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1173 } 1174 1175 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1176 { 1177 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1178 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1179 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1180 int val; 1181 int uart_first = aspeed_uart_first(sc); 1182 int uart_last = aspeed_uart_last(sc); 1183 1184 if (sscanf(value, "uart%u", &val) != 1) { 1185 error_setg(errp, "Bad value for \"uart\" property"); 1186 return; 1187 } 1188 1189 /* The number of UART depends on the SoC */ 1190 if (val < uart_first || val > uart_last) { 1191 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1192 uart_first, uart_last); 1193 return; 1194 } 1195 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1196 } 1197 1198 static void aspeed_machine_class_props_init(ObjectClass *oc) 1199 { 1200 object_class_property_add_bool(oc, "execute-in-place", 1201 aspeed_get_mmio_exec, 1202 aspeed_set_mmio_exec); 1203 object_class_property_set_description(oc, "execute-in-place", 1204 "boot directly from CE0 flash device"); 1205 1206 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1207 aspeed_set_bmc_console); 1208 object_class_property_set_description(oc, "bmc-console", 1209 "Change the default UART to \"uartX\""); 1210 1211 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1212 aspeed_set_fmc_model); 1213 object_class_property_set_description(oc, "fmc-model", 1214 "Change the FMC Flash model"); 1215 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1216 aspeed_set_spi_model); 1217 object_class_property_set_description(oc, "spi-model", 1218 "Change the SPI Flash model"); 1219 } 1220 1221 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1222 { 1223 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1224 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1225 1226 mc->default_cpus = sc->num_cpus; 1227 mc->min_cpus = sc->num_cpus; 1228 mc->max_cpus = sc->num_cpus; 1229 mc->valid_cpu_types = sc->valid_cpu_types; 1230 } 1231 1232 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1233 { 1234 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1235 1236 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1237 } 1238 1239 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1240 Error **errp) 1241 { 1242 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1243 1244 if (value) { 1245 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1246 } else { 1247 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1248 } 1249 } 1250 1251 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1252 { 1253 object_class_property_add_bool(oc, "boot-emmc", 1254 aspeed_machine_ast2600_get_boot_from_emmc, 1255 aspeed_machine_ast2600_set_boot_from_emmc); 1256 object_class_property_set_description(oc, "boot-emmc", 1257 "Set or unset boot from EMMC"); 1258 } 1259 1260 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1261 { 1262 MachineClass *mc = MACHINE_CLASS(oc); 1263 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1264 1265 mc->init = aspeed_machine_init; 1266 mc->no_floppy = 1; 1267 mc->no_cdrom = 1; 1268 mc->no_parallel = 1; 1269 mc->default_ram_id = "ram"; 1270 amc->macs_mask = ASPEED_MAC0_ON; 1271 amc->uart_default = ASPEED_DEV_UART5; 1272 1273 aspeed_machine_class_props_init(oc); 1274 } 1275 1276 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(oc); 1279 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1280 1281 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1282 amc->soc_name = "ast2400-a1"; 1283 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1284 amc->fmc_model = "n25q256a"; 1285 amc->spi_model = "mx25l25635f"; 1286 amc->num_cs = 1; 1287 amc->i2c_init = palmetto_bmc_i2c_init; 1288 mc->default_ram_size = 256 * MiB; 1289 aspeed_machine_class_init_cpus_defaults(mc); 1290 }; 1291 1292 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1293 { 1294 MachineClass *mc = MACHINE_CLASS(oc); 1295 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1296 1297 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1298 amc->soc_name = "ast2400-a1"; 1299 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1300 amc->fmc_model = "n25q256a"; 1301 amc->spi_model = "mx25l25635e"; 1302 amc->num_cs = 1; 1303 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1304 mc->default_ram_size = 128 * MiB; 1305 aspeed_machine_class_init_cpus_defaults(mc); 1306 } 1307 1308 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1309 void *data) 1310 { 1311 MachineClass *mc = MACHINE_CLASS(oc); 1312 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1313 1314 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1315 amc->soc_name = "ast2400-a1"; 1316 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1317 amc->fmc_model = "mx25l25635e"; 1318 amc->spi_model = "mx25l25635e"; 1319 amc->num_cs = 1; 1320 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1321 amc->i2c_init = palmetto_bmc_i2c_init; 1322 mc->default_ram_size = 256 * MiB; 1323 aspeed_machine_class_init_cpus_defaults(mc); 1324 } 1325 1326 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1327 void *data) 1328 { 1329 MachineClass *mc = MACHINE_CLASS(oc); 1330 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1331 1332 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1333 amc->soc_name = "ast2500-a1"; 1334 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1335 amc->fmc_model = "mx25l25635e"; 1336 amc->spi_model = "mx25l25635e"; 1337 amc->num_cs = 1; 1338 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1339 amc->i2c_init = palmetto_bmc_i2c_init; 1340 mc->default_ram_size = 512 * MiB; 1341 aspeed_machine_class_init_cpus_defaults(mc); 1342 } 1343 1344 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1345 { 1346 MachineClass *mc = MACHINE_CLASS(oc); 1347 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1348 1349 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1350 amc->soc_name = "ast2500-a1"; 1351 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1352 amc->fmc_model = "mx25l25635e"; 1353 amc->spi_model = "mx25l25635f"; 1354 amc->num_cs = 1; 1355 amc->i2c_init = ast2500_evb_i2c_init; 1356 mc->default_ram_size = 512 * MiB; 1357 aspeed_machine_class_init_cpus_defaults(mc); 1358 }; 1359 1360 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1361 { 1362 MachineClass *mc = MACHINE_CLASS(oc); 1363 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1364 1365 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1366 amc->soc_name = "ast2500-a1"; 1367 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1368 amc->hw_strap2 = 0; 1369 amc->fmc_model = "n25q256a"; 1370 amc->spi_model = "mx25l25635e"; 1371 amc->num_cs = 2; 1372 amc->i2c_init = yosemitev2_bmc_i2c_init; 1373 mc->default_ram_size = 512 * MiB; 1374 aspeed_machine_class_init_cpus_defaults(mc); 1375 }; 1376 1377 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1378 { 1379 MachineClass *mc = MACHINE_CLASS(oc); 1380 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1381 1382 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1383 amc->soc_name = "ast2500-a1"; 1384 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1385 amc->fmc_model = "n25q256a"; 1386 amc->spi_model = "mx66l1g45g"; 1387 amc->num_cs = 2; 1388 amc->i2c_init = romulus_bmc_i2c_init; 1389 mc->default_ram_size = 512 * MiB; 1390 aspeed_machine_class_init_cpus_defaults(mc); 1391 }; 1392 1393 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1394 { 1395 MachineClass *mc = MACHINE_CLASS(oc); 1396 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1397 1398 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1399 amc->soc_name = "ast2500-a1"; 1400 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1401 amc->hw_strap2 = 0; 1402 amc->fmc_model = "n25q256a"; 1403 amc->spi_model = "mx25l25635e"; 1404 amc->num_cs = 2; 1405 amc->i2c_init = tiogapass_bmc_i2c_init; 1406 mc->default_ram_size = 1 * GiB; 1407 aspeed_machine_class_init_cpus_defaults(mc); 1408 }; 1409 1410 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1411 { 1412 MachineClass *mc = MACHINE_CLASS(oc); 1413 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1414 1415 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1416 amc->soc_name = "ast2500-a1"; 1417 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1418 amc->fmc_model = "mx66l1g45g"; 1419 amc->spi_model = "mx66l1g45g"; 1420 amc->num_cs = 2; 1421 amc->i2c_init = sonorapass_bmc_i2c_init; 1422 mc->default_ram_size = 512 * MiB; 1423 aspeed_machine_class_init_cpus_defaults(mc); 1424 }; 1425 1426 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1427 { 1428 MachineClass *mc = MACHINE_CLASS(oc); 1429 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1430 1431 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1432 amc->soc_name = "ast2500-a1"; 1433 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1434 amc->fmc_model = "mx25l25635f"; 1435 amc->spi_model = "mx66l1g45g"; 1436 amc->num_cs = 2; 1437 amc->i2c_init = witherspoon_bmc_i2c_init; 1438 mc->default_ram_size = 512 * MiB; 1439 aspeed_machine_class_init_cpus_defaults(mc); 1440 }; 1441 1442 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1443 { 1444 MachineClass *mc = MACHINE_CLASS(oc); 1445 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1446 1447 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1448 amc->soc_name = "ast2600-a3"; 1449 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1450 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1451 amc->fmc_model = "mx66u51235f"; 1452 amc->spi_model = "mx66u51235f"; 1453 amc->num_cs = 1; 1454 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1455 ASPEED_MAC3_ON; 1456 amc->sdhci_wp_inverted = true; 1457 amc->i2c_init = ast2600_evb_i2c_init; 1458 mc->default_ram_size = 1 * GiB; 1459 aspeed_machine_class_init_cpus_defaults(mc); 1460 aspeed_machine_ast2600_class_emmc_init(oc); 1461 }; 1462 1463 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1464 { 1465 MachineClass *mc = MACHINE_CLASS(oc); 1466 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1467 1468 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1469 amc->soc_name = "ast2500-a1"; 1470 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1471 amc->fmc_model = "n25q512a"; 1472 amc->spi_model = "mx25l25635e"; 1473 amc->num_cs = 2; 1474 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1475 amc->i2c_init = g220a_bmc_i2c_init; 1476 mc->default_ram_size = 1024 * MiB; 1477 aspeed_machine_class_init_cpus_defaults(mc); 1478 }; 1479 1480 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1481 { 1482 MachineClass *mc = MACHINE_CLASS(oc); 1483 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1484 1485 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1486 amc->soc_name = "ast2500-a1"; 1487 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1488 amc->fmc_model = "n25q512a"; 1489 amc->spi_model = "mx25l25635e"; 1490 amc->num_cs = 2; 1491 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1492 amc->i2c_init = fp5280g2_bmc_i2c_init; 1493 mc->default_ram_size = 512 * MiB; 1494 aspeed_machine_class_init_cpus_defaults(mc); 1495 }; 1496 1497 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1498 { 1499 MachineClass *mc = MACHINE_CLASS(oc); 1500 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1501 1502 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1503 amc->soc_name = "ast2600-a3"; 1504 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1505 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1506 amc->fmc_model = "mx66l1g45g"; 1507 amc->spi_model = "mx66l1g45g"; 1508 amc->num_cs = 2; 1509 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1510 amc->i2c_init = rainier_bmc_i2c_init; 1511 mc->default_ram_size = 1 * GiB; 1512 aspeed_machine_class_init_cpus_defaults(mc); 1513 aspeed_machine_ast2600_class_emmc_init(oc); 1514 }; 1515 1516 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1517 1518 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1519 { 1520 MachineClass *mc = MACHINE_CLASS(oc); 1521 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1522 1523 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1524 amc->soc_name = "ast2600-a3"; 1525 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1526 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1527 amc->fmc_model = "mx66l1g45g"; 1528 amc->spi_model = "mx66l1g45g"; 1529 amc->num_cs = 2; 1530 amc->macs_mask = ASPEED_MAC3_ON; 1531 amc->i2c_init = fuji_bmc_i2c_init; 1532 amc->uart_default = ASPEED_DEV_UART1; 1533 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1534 aspeed_machine_class_init_cpus_defaults(mc); 1535 }; 1536 1537 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1538 1539 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1540 { 1541 MachineClass *mc = MACHINE_CLASS(oc); 1542 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1543 1544 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1545 amc->soc_name = "ast2600-a3"; 1546 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1547 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1548 amc->fmc_model = "w25q01jvq"; 1549 amc->spi_model = NULL; 1550 amc->num_cs = 2; 1551 amc->macs_mask = ASPEED_MAC2_ON; 1552 amc->i2c_init = bletchley_bmc_i2c_init; 1553 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1554 aspeed_machine_class_init_cpus_defaults(mc); 1555 } 1556 1557 static void fby35_reset(MachineState *state, ResetType type) 1558 { 1559 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1560 AspeedGPIOState *gpio = &bmc->soc->gpio; 1561 1562 qemu_devices_reset(type); 1563 1564 /* Board ID: 7 (Class-1, 4 slots) */ 1565 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1566 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1567 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1568 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1569 1570 /* Slot presence pins, inverse polarity. (False means present) */ 1571 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1572 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1573 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1574 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1575 1576 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1577 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1578 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1579 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1580 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1581 } 1582 1583 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1584 { 1585 MachineClass *mc = MACHINE_CLASS(oc); 1586 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1587 1588 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1589 mc->reset = fby35_reset; 1590 amc->fmc_model = "mx66l1g45g"; 1591 amc->num_cs = 2; 1592 amc->macs_mask = ASPEED_MAC3_ON; 1593 amc->i2c_init = fby35_i2c_init; 1594 /* FIXME: Replace this macro with something more general */ 1595 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1596 aspeed_machine_class_init_cpus_defaults(mc); 1597 } 1598 1599 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1600 /* Main SYSCLK frequency in Hz (200MHz) */ 1601 #define SYSCLK_FRQ 200000000ULL 1602 1603 static void aspeed_minibmc_machine_init(MachineState *machine) 1604 { 1605 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1606 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1607 Clock *sysclk; 1608 1609 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1610 clock_set_hz(sysclk, SYSCLK_FRQ); 1611 1612 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1613 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1614 object_unref(OBJECT(bmc->soc)); 1615 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1616 1617 object_property_set_link(OBJECT(bmc->soc), "memory", 1618 OBJECT(get_system_memory()), &error_abort); 1619 connect_serial_hds_to_uarts(bmc); 1620 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1621 1622 if (defaults_enabled()) { 1623 aspeed_board_init_flashes(&bmc->soc->fmc, 1624 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1625 amc->num_cs, 1626 0); 1627 1628 aspeed_board_init_flashes(&bmc->soc->spi[0], 1629 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1630 amc->num_cs, amc->num_cs); 1631 1632 aspeed_board_init_flashes(&bmc->soc->spi[1], 1633 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1634 amc->num_cs, (amc->num_cs * 2)); 1635 } 1636 1637 if (amc->i2c_init) { 1638 amc->i2c_init(bmc); 1639 } 1640 1641 armv7m_load_kernel(ARM_CPU(first_cpu), 1642 machine->kernel_filename, 1643 0, 1644 AST1030_INTERNAL_FLASH_SIZE); 1645 } 1646 1647 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1648 { 1649 AspeedSoCState *soc = bmc->soc; 1650 1651 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1652 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1653 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1654 1655 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1656 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1657 } 1658 1659 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1660 void *data) 1661 { 1662 MachineClass *mc = MACHINE_CLASS(oc); 1663 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1664 1665 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1666 amc->soc_name = "ast1030-a1"; 1667 amc->hw_strap1 = 0; 1668 amc->hw_strap2 = 0; 1669 mc->init = aspeed_minibmc_machine_init; 1670 amc->i2c_init = ast1030_evb_i2c_init; 1671 mc->default_ram_size = 0; 1672 amc->fmc_model = "w25q80bl"; 1673 amc->spi_model = "w25q256"; 1674 amc->num_cs = 2; 1675 amc->macs_mask = 0; 1676 aspeed_machine_class_init_cpus_defaults(mc); 1677 } 1678 1679 #ifdef TARGET_AARCH64 1680 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1681 { 1682 AspeedSoCState *soc = bmc->soc; 1683 1684 /* LM75 is compatible with TMP105 driver */ 1685 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1686 TYPE_TMP105, 0x4d); 1687 } 1688 1689 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1690 { 1691 MachineClass *mc = MACHINE_CLASS(oc); 1692 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1693 1694 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1695 amc->soc_name = "ast2700-a0"; 1696 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1697 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1698 amc->fmc_model = "w25q01jvq"; 1699 amc->spi_model = "w25q512jv"; 1700 amc->num_cs = 2; 1701 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1702 amc->uart_default = ASPEED_DEV_UART12; 1703 amc->i2c_init = ast2700_evb_i2c_init; 1704 mc->default_ram_size = 1 * GiB; 1705 aspeed_machine_class_init_cpus_defaults(mc); 1706 } 1707 #endif 1708 1709 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1710 void *data) 1711 { 1712 MachineClass *mc = MACHINE_CLASS(oc); 1713 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1714 1715 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1716 amc->soc_name = "ast2600-a3"; 1717 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1718 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1719 amc->fmc_model = "n25q512a"; 1720 amc->spi_model = "n25q512a"; 1721 amc->num_cs = 2; 1722 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1723 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1724 mc->default_ram_size = 1 * GiB; 1725 aspeed_machine_class_init_cpus_defaults(mc); 1726 }; 1727 1728 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1729 void *data) 1730 { 1731 MachineClass *mc = MACHINE_CLASS(oc); 1732 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1733 1734 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1735 amc->soc_name = "ast2600-a3"; 1736 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1737 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1738 amc->fmc_model = "n25q512a"; 1739 amc->spi_model = "n25q512a"; 1740 amc->num_cs = 2; 1741 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1742 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1743 mc->default_ram_size = 1 * GiB; 1744 aspeed_machine_class_init_cpus_defaults(mc); 1745 }; 1746 1747 static const TypeInfo aspeed_machine_types[] = { 1748 { 1749 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1750 .parent = TYPE_ASPEED_MACHINE, 1751 .class_init = aspeed_machine_palmetto_class_init, 1752 }, { 1753 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1754 .parent = TYPE_ASPEED_MACHINE, 1755 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1756 }, { 1757 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1758 .parent = TYPE_ASPEED_MACHINE, 1759 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1760 }, { 1761 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1762 .parent = TYPE_ASPEED_MACHINE, 1763 .class_init = aspeed_machine_ast2500_evb_class_init, 1764 }, { 1765 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1766 .parent = TYPE_ASPEED_MACHINE, 1767 .class_init = aspeed_machine_romulus_class_init, 1768 }, { 1769 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1770 .parent = TYPE_ASPEED_MACHINE, 1771 .class_init = aspeed_machine_sonorapass_class_init, 1772 }, { 1773 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1774 .parent = TYPE_ASPEED_MACHINE, 1775 .class_init = aspeed_machine_witherspoon_class_init, 1776 }, { 1777 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1778 .parent = TYPE_ASPEED_MACHINE, 1779 .class_init = aspeed_machine_ast2600_evb_class_init, 1780 }, { 1781 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1782 .parent = TYPE_ASPEED_MACHINE, 1783 .class_init = aspeed_machine_yosemitev2_class_init, 1784 }, { 1785 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1786 .parent = TYPE_ASPEED_MACHINE, 1787 .class_init = aspeed_machine_tiogapass_class_init, 1788 }, { 1789 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1790 .parent = TYPE_ASPEED_MACHINE, 1791 .class_init = aspeed_machine_g220a_class_init, 1792 }, { 1793 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1794 .parent = TYPE_ASPEED_MACHINE, 1795 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1796 }, { 1797 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1798 .parent = TYPE_ASPEED_MACHINE, 1799 .class_init = aspeed_machine_qcom_firework_class_init, 1800 }, { 1801 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1802 .parent = TYPE_ASPEED_MACHINE, 1803 .class_init = aspeed_machine_fp5280g2_class_init, 1804 }, { 1805 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1806 .parent = TYPE_ASPEED_MACHINE, 1807 .class_init = aspeed_machine_quanta_q71l_class_init, 1808 }, { 1809 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1810 .parent = TYPE_ASPEED_MACHINE, 1811 .class_init = aspeed_machine_rainier_class_init, 1812 }, { 1813 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1814 .parent = TYPE_ASPEED_MACHINE, 1815 .class_init = aspeed_machine_fuji_class_init, 1816 }, { 1817 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1818 .parent = TYPE_ASPEED_MACHINE, 1819 .class_init = aspeed_machine_bletchley_class_init, 1820 }, { 1821 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1822 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1823 .class_init = aspeed_machine_fby35_class_init, 1824 }, { 1825 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1826 .parent = TYPE_ASPEED_MACHINE, 1827 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1828 #ifdef TARGET_AARCH64 1829 }, { 1830 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1831 .parent = TYPE_ASPEED_MACHINE, 1832 .class_init = aspeed_machine_ast2700_evb_class_init, 1833 #endif 1834 }, { 1835 .name = TYPE_ASPEED_MACHINE, 1836 .parent = TYPE_MACHINE, 1837 .instance_size = sizeof(AspeedMachineState), 1838 .instance_init = aspeed_machine_instance_init, 1839 .class_size = sizeof(AspeedMachineClass), 1840 .class_init = aspeed_machine_class_init, 1841 .abstract = true, 1842 } 1843 }; 1844 1845 DEFINE_TYPES(aspeed_machine_types) 1846