1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "cpu.h" 15 #include "exec/address-spaces.h" 16 #include "hw/arm/boot.h" 17 #include "hw/arm/aspeed.h" 18 #include "hw/arm/aspeed_soc.h" 19 #include "hw/boards.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/misc/pca9552.h" 22 #include "hw/misc/tmp105.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/log.h" 25 #include "sysemu/block-backend.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/loader.h" 28 #include "qemu/error-report.h" 29 #include "qemu/units.h" 30 31 static struct arm_boot_info aspeed_board_binfo = { 32 .board_id = -1, /* device-tree-only board */ 33 }; 34 35 struct AspeedBoardState { 36 AspeedSoCState soc; 37 MemoryRegion ram_container; 38 MemoryRegion max_ram; 39 }; 40 41 /* Palmetto hardware value: 0x120CE416 */ 42 #define PALMETTO_BMC_HW_STRAP1 ( \ 43 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 44 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 45 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 46 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 47 SCU_HW_STRAP_VGA_CLASS_CODE | \ 48 SCU_HW_STRAP_LPC_RESET_PIN | \ 49 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 50 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 51 SCU_HW_STRAP_SPI_WIDTH | \ 52 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 53 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 54 55 /* AST2500 evb hardware value: 0xF100C2E6 */ 56 #define AST2500_EVB_HW_STRAP1 (( \ 57 AST2500_HW_STRAP1_DEFAULTS | \ 58 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 59 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 60 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 61 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 62 SCU_HW_STRAP_MAC1_RGMII | \ 63 SCU_HW_STRAP_MAC0_RGMII) & \ 64 ~SCU_HW_STRAP_2ND_BOOT_WDT) 65 66 /* Romulus hardware value: 0xF10AD206 */ 67 #define ROMULUS_BMC_HW_STRAP1 ( \ 68 AST2500_HW_STRAP1_DEFAULTS | \ 69 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 70 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 71 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 72 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 73 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 74 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 75 76 /* Swift hardware value: 0xF11AD206 */ 77 #define SWIFT_BMC_HW_STRAP1 ( \ 78 AST2500_HW_STRAP1_DEFAULTS | \ 79 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 80 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 81 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 82 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 83 SCU_H_PLL_BYPASS_EN | \ 84 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 85 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 86 87 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 88 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 89 90 /* AST2600 evb hardware value */ 91 #define AST2600_EVB_HW_STRAP1 0x000000C0 92 #define AST2600_EVB_HW_STRAP2 0x00000003 93 94 /* Tacoma hardware value */ 95 #define TACOMA_BMC_HW_STRAP1 0x00000000 96 #define TACOMA_BMC_HW_STRAP2 0x00000040 97 98 /* 99 * The max ram region is for firmwares that scan the address space 100 * with load/store to guess how much RAM the SoC has. 101 */ 102 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) 103 { 104 return 0; 105 } 106 107 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, 108 unsigned size) 109 { 110 /* Discard writes */ 111 } 112 113 static const MemoryRegionOps max_ram_ops = { 114 .read = max_ram_read, 115 .write = max_ram_write, 116 .endianness = DEVICE_NATIVE_ENDIAN, 117 }; 118 119 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 120 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 121 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 122 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 123 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 124 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 125 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 126 127 static void aspeed_write_smpboot(ARMCPU *cpu, 128 const struct arm_boot_info *info) 129 { 130 static const uint32_t poll_mailbox_ready[] = { 131 /* 132 * r2 = per-cpu go sign value 133 * r1 = AST_SMP_MBOX_FIELD_ENTRY 134 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 135 */ 136 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ 137 0xe21000ff, /* ands r0, r0, #255 */ 138 0xe59f201c, /* ldr r2, [pc, #28] */ 139 0xe1822000, /* orr r2, r2, r0 */ 140 141 0xe59f1018, /* ldr r1, [pc, #24] */ 142 0xe59f0018, /* ldr r0, [pc, #24] */ 143 144 0xe320f002, /* wfe */ 145 0xe5904000, /* ldr r4, [r0] */ 146 0xe1520004, /* cmp r2, r4 */ 147 0x1afffffb, /* bne <wfe> */ 148 0xe591f000, /* ldr pc, [r1] */ 149 AST_SMP_MBOX_GOSIGN, 150 AST_SMP_MBOX_FIELD_ENTRY, 151 AST_SMP_MBOX_FIELD_GOSIGN, 152 }; 153 154 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, 155 sizeof(poll_mailbox_ready), 156 info->smp_loader_start); 157 } 158 159 static void aspeed_reset_secondary(ARMCPU *cpu, 160 const struct arm_boot_info *info) 161 { 162 AddressSpace *as = arm_boot_address_space(cpu, info); 163 CPUState *cs = CPU(cpu); 164 165 /* info->smp_bootreg_addr */ 166 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 167 MEMTXATTRS_UNSPECIFIED, NULL); 168 cpu_set_pc(cs, info->smp_loader_start); 169 } 170 171 #define FIRMWARE_ADDR 0x0 172 173 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, 174 Error **errp) 175 { 176 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 177 uint8_t *storage; 178 int64_t size; 179 180 /* The block backend size should have already been 'validated' by 181 * the creation of the m25p80 object. 182 */ 183 size = blk_getlength(blk); 184 if (size <= 0) { 185 error_setg(errp, "failed to get flash size"); 186 return; 187 } 188 189 if (rom_size > size) { 190 rom_size = size; 191 } 192 193 storage = g_new0(uint8_t, rom_size); 194 if (blk_pread(blk, 0, storage, rom_size) < 0) { 195 error_setg(errp, "failed to read the initial flash content"); 196 return; 197 } 198 199 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 200 g_free(storage); 201 } 202 203 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 204 Error **errp) 205 { 206 int i ; 207 208 for (i = 0; i < s->num_cs; ++i) { 209 AspeedSMCFlash *fl = &s->flashes[i]; 210 DriveInfo *dinfo = drive_get_next(IF_MTD); 211 qemu_irq cs_line; 212 213 fl->flash = ssi_create_slave_no_init(s->spi, flashtype); 214 if (dinfo) { 215 qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), 216 errp); 217 } 218 qdev_init_nofail(fl->flash); 219 220 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); 221 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); 222 } 223 } 224 225 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) 226 { 227 DeviceState *card; 228 229 card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 230 TYPE_SD_CARD); 231 if (dinfo) { 232 qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), 233 &error_fatal); 234 } 235 object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); 236 } 237 238 static void aspeed_machine_init(MachineState *machine) 239 { 240 AspeedBoardState *bmc; 241 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 242 AspeedSoCClass *sc; 243 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); 244 ram_addr_t max_ram_size; 245 int i; 246 247 bmc = g_new0(AspeedBoardState, 1); 248 249 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 250 UINT32_MAX); 251 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 252 253 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 254 (sizeof(bmc->soc)), amc->soc_name, &error_abort, 255 NULL); 256 257 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 258 259 /* 260 * This will error out if isize is not supported by memory controller. 261 */ 262 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 263 &error_fatal); 264 265 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 266 &error_abort); 267 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", 268 &error_abort); 269 object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", 270 &error_abort); 271 object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", 272 &error_abort); 273 object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 274 "dram", &error_abort); 275 if (machine->kernel_filename) { 276 /* 277 * When booting with a -kernel command line there is no u-boot 278 * that runs to unlock the SCU. In this case set the default to 279 * be unlocked as the kernel expects 280 */ 281 object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 282 "hw-prot-key", &error_abort); 283 } 284 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 285 &error_abort); 286 287 memory_region_add_subregion(get_system_memory(), 288 sc->memmap[ASPEED_SDRAM], 289 &bmc->ram_container); 290 291 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", 292 &error_abort); 293 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, 294 "max_ram", max_ram_size - ram_size); 295 memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); 296 297 aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model, &error_abort); 298 aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model, &error_abort); 299 300 /* Install first FMC flash content as a boot rom. */ 301 if (drive0) { 302 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; 303 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 304 305 /* 306 * create a ROM region using the default mapping window size of 307 * the flash module. The window size is 64MB for the AST2400 308 * SoC and 128MB for the AST2500 SoC, which is twice as big as 309 * needed by the flash modules of the Aspeed machines. 310 */ 311 if (ASPEED_MACHINE(machine)->mmio_exec) { 312 memory_region_init_alias(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 313 &fl->mmio, 0, fl->size); 314 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 315 boot_rom); 316 } else { 317 memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", 318 fl->size, &error_abort); 319 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, 320 boot_rom); 321 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); 322 } 323 } 324 325 if (machine->kernel_filename && bmc->soc.num_cpus > 1) { 326 /* With no u-boot we must set up a boot stub for the secondary CPU */ 327 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 328 memory_region_init_ram(smpboot, OBJECT(bmc), "aspeed.smpboot", 329 0x80, &error_abort); 330 memory_region_add_subregion(get_system_memory(), 331 AST_SMP_MAILBOX_BASE, smpboot); 332 333 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 334 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 335 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 336 } 337 338 aspeed_board_binfo.ram_size = ram_size; 339 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM]; 340 aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus; 341 342 if (amc->i2c_init) { 343 amc->i2c_init(bmc); 344 } 345 346 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { 347 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); 348 } 349 350 if (bmc->soc.emmc.num_slots) { 351 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); 352 } 353 354 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 355 } 356 357 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) 358 { 359 AspeedSoCState *soc = &bmc->soc; 360 DeviceState *dev; 361 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 362 363 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 364 * enough to provide basic RTC features. Alarms will be missing */ 365 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); 366 367 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50, 368 eeprom_buf); 369 370 /* add a TMP423 temperature sensor */ 371 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 372 "tmp423", 0x4c); 373 object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 374 object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 375 object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 376 object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 377 } 378 379 static void ast2500_evb_i2c_init(AspeedBoardState *bmc) 380 { 381 AspeedSoCState *soc = &bmc->soc; 382 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 383 384 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50, 385 eeprom_buf); 386 387 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 388 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), 389 TYPE_TMP105, 0x4d); 390 391 /* The AST2500 EVB does not have an RTC. Let's pretend that one is 392 * plugged on the I2C bus header */ 393 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 394 } 395 396 static void ast2600_evb_i2c_init(AspeedBoardState *bmc) 397 { 398 /* Start with some devices on our I2C busses */ 399 ast2500_evb_i2c_init(bmc); 400 } 401 402 static void romulus_bmc_i2c_init(AspeedBoardState *bmc) 403 { 404 AspeedSoCState *soc = &bmc->soc; 405 406 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 407 * good enough */ 408 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 409 } 410 411 static void swift_bmc_i2c_init(AspeedBoardState *bmc) 412 { 413 AspeedSoCState *soc = &bmc->soc; 414 415 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); 416 417 /* The swift board expects a TMP275 but a TMP105 is compatible */ 418 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x48); 419 /* The swift board expects a pca9551 but a pca9552 is compatible */ 420 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "pca9552", 0x60); 421 422 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ 423 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "ds1338", 0x32); 424 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 8), "pca9552", 0x60); 425 426 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp423", 0x4c); 427 /* The swift board expects a pca9539 but a pca9552 is compatible */ 428 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "pca9552", 0x74); 429 430 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "tmp423", 0x4c); 431 /* The swift board expects a pca9539 but a pca9552 is compatible */ 432 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 10), "pca9552", 433 0x74); 434 435 /* The swift board expects a TMP275 but a TMP105 is compatible */ 436 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x48); 437 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 12), "tmp105", 0x4a); 438 } 439 440 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) 441 { 442 AspeedSoCState *soc = &bmc->soc; 443 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 444 445 /* Bus 3: TODO bmp280@77 */ 446 /* Bus 3: TODO max31785@52 */ 447 /* Bus 3: TODO dps310@76 */ 448 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, 449 0x60); 450 451 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); 452 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); 453 454 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 455 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, 456 0x4a); 457 458 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 459 * good enough */ 460 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); 461 462 smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, 463 eeprom_buf); 464 i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, 465 0x60); 466 /* Bus 11: TODO ucd90160@64 */ 467 } 468 469 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 470 { 471 return ASPEED_MACHINE(obj)->mmio_exec; 472 } 473 474 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 475 { 476 ASPEED_MACHINE(obj)->mmio_exec = value; 477 } 478 479 static void aspeed_machine_instance_init(Object *obj) 480 { 481 ASPEED_MACHINE(obj)->mmio_exec = false; 482 } 483 484 static void aspeed_machine_class_props_init(ObjectClass *oc) 485 { 486 object_class_property_add_bool(oc, "execute-in-place", 487 aspeed_get_mmio_exec, 488 aspeed_set_mmio_exec, &error_abort); 489 object_class_property_set_description(oc, "execute-in-place", 490 "boot directly from CE0 flash device", &error_abort); 491 } 492 493 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 494 { 495 MachineClass *mc = MACHINE_CLASS(oc); 496 497 mc->init = aspeed_machine_init; 498 mc->max_cpus = ASPEED_CPUS_NUM; 499 mc->no_floppy = 1; 500 mc->no_cdrom = 1; 501 mc->no_parallel = 1; 502 mc->default_ram_id = "ram"; 503 504 aspeed_machine_class_props_init(oc); 505 } 506 507 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 508 { 509 MachineClass *mc = MACHINE_CLASS(oc); 510 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 511 512 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 513 amc->soc_name = "ast2400-a1"; 514 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 515 amc->fmc_model = "n25q256a"; 516 amc->spi_model = "mx25l25635e"; 517 amc->num_cs = 1; 518 amc->i2c_init = palmetto_bmc_i2c_init; 519 mc->default_ram_size = 256 * MiB; 520 }; 521 522 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 523 { 524 MachineClass *mc = MACHINE_CLASS(oc); 525 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 526 527 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 528 amc->soc_name = "ast2500-a1"; 529 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 530 amc->fmc_model = "w25q256"; 531 amc->spi_model = "mx25l25635e"; 532 amc->num_cs = 1; 533 amc->i2c_init = ast2500_evb_i2c_init; 534 mc->default_ram_size = 512 * MiB; 535 }; 536 537 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 538 { 539 MachineClass *mc = MACHINE_CLASS(oc); 540 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 541 542 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 543 amc->soc_name = "ast2500-a1"; 544 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 545 amc->fmc_model = "n25q256a"; 546 amc->spi_model = "mx66l1g45g"; 547 amc->num_cs = 2; 548 amc->i2c_init = romulus_bmc_i2c_init; 549 mc->default_ram_size = 512 * MiB; 550 }; 551 552 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) 553 { 554 MachineClass *mc = MACHINE_CLASS(oc); 555 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 556 557 mc->desc = "OpenPOWER Swift BMC (ARM1176)"; 558 amc->soc_name = "ast2500-a1"; 559 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; 560 amc->fmc_model = "mx66l1g45g"; 561 amc->spi_model = "mx66l1g45g"; 562 amc->num_cs = 2; 563 amc->i2c_init = swift_bmc_i2c_init; 564 mc->default_ram_size = 512 * MiB; 565 }; 566 567 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 568 { 569 MachineClass *mc = MACHINE_CLASS(oc); 570 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 571 572 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 573 amc->soc_name = "ast2500-a1"; 574 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 575 amc->fmc_model = "mx25l25635e"; 576 amc->spi_model = "mx66l1g45g"; 577 amc->num_cs = 2; 578 amc->i2c_init = witherspoon_bmc_i2c_init; 579 mc->default_ram_size = 512 * MiB; 580 }; 581 582 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 583 { 584 MachineClass *mc = MACHINE_CLASS(oc); 585 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 586 587 mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; 588 amc->soc_name = "ast2600-a1"; 589 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 590 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 591 amc->fmc_model = "w25q512jv"; 592 amc->spi_model = "mx66u51235f"; 593 amc->num_cs = 1; 594 amc->i2c_init = ast2600_evb_i2c_init; 595 mc->default_ram_size = 1 * GiB; 596 }; 597 598 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 599 { 600 MachineClass *mc = MACHINE_CLASS(oc); 601 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 602 603 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; 604 amc->soc_name = "ast2600-a1"; 605 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 606 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 607 amc->fmc_model = "mx66l1g45g"; 608 amc->spi_model = "mx66l1g45g"; 609 amc->num_cs = 2; 610 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 611 mc->default_ram_size = 1 * GiB; 612 }; 613 614 static const TypeInfo aspeed_machine_types[] = { 615 { 616 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 617 .parent = TYPE_ASPEED_MACHINE, 618 .class_init = aspeed_machine_palmetto_class_init, 619 }, { 620 .name = MACHINE_TYPE_NAME("ast2500-evb"), 621 .parent = TYPE_ASPEED_MACHINE, 622 .class_init = aspeed_machine_ast2500_evb_class_init, 623 }, { 624 .name = MACHINE_TYPE_NAME("romulus-bmc"), 625 .parent = TYPE_ASPEED_MACHINE, 626 .class_init = aspeed_machine_romulus_class_init, 627 }, { 628 .name = MACHINE_TYPE_NAME("swift-bmc"), 629 .parent = TYPE_ASPEED_MACHINE, 630 .class_init = aspeed_machine_swift_class_init, 631 }, { 632 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 633 .parent = TYPE_ASPEED_MACHINE, 634 .class_init = aspeed_machine_witherspoon_class_init, 635 }, { 636 .name = MACHINE_TYPE_NAME("ast2600-evb"), 637 .parent = TYPE_ASPEED_MACHINE, 638 .class_init = aspeed_machine_ast2600_evb_class_init, 639 }, { 640 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 641 .parent = TYPE_ASPEED_MACHINE, 642 .class_init = aspeed_machine_tacoma_class_init, 643 }, { 644 .name = TYPE_ASPEED_MACHINE, 645 .parent = TYPE_MACHINE, 646 .instance_size = sizeof(AspeedMachine), 647 .instance_init = aspeed_machine_instance_init, 648 .class_size = sizeof(AspeedMachineClass), 649 .class_init = aspeed_machine_class_init, 650 .abstract = true, 651 } 652 }; 653 654 DEFINE_TYPES(aspeed_machine_types) 655